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URL https://opencores.org/ocsvn/mjpeg-decoder/mjpeg-decoder/trunk

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[/] [mjpeg-decoder/] [trunk/] [mjpeg/] [pcores/] [myipif/] [hdl/] [vhdl/] [jpeg.vhd] - Blame information for rev 4

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Line No. Rev Author Line
1 2 smanz 
--------------------------------------------------------------------------------
2 
-- TODO
3 
-- * register all output signals
4 
-- * ??? delay input_fifo_valid by one cycle to match data
5 
--------------------------------------------------------------------------------
6 
 
7 
library ieee;
8 
use ieee.std_logic_1164.all;
9 
use ieee.std_logic_arith.all;
10 
use ieee.std_logic_unsigned.all;
11 
 
12 
 
13 
entity jpeg is
14 
  port(
15 
        Clk                     :  in std_logic;
16 
                data_i          :  in std_logic_vector(31 downto 0);
17 
                reset_i         :  in std_logic;
18 
 
19 
                -- Indicates the detection of an eoi marker at the input side
20 
                -- of the pipeline. This is used to handle the input stream.
21 
                eoi_o                   : out std_logic;
22 
 
23 
                -- The Huffman- and the header-component may run in an error-state
24 
                -- on invalid input data.
25 
                error_o         : out std_logic;
26 
 
27 
                -- data and context at the output side of the pipeline
28 
                context_o       : out std_logic_vector (3 downto 0);
29 
                red_o                   : out STD_LOGIC_VECTOR (7 downto 0);
30 
                green_o         : out STD_LOGIC_VECTOR (7 downto 0);
31 
                blue_o          : out STD_LOGIC_VECTOR (7 downto 0);
32 
                width_o         : out std_logic_vector(15 downto 0);
33 
                height_o                : out std_logic_vector(15 downto 0);
34 
                sampling_o      : out std_logic_vector( 1 downto 0);
35 
 
36 
--              -- debug
37 
--              LEDs                    : out std_logic_vector(3 downto 0);
38 
--              BUTTONs         :  in std_logic_vector(4 downto 0); -- 0:left, 1:right, 2:up, 3:down, 4:center
39 
--              SWITCHEs                :  in std_logic_vector(3 downto 0);
40 
--              -- chipscope-debugging
41 
--              chipscope_o     : out std_logic_vector(127 downto 0);
42 
 
43 
                -- flow controll
44 
                datavalid_i :  in std_logic;
45 
                datavalid_o : out std_logic;
46 
                ready_i         :  in std_logic;
47 
                ready_o         : out std_logic
48 
    );
49 
end entity jpeg;
50 
 
51 
 
52 
 
53 
 
54 
 
55 
architecture IMP of jpeg is
56 
 
57 
-- **********************************************************************************************
58 
-- * Components
59 
-- **********************************************************************************************
60 
 
61 
------------------------------------------------------------
62 
-- FIFO to buffer the input data
63 
------------------------------------------------------------
64 
component jpeg_input_fifo
65 
        port (
66 
        din: IN std_logic_VECTOR(31 downto 0);
67 
        rd_clk: IN std_logic;
68 
        rd_en: IN std_logic;
69 
        rst: IN std_logic;
70 
        wr_clk: IN std_logic;
71 
        wr_en: IN std_logic;
72 
        almost_full: OUT std_logic;
73 
        dout: OUT std_logic_VECTOR(7 downto 0);
74 
        empty: OUT std_logic;
75 
        full: OUT std_logic;
76 
        valid: OUT std_logic);
77 
end component;
78 
------------------------------------------------------------
79 
 
80 
 
81 
------------------------------------------------------------
82 
-- Replaces "FF00" with "FF" and filters out other occurances
83 
-- of "FF", detects eoi markers
84 
------------------------------------------------------------
85 
component jpeg_check_FF is
86 
        port(
87 
                Clk                             : in std_logic;
88 
                reset_i                 : in std_logic;
89 
 
90 
                header_valid_i  : in  std_logic;
91 
                header_select_i: in  std_logic;
92 
                eoi_o                   : out std_logic;
93 
 
94 
                data_i                  : in std_logic_vector(7 downto 0);
95 
                data_o                  : out std_logic_vector(7 downto 0);
96 
 
97 
                -- bit occupancy
98 
                -- 0: header_valid
99 
                -- 1: header_select
100 
                -- 2: end of block
101 
                -- 3: end of image
102 
                context_o               : out std_logic_vector(3 downto 0);
103 
 
104 
                -- flow control
105 
                datavalid_i     : in std_logic;
106 
                datavalid_o     : out std_logic;
107 
                ready_i                 : in  std_logic;
108 
                ready_o                 : out std_logic
109 
        );
110 
end component jpeg_check_FF;
111 
--------------------------------------------------------------
112 
 
113 
 
114 
--------------------------------------------------------------
115 
-- Fifo between checkff and huffman
116 
--------------------------------------------------------------
117 
component jpeg_checkff_fifo
118 
        port (
119 
                din: IN std_logic_VECTOR(11 downto 0);
120 
                rd_clk: IN std_logic;
121 
                rd_en: IN std_logic;
122 
                rst: IN std_logic;
123 
                wr_clk: IN std_logic;
124 
                wr_en: IN std_logic;
125 
                almost_empty: OUT std_logic;
126 
                almost_full: OUT std_logic;
127 
                dout: OUT std_logic_VECTOR(11 downto 0);
128 
                empty: OUT std_logic;
129 
                full: OUT std_logic;
130 
                valid: OUT std_logic
131 
        );
132 
end component;
133 
--------------------------------------------------------------
134 
 
135 
 
136 
--------------------------------------------------------------
137 
-- Huffman decoder.
138 
--------------------------------------------------------------
139 
component jpeg_huffman is
140 
        port(
141 
                Clk                             : in std_logic;
142 
                reset_i                 : in std_logic;
143 
                error_o                 : out std_logic;
144 
                header_select_i : in std_logic;
145 
 
146 
                ht_symbols_wea_i        : in std_logic;
147 
                ht_tables_wea_i : in std_logic;
148 
                ht_select_i                     : in std_logic_vector(2 downto 0);   -- bit 2: dc (low) or ac (high), bit 1 and 0: table-nr.
149 
                ht_tables_address_i                     : in std_logic_vector(7 downto 0);       -- address in bram:   ht_select_o & ht_tables_address_o
150 
                ht_nr_of_symbols_address_i      : in std_logic_vector(3 downto 0);       -- address in distrib-ram:   ht_select_o & ht_nr_of_symbols_address_o
151 
                ht_data_i                       : in std_logic_vector(7 downto 0);
152 
 
153 
                context_i               : in std_logic_vector(3 downto 0);
154 
                data_i                  : in std_logic_vector(7 downto 0);
155 
                context_o               : out std_logic_vector(3 downto 0);
156 
                data_o                  : out std_logic_vector(15 downto 0);
157 
 
158 
                -- header data
159 
                comp1_huff_dc_i : in std_logic_vector(3 downto 0);
160 
                comp2_huff_dc_i : in std_logic_vector(3 downto 0);
161 
                comp3_huff_dc_i : in std_logic_vector(3 downto 0);
162 
                comp1_huff_ac_i : in std_logic_vector(3 downto 0);
163 
                comp2_huff_ac_i : in std_logic_vector(3 downto 0);
164 
                comp3_huff_ac_i : in std_logic_vector(3 downto 0);
165 
                sampling_i      : in std_logic_vector(3 downto 0); -- "00"->gray, "01"->4:2:0, "10"->4:2:2, "11"->4:4:4
166 
 
167 
                -- flow control
168 
                -- datavalid signal valid data in this cycle
169 
                -- ready signals "I am ready in NEXT cycle"
170 
                datavalid_i     : in std_logic;
171 
                datavalid_o     : out std_logic;
172 
                ready_i                 : in  std_logic;
173 
                ready_o                 : out std_logic
174 
        );
175 
end component jpeg_huffman;
176 
--------------------------------------------------------------
177 
 
178 
 
179 
--------------------------------------------------------------
180 
-- Dequantization
181 
--------------------------------------------------------------
182 
component jpeg_dequantize is
183 
        port(
184 
                Clk                             : in std_logic;
185 
                reset_i                 : in std_logic;
186 
 
187 
                context_i               : in  std_logic_vector(3 downto 0);
188 
                data_i                  : in  std_logic_vector(11 downto 0);
189 
                context_o               : out std_logic_vector(3 downto 0);
190 
                data_o                  : out std_logic_vector(11 downto 0);
191 
 
192 
                -- header data
193 
                header_select_i : in std_logic;
194 
                sampling_i                      : in std_logic_vector(3 downto 0);
195 
                qt_wea_i                                : in std_logic;
196 
                qt_select_i                     : in std_logic_vector(1 downto 0);
197 
                qt_data_i                       : in std_logic_vector(7 downto 0);
198 
                comp1_qt_number_i : in std_logic_vector(1 downto 0);
199 
                comp2_qt_number_i : in std_logic_vector(1 downto 0);
200 
                comp3_qt_number_i : in std_logic_vector(1 downto 0);
201 
 
202 
                -- flow control
203 
                datavalid_i     : in std_logic;
204 
                datavalid_o     : out std_logic;
205 
                ready_i                 : in  std_logic;
206 
                ready_o                 : out std_logic
207 
        );
208 
end component jpeg_dequantize;
209 
--------------------------------------------------------------
210 
 
211 
 
212 
--------------------------------------------------------------
213 
-- Address-maping to revert the ZigZag-Order
214 
--------------------------------------------------------------
215 
component jpeg_dezigzag is
216 
        port(
217 
                Clk             : in std_logic;
218 
                context_i: in  std_logic_vector(3 downto 0);
219 
                data_i  : in std_logic_vector(11 downto 0);
220 
                reset_i : in std_logic;
221 
 
222 
                context_o: out std_logic_vector(3 downto 0);
223 
                data_o  : out std_logic_vector(11 downto 0);
224 
 
225 
                -- flow control
226 
                datavalid_i     : in std_logic;
227 
                datavalid_o     : out std_logic;
228 
                ready_i                 : in  std_logic;
229 
                ready_o                 : out std_logic
230 
        );
231 
end component jpeg_dezigzag;
232 
--------------------------------------------------------------
233 
 
234 
 
235 
--------------------------------------------------------------
236 
-- Inverse Discrete Cosine Transformation
237 
-- Core provided by Xilinx, with some additional logic
238 
-- for reverse flow control
239 
--------------------------------------------------------------
240 
component jpeg_idct is
241 
        port(
242 
        Clk                             : in  std_logic;
243 
                reset_i                 : in  std_logic;
244 
                context_i               : in  std_logic_vector( 3 downto 0);
245 
                data_i                  : in  std_logic_vector(11 downto 0);
246 
                context_o               : out std_logic_vector( 3 downto 0);
247 
                data_o                  : out std_logic_vector( 8 downto 0);
248 
                datavalid_i     : in  std_logic;
249 
                datavalid_o     : out std_logic;
250 
                ready_i                 : in  std_logic;
251 
                ready_o                 : out std_logic
252 
        );
253 
end component jpeg_idct;
254 
--------------------------------------------------------------
255 
 
256 
 
257 
--------------------------------------------------------------
258 
-- Upsampling
259 
--------------------------------------------------------------
260 
component jpeg_upsampling is
261 
        port(
262 
                Clk                     : in  std_logic;
263 
                reset_i         : in  std_logic;
264 
                context_i       : in  std_logic_vector(3 downto 0);
265 
                data_i          : in  std_logic_vector(8 downto 0);
266 
                sampling_i      : in  std_logic_vector(3 downto 0);
267 
                context_o       : out std_logic_vector(3 downto 0);
268 
                Y_o                     : out std_logic_vector(8 downto 0);
269 
                Cb_o                    : out std_logic_vector(8 downto 0);
270 
                Cr_o                    : out std_logic_vector(8 downto 0);
271 
                datavalid_i     : in  std_logic;
272 
                datavalid_o     : out std_logic;
273 
                ready_i         : in  std_logic;
274 
                ready_o         : out std_logic
275 
        );
276 
end component jpeg_upsampling;
277 
--------------------------------------------------------------
278 
 
279 
 
280 
--------------------------------------------------------------
281 
-- Color Transformation
282 
--------------------------------------------------------------
283 
component jpeg_YCbCr2RGB is
284 
        port(
285 
                Clk                     : in  std_logic;
286 
                reset_i         : in  std_logic;
287 
                context_i       : in  std_logic_vector(3 downto 0);
288 
                Y_i                     : in  std_logic_vector(8 downto 0);
289 
                Cb_i                    : in  std_logic_vector(8 downto 0);
290 
                Cr_i                    : in  std_logic_vector(8 downto 0);
291 
                context_o       : out std_logic_vector(3 downto 0);
292 
                R_o                     : out std_logic_vector(7 downto 0);
293 
                G_o                     : out std_logic_vector(7 downto 0);
294 
                B_o                     : out std_logic_vector(7 downto 0);
295 
                datavalid_i     : in  std_logic;
296 
                datavalid_o     : out std_logic;
297 
                ready_i         : in  std_logic;
298 
                ready_o         : out std_logic
299 
        );
300 
end component jpeg_YCbCr2RGB;
301 
--------------------------------------------------------------
302 
 
303 
 
304 
------------------------------------------------------------
305 
-- This one first reads out header information,
306 
-- then provides header information
307 
------------------------------------------------------------
308 
component jpeg_header is
309 
        port(
310 
                Clk                     : in std_logic;
311 
                data_i          : in std_logic_vector(7 downto 0);
312 
                datavalid_i     : in std_logic;
313 
                reset_i         : in std_logic;
314 
                eoi_i                   : in std_logic;
315 
 
316 
                header_valid_o  : out std_logic;
317 
                header_select_o: out std_logic;
318 
                header_error_o  : out std_logic;
319 
 
320 
                -- initialize the huffmann tables located in the huffmann-decoder entity
321 
                ht_symbols_wea_o        : out std_logic;
322 
                ht_tables_wea_o : out std_logic;
323 
                ht_select_o                     : out std_logic_vector(2 downto 0);              -- bit 2: dc (low) or ac (high), bit 1 and 0: table-nr.
324 
                ht_tables_address_o                     : out std_logic_vector(7 downto 0);      -- address in bram:   ht_select_o & ht_tables_address_o
325 
                ht_nr_of_symbols_address_o      : out std_logic_vector(3 downto 0);      -- address in distrib-ram:   ht_select_o & ht_nr_of_symbols_address_o
326 
                ht_data_o                       : out std_logic_vector(7 downto 0);
327 
 
328 
                -- initialize the quantization tables located in the dequantize entity
329 
                qt_wea_o                : out std_logic;
330 
                qt_select_o     : out std_logic_vector(1 downto 0);
331 
                qt_data_o       : out std_logic_vector(7 downto 0);
332 
 
333 
                -- sos-field
334 
                comp1_huff_dc_o : out std_logic_vector(3 downto 0);
335 
                comp2_huff_dc_o : out std_logic_vector(3 downto 0);
336 
                comp3_huff_dc_o : out std_logic_vector(3 downto 0);
337 
                comp1_huff_ac_o : out std_logic_vector(3 downto 0);
338 
                comp2_huff_ac_o : out std_logic_vector(3 downto 0);
339 
                comp3_huff_ac_o : out std_logic_vector(3 downto 0);
340 
 
341 
                --sof-field
342 
                height_o                                : out std_logic_vector(15 downto 0);
343 
                width_o                         : out std_logic_vector(15 downto 0);
344 
                sampling_o                      : out std_logic_vector(1 downto 0);      -- "00"->gray, "01"->4:2:0, "10"->4:2:2, "11"->4:4:4
345 
                comp1_qt_number_o       : out std_logic_vector(0 downto 0);
346 
                comp2_qt_number_o       : out std_logic_vector(0 downto 0);
347 
                comp3_qt_number_o       : out std_logic_vector(0 downto 0)
348 
        );
349 
end component jpeg_header;
350 
--------------------------------------------------------------
351 
 
352 
 
353 
 
354 
 
355 
-- **********************************************************************************************
356 
-- * Signals
357 
-- **********************************************************************************************
358 
        signal ready, ready_D : std_logic :='0';
359 
        signal reset, error : std_logic :='0';
360 
 
361 
        -- double width to have old and new values present in pipline in case of picture change
362 
        signal sampling, sampling_D : std_logic_vector(3 downto 0) :=(others=>'0');
363 
        signal width, width_D, height, height_D : std_logic_vector(31 downto 0) :=(others=>'0');
364 
        signal comp1_qt_number, comp1_qt_number_D : std_logic_vector(1 downto 0) := (others=>'0');
365 
        signal comp2_qt_number, comp2_qt_number_D : std_logic_vector(1 downto 0) := (others=>'0');
366 
        signal comp3_qt_number, comp3_qt_number_D : std_logic_vector(1 downto 0) := (others=>'0');
367 
        signal sampling_out : std_logic_vector(1 downto 0) :=(others=>'0');
368 
        signal width_out, height_out : std_logic_vector(15 downto 0) :=(others=>'0');
369 
 
370 
        -- Signals to connect the pipeline components. The signals are named after the component
371 
        -- from which it originates.
372 
        signal check_FF_ready : std_logic :='0';
373 
        signal check_FF_data : std_logic_vector(7 downto 0) := (others=>'0');
374 
        signal check_FF_datavalid : std_logic :='0';
375 
        signal check_FF_eoi : std_logic :='0';
376 
        signal check_FF_context : std_logic_vector(3 downto 0) := (others=>'0');
377 
 
378 
        signal input_fifo_data : std_logic_vector(7 downto 0) := (others=>'0');
379 
        signal input_fifo_datavalid, input_fifo_full, input_fifo_almost_full, input_fifo_empty, input_fifo_almost_empty : std_logic :='0';
380 
        signal input_fifo_rd_en, input_fifo_wr_en, input_fifo_reset : std_logic :='0';
381 
 
382 
        signal checkff_fifo_data : std_logic_vector(11 downto 0) := (others=>'0');
383 
        signal checkff_fifo_datavalid, checkff_fifo_full, checkff_fifo_almost_full, checkff_fifo_empty, checkff_fifo_almost_empty : std_logic :='0';
384 
        signal checkff_fifo_ready : std_logic :='0';
385 
 
386 
        signal huffman_error, huffman_ready, huffman_datavalid, huffman_eob : std_logic :='0';
387 
        signal huffman_address : std_logic_vector(5 downto 0) := (others=>'0');
388 
        signal huffman_data : std_logic_vector(15 downto 0) := (others=>'0');
389 
        signal huffman_context : std_logic_vector(3 downto 0) :=(others=>'0');
390 
 
391 
        signal dezigzag_context : std_logic_vector(3 downto 0) :=(others=>'0');
392 
        signal dezigzag_data : std_logic_vector(11 downto 0) := (others=>'0');
393 
        signal dezigzag_datavalid, dezigzag_ready : std_logic :='0';
394 
 
395 
        signal dequantize_datavalid, dequantize_ready : std_logic :='0';
396 
        signal dequantize_context : std_logic_vector(3 downto 0) :=(others=>'0');
397 
        signal dequantize_data : std_logic_vector(11 downto 0) := (others=>'0');
398 
 
399 
        signal idct_datavalid, idct_ready : std_logic :='0';
400 
        signal idct_context : std_logic_vector(3 downto 0) :=(others=>'0');
401 
        signal idct_data : std_logic_vector(8 downto 0) := (others=>'0');
402 
 
403 
        signal upsampling_datavalid, upsampling_ready : std_logic :='0';
404 
        signal upsampling_context : std_logic_vector(3 downto 0) :=(others=>'0');
405 
        signal upsampling_Y, upsampling_Cb, upsampling_Cr : std_logic_vector(8 downto 0) := (others=>'0');
406 
 
407 
        signal YCbCr2RGB_datavalid, YCbCr2RGB_ready : std_logic :='0';
408 
        signal YCbCr2RGB_context : std_logic_vector(3 downto 0) :=(others=>'0');
409 
        signal YCbCr2RGB_R, YCbCr2RGB_G, YCbCr2RGB_B : std_logic_vector(7 downto 0) := (others=>'0');
410 
 
411 
        signal vga_datavalid, vga_ready, vga_error : std_logic :='0';
412 
 
413 
   -- header: info
414 
        signal header_select, header_valid, header_error : std_logic :='0';
415 
        -- huffman tables
416 
        signal header_ht_symbols_wea, header_ht_tables_wea :std_logic :='0';
417 
        signal header_ht_select : std_logic_vector(2 downto 0) := (others=>'0');
418 
        signal header_ht_tables_address : std_logic_vector(7 downto 0) := (others=>'0');
419 
        signal header_ht_nr_of_symbols_address : std_logic_vector(3 downto 0) := (others=>'0');
420 
        signal header_ht_data : std_logic_vector(7 downto 0) := (others=>'0');
421 
        -- quantization tables
422 
        signal header_qt_wea : std_logic := '0';
423 
        signal header_qt_select : std_logic_vector(1 downto 0) := (others=>'0');
424 
        signal header_qt_data : std_logic_vector(7 downto 0) := (others=>'0');
425 
        -- header: sos-field
426 
        signal header_comp1_huff_dc : std_logic_vector(3 downto 0) := (others=>'0');
427 
        signal header_comp2_huff_dc : std_logic_vector(3 downto 0) := (others=>'0');
428 
        signal header_comp3_huff_dc : std_logic_vector(3 downto 0) := (others=>'0');
429 
        signal header_comp1_huff_ac : std_logic_vector(3 downto 0) := (others=>'0');
430 
        signal header_comp2_huff_ac : std_logic_vector(3 downto 0) := (others=>'0');
431 
        signal header_comp3_huff_ac : std_logic_vector(3 downto 0) := (others=>'0');
432 
        --header: sof-field
433 
        signal header_height : std_logic_vector(15 downto 0) := (others=>'0');
434 
        signal header_width : std_logic_vector(15 downto 0) := (others=>'0');
435 
        signal header_sampling: std_logic_vector(1 downto 0) := (others=>'0');
436 
        signal header_comp1_qt_number : std_logic_vector(0 downto 0) := (others=>'0');
437 
        signal header_comp2_qt_number : std_logic_vector(0 downto 0) := (others=>'0');
438 
        signal header_comp3_qt_number : std_logic_vector(0 downto 0) := (others=>'0');
439 
 
440 
 
441 
 
442 
 
443 
begin
444 
 
445 
 
446 
 
447 
-- **********************************************************************************************
448 
-- * Debugging
449 
-- **********************************************************************************************
450 
--LEDs <= not header_error & not huffman_error & not vga_ready & not header_valid;
451 
--chipscope_o <= data_i &
452 
--                                      input_fifo_data & YCbCr2RGB_R & YCbCr2RGB_G & YCbCr2RGB_B &
453 
--                                      datavalid_i & ready_i & YCbCr2RGB_datavalid & ready & header_sampling & check_FF_eoi &
454 
--                                      (header_error or huffman_error) & check_FF_data & checkff_fifo_data(7 downto 0) &
455 
--                                      huffman_data(7 downto 0) & header_width &  header_height;
456 
-- **********************************************************************************************
457 
 
458 
 
459 
 
460 
--------------------------------------------------------------
461 
-- store some values from header
462 
--------------------------------------------------------------
463 
process(        header_select, header_sampling, sampling, width, height, header_width, header_height,
464 
                        header_comp1_qt_number, header_comp2_qt_number, header_comp3_qt_number,
465 
                        comp1_qt_number, comp2_qt_number, comp3_qt_number)
466 
begin
467 
        sampling_D      <= sampling;
468 
        comp1_qt_number_D <= comp1_qt_number;
469 
        comp2_qt_number_D <= comp2_qt_number;
470 
        comp3_qt_number_D <= comp3_qt_number;
471 
        width_D         <= width;
472 
        height_D                <= height;
473 
        if(header_select='0') then
474 
                sampling_D(1 downto 0)   <= header_sampling;
475 
                comp1_qt_number_D(0 downto 0) <= header_comp1_qt_number;
476 
                comp2_qt_number_D(0 downto 0) <= header_comp2_qt_number;
477 
                comp3_qt_number_D(0 downto 0) <= header_comp3_qt_number;
478 
                width_D(15 downto 0)             <= header_width;
479 
                height_D(15 downto 0)    <= header_height;
480 
        else
481 
                sampling_D(3 downto 2)  <= header_sampling;
482 
                comp1_qt_number_D(1 downto 1) <= header_comp1_qt_number;
483 
                comp2_qt_number_D(1 downto 1) <= header_comp2_qt_number;
484 
                comp3_qt_number_D(1 downto 1) <= header_comp3_qt_number;
485 
                width_D(31 downto 16)   <= header_width;
486 
                height_D(31 downto 16)  <= header_height;
487 
        end if;
488 
end process;
489 
 
490 
process(Clk)
491 
begin
492 
        if rising_edge(Clk) then
493 
                if reset='1' then
494 
                        sampling <= (others=>'0');
495 
                        comp1_qt_number <= (others=>'0');
496 
                        comp2_qt_number <= (others=>'0');
497 
                        comp3_qt_number <= (others=>'0');
498 
                        width           <= (others=>'0');
499 
                        height  <= (others=>'0');
500 
                else
501 
                        sampling <= sampling_D;
502 
                        comp1_qt_number <= comp1_qt_number_D;
503 
                        comp2_qt_number <= comp2_qt_number_D;
504 
                        comp3_qt_number <= comp3_qt_number_D;
505 
                        width           <= width_D;
506 
                        height  <= height_D;
507 
                end if;
508 
        end if;
509 
end process;
510 
--------------------------------------------------------------
511 
 
512 
 
513 
 
514 
 
515 
-- **********************************************************************************************
516 
-- * Port Maps
517 
-- **********************************************************************************************
518 
 
519 
--------------------------------------------------------------
520 
-- FIFO to buffer the input data
521 
--------------------------------------------------------------
522 
jpeg_input_fifo_p:jpeg_input_fifo
523 
        port map (
524 
                din                             => data_i,
525 
                rd_clk                  => Clk,
526 
                rd_en                   => input_fifo_rd_en,
527 
                rst                             => input_fifo_reset,
528 
                wr_clk                  => Clk,
529 
                wr_en                   => input_fifo_wr_en,
530 
                almost_full     => input_fifo_almost_full,
531 
                dout                            => input_fifo_data,
532 
                empty                   => input_fifo_empty,
533 
                full                            => input_fifo_full,
534 
                valid                   => input_fifo_datavalid
535 
        );
536 
input_fifo_reset <= reset or check_FF_eoi;
537 
--------------------------------------------------------------
538 
input_fifo_rd_en <= check_FF_ready;
539 
input_fifo_wr_en <= datavalid_i and ready;
540 
 
541 
 
542 
--------------------------------------------------------------
543 
-- Replaces "FF00" with "FF" and filters out other occurances
544 
-- of "FF"
545 
--------------------------------------------------------------
546 
jpeg_check_FF_p:jpeg_check_FF
547 
        port map(
548 
                Clk                             => Clk,
549 
                reset_i                 => reset,
550 
                eoi_o                           => check_FF_eoi,
551 
                header_valid_i  => header_valid,
552 
                header_select_i=> header_select,
553 
                data_i                  => input_fifo_data,
554 
                data_o                  => check_FF_data,
555 
                context_o               => check_FF_context,
556 
                datavalid_i     => input_fifo_datavalid,
557 
                datavalid_o     => check_FF_datavalid,
558 
                ready_i                 => checkff_fifo_ready,
559 
                ready_o                 => check_FF_ready
560 
        );
561 
--------------------------------------------------------------
562 
 
563 
 
564 
--------------------------------------------------------------
565 
-- Fifo between checkff and huffman
566 
--------------------------------------------------------------
567 
jpeg_checkff_fifo_p:jpeg_checkff_fifo
568 
        port map (
569 
                din(11 downto 8)        => check_ff_context,
570 
                din(7 downto 0)  => check_FF_data,
571 
                rd_clk                  => Clk,
572 
                rd_en                   => huffman_ready,
573 
                rst                             => reset,
574 
                wr_clk                  => Clk,
575 
                wr_en                   => check_FF_datavalid,
576 
                almost_empty    => checkff_fifo_almost_empty,
577 
                almost_full     => checkff_fifo_almost_full,
578 
                dout                            => checkff_fifo_data,
579 
                empty                   => checkff_fifo_empty,
580 
                full                            => checkff_fifo_full,
581 
                valid                   => checkff_fifo_datavalid
582 
        );
583 
 
584 
--------------------------------------------------------------
585 
checkff_fifo_ready <= not (checkff_fifo_full);
586 
 
587 
 
588 
--------------------------------------------------------------
589 
-- Huffman decoder
590 
--------------------------------------------------------------
591 
jpeg_huffman_p:jpeg_huffman
592 
        port map (
593 
                Clk                                             => Clk,
594 
                reset_i                                 => reset,
595 
                header_select_i         => header_select,
596 
                error_o                                 => huffman_error,
597 
                ht_symbols_wea_i                => header_ht_symbols_wea,
598 
                ht_tables_wea_i         => header_ht_tables_wea,
599 
                ht_select_i                             => header_ht_select,
600 
                ht_tables_address_i                     => header_ht_tables_address,
601 
                ht_nr_of_symbols_address_i      => header_ht_nr_of_symbols_address,
602 
                ht_data_i                               => header_ht_data,
603 
                context_i                               => checkff_fifo_data(11 downto 8),
604 
                data_i                                  => checkff_fifo_data(7 downto 0),
605 
                context_o                               => huffman_context,
606 
                data_o                                  => huffman_data,
607 
                comp1_huff_dc_i         => header_comp1_huff_dc,
608 
                comp2_huff_dc_i         => header_comp2_huff_dc,
609 
                comp3_huff_dc_i         => header_comp3_huff_dc,
610 
                comp1_huff_ac_i         => header_comp1_huff_ac,
611 
                comp2_huff_ac_i         => header_comp2_huff_ac,
612 
                comp3_huff_ac_i         => header_comp3_huff_ac,
613 
                sampling_i                              => sampling,
614 
                datavalid_i                     => checkff_fifo_datavalid,
615 
                datavalid_o                     => huffman_datavalid,
616 
                ready_i                                 => dequantize_ready,
617 
                ready_o                                 => huffman_ready
618 
    );
619 
--------------------------------------------------------------
620 
 
621 
 
622 
--------------------------------------------------------------
623 
-- Dequantization
624 
--------------------------------------------------------------
625 
jpeg_dequantize_p:jpeg_dequantize
626 
        port map (
627 
                Clk                             => Clk,
628 
                reset_i                 => reset,
629 
                header_select_i=> header_select,
630 
                qt_wea_i                        => header_qt_wea,
631 
                qt_select_i             => header_qt_select,
632 
                qt_data_i               => header_qt_data,
633 
                sampling_i              => sampling,
634 
                comp1_qt_number_i => comp1_qt_number,
635 
                comp2_qt_number_i => comp2_qt_number,
636 
                comp3_qt_number_i => comp3_qt_number,
637 
                context_i               => huffman_context,
638 
                data_i(11)              => huffman_data(15),                    -- handle negative values (TODO better)
639 
                data_i(10 downto 0) => huffman_data(10 downto 0),
640 
                context_o               => dequantize_context,
641 
                data_o                  => dequantize_data,
642 
                datavalid_i     => huffman_datavalid,                           -- TODO
643 
                datavalid_o     => dequantize_datavalid,
644 
                ready_i                 => dezigzag_ready,
645 
                ready_o                 => dequantize_ready                                     -- TODO
646 
    );
647 
--------------------------------------------------------------
648 
 
649 
 
650 
--------------------------------------------------------------
651 
-- Address-maping to revert the ZigZag-Order
652 
--------------------------------------------------------------
653 
jpeg_dezigzag_p:jpeg_dezigzag
654 
        port map (
655 
                Clk                     => Clk,
656 
                context_i       => dequantize_context,
657 
                data_i          => dequantize_data,
658 
                reset_i         => reset,
659 
                data_o          => dezigzag_data,
660 
                context_o       => dezigzag_context,
661 
                datavalid_i => dequantize_datavalid,
662 
                datavalid_o => dezigzag_datavalid,
663 
                ready_i         => idct_ready,
664 
                ready_o         => dezigzag_ready
665 
    );
666 
--------------------------------------------------------------
667 
 
668 
 
669 
--------------------------------------------------------------
670 
-- IDCT
671 
--------------------------------------------------------------
672 
jpeg_idct_p:jpeg_idct
673 
        port map (
674 
                Clk                             => Clk,
675 
                reset_i                 => reset,
676 
                context_i               => dezigzag_context,
677 
                data_i                  => dezigzag_data,
678 
                context_o               => idct_context,
679 
                data_o                  => idct_data,
680 
                datavalid_i     => dezigzag_datavalid,
681 
                datavalid_o     => idct_datavalid,
682 
                ready_i                 => upsampling_ready,
683 
                ready_o                 => idct_ready
684 
    );
685 
--------------------------------------------------------------
686 
 
687 
 
688 
--------------------------------------------------------------
689 
-- Upsampling
690 
--------------------------------------------------------------
691 
jpeg_upsampling_p:jpeg_upsampling
692 
        port map (
693 
                Clk                             => Clk,
694 
                reset_i                 => reset,
695 
                context_i               => idct_context,
696 
                data_i                  => idct_data,
697 
                sampling_i              => sampling,
698 
                context_o               => upsampling_context,
699 
                Y_o                             => upsampling_Y,
700 
                Cb_o                            => upsampling_Cb,
701 
                Cr_o                            => upsampling_Cr,
702 
                datavalid_i     => idct_datavalid,
703 
                datavalid_o     => upsampling_datavalid,
704 
                ready_i                 => YCbCr2RGB_ready,
705 
                ready_o                 => upsampling_ready
706 
    );
707 
--------------------------------------------------------------
708 
 
709 
 
710 
--------------------------------------------------------------
711 
-- YCbCr2RGB
712 
--------------------------------------------------------------
713 
jpeg_YCbCr2RGB_p:jpeg_YCbCr2RGB
714 
        port map (
715 
                Clk                             => Clk,
716 
                reset_i                 => reset,
717 
                context_i               => upsampling_context,
718 
                Y_i                             => upsampling_Y,
719 
                Cb_i                            => upsampling_Cb,
720 
                Cr_i                            => upsampling_Cr,
721 
                context_o               => YCbCr2RGB_context,
722 
                R_o                             => YCbCr2RGB_R,
723 
                G_o                             => YCbCr2RGB_G,
724 
                B_o                             => YCbCr2RGB_B,
725 
                datavalid_i     => upsampling_datavalid,
726 
                datavalid_o     => YCbCr2RGB_datavalid,
727 
                ready_i                 => vga_ready,
728 
                ready_o                 => YCbCr2RGB_ready
729 
    );
730 
--------------------------------------------------------------
731 
vga_ready       <= ready_i;
732 
 
733 
 
734 
------------------------------------------------------------
735 
-- This one first reads out header information,
736 
-- then provides header information
737 
------------------------------------------------------------
738 
jpeg_header_p:jpeg_header
739 
        port map (
740 
                Clk                     => Clk,                                                 -- 1 bit
741 
                data_i          => input_fifo_data,                     -- 8 bit
742 
                datavalid_i     => input_fifo_datavalid,        -- 1 bit
743 
                reset_i                 => reset,                                               -- 1 bit
744 
                eoi_i                   => check_FF_eoi,                        -- 1 ibt
745 
 
746 
                header_valid_o => header_valid,                 -- 1 bit
747 
                header_select_o=> header_select,                        -- 1 bit
748 
                header_error_o => header_error,                 -- 1 bit
749 
 
750 
                -- initialize the huffmann tables (located in the huffmann-decoder entity)
751 
                ht_symbols_wea_o        => header_ht_symbols_wea,
752 
                ht_tables_wea_o         => header_ht_tables_wea,
753 
                ht_select_o                     => header_ht_select,
754 
                ht_tables_address_o                     => header_ht_tables_address,
755 
                ht_nr_of_symbols_address_o      => header_ht_nr_of_symbols_address,
756 
                ht_data_o                       => header_ht_data,
757 
 
758 
                -- initialize the quantization tables (located in the dequantisation entity)
759 
                qt_wea_o                        => header_qt_wea,
760 
                qt_select_o             => header_qt_select,
761 
                qt_data_o               => header_qt_data,
762 
 
763 
                -- sos-field
764 
                comp1_huff_dc_o         => header_comp1_huff_dc,
765 
                comp2_huff_dc_o         => header_comp2_huff_dc,
766 
                comp3_huff_dc_o         => header_comp3_huff_dc,
767 
                comp1_huff_ac_o         => header_comp1_huff_ac,
768 
                comp2_huff_ac_o         => header_comp2_huff_ac,
769 
                comp3_huff_ac_o         => header_comp3_huff_ac,
770 
 
771 
                --sof-field
772 
                height_o                                => header_height,
773 
                width_o                                         => header_width,
774 
                sampling_o                              => header_sampling,
775 
                comp1_qt_number_o       => header_comp1_qt_number,
776 
                comp2_qt_number_o       => header_comp2_qt_number,
777 
                comp3_qt_number_o       => header_comp3_qt_number
778 
        );
779 
------------------------------------------------------------
780 
 
781 
 
782 
 
783 
-- **********************************************************************************************
784 
-- * Wires
785 
-- **********************************************************************************************
786 
eoi_o           <= check_FF_eoi;                        -- for controlling input data (backwards in pipeline)
787 
context_o<= YCbCr2RGB_context;  -- context of output data
788 
 
789 
reset           <= reset_i;
790 
error_o <= error;
791 
error           <= header_error or huffman_error;
792 
 
793 
red_o           <= YCbCr2RGB_R;
794 
green_o <= YCbCr2RGB_G;
795 
blue_o  <= YCbCr2RGB_B;
796 
 
797 
-- connect the valid context set to the outside
798 
sampling_o      <= sampling_out;
799 
width_o         <= width_out;
800 
height_o                <= height_out;
801 
process(YCbCr2RGB_context, sampling, width, height)
802 
begin
803 
        if YCbCr2RGB_context(1) ='0' then
804 
                sampling_out    <= sampling(1 downto 0);
805 
                width_out               <= width(15 downto 0);
806 
                height_out              <= height(15 downto 0);
807 
        else
808 
                sampling_out    <= sampling(3 downto 2);
809 
                width_out               <= width(31 downto 16);
810 
                height_out              <= height(31 downto 16);
811 
        end if;
812 
end process;
813 
 
814 
 
815 
-- connect pipeline flowcontroll to the outside
816 
datavalid_o <= YCbCr2RGB_datavalid;
817 
ready_o         <= ready and not error;
818 
 
819 
 
820 
-- **********************************************************************************************
821 
-- * Processes
822 
-- **********************************************************************************************
823 
 
824 
-- refill the input-fifo only after it has run empty -> bus is free the most time
825 
process(input_fifo_almost_full, input_fifo_empty)
826 
begin
827 
        ready_D <= ready;
828 
        if input_fifo_almost_full='1' then
829 
                ready_D <= '0';
830 
        elsif input_fifo_empty ='1' then
831 
                ready_D <= '1';
832 
        end if;
833 
end process;
834 
 
835 
process(Clk)
836 
begin
837 
        if rising_edge(Clk) then
838 
                if reset='1' or check_FF_eoi='1' then
839 
                        ready <= '0';
840 
                else
841 
                        ready <= ready_D;
842 
                end if;
843 
        end if;
844 
end process;
845 
 
846 
end IMP;

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