URL https://opencores.org/ocsvn/mjpeg-decoder/mjpeg-decoder/trunk

Subversion Repositories mjpeg-decoder

[/] [mjpeg-decoder/] [trunk/] [mjpeg/] [pcores/] [myipif/] [hdl/] [vhdl/] [jpeg_YCbCr2RGB.vhd] - Blame information for rev 8

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------------------------------------------------------------------
-- Two clock cycles delay
--
-- TODO: 
-- - remove reset ???
------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity jpeg_YCbCr2RGB is
        port(
                Clk                     : in std_logic;
                reset_i         : in std_logic;
 
                context_i       : in  std_logic_vector(3 downto 0);
                Y_i                     : in std_logic_vector(8 downto 0);
                Cb_i                    : in std_logic_vector(8 downto 0);
                Cr_i                    : in std_logic_vector(8 downto 0);
 
                context_o       : out  std_logic_vector(3 downto 0);
                R_o                     : out std_logic_vector(7 downto 0);
                G_o                     : out std_logic_vector(7 downto 0);
                B_o                     : out std_logic_vector(7 downto 0);
 
                -- flow control
                datavalid_i     : in std_logic;
                datavalid_o     : out std_logic;
                ready_i         : in  std_logic;
                ready_o         : out std_logic
        );
end entity jpeg_YCbCr2RGB;
 
 
 
architecture IMP of jpeg_YCbCr2RGB is
 
        signal datavalid, datavalid_D : std_logic := '0';
        signal ready : std_logic := '0';
        signal ce : std_logic :='1';
        signal reset : std_logic :='1';
 
        signal context, context_D : std_logic_vector(3 downto 0) := (others=>'0');
        signal R, R_D, G, G_D, B, B_D : std_logic_vector(7 downto 0) := (others=>'0');
        signal tmp_R, tmp_G, tmp_B : integer := 0;
        signal tmp_R_D, tmp_G_D, tmp_B_D : integer := 0;
        signal Y, Cb, Cr :  std_logic_vector(7 downto 0) := (others=>'0');
 
begin
 
        process(Y_i, Cb_i, Cr_i, R, G, B)
                variable tmp_Y : integer := 0;
                variable int_Y, int_Cb, int_Cr : integer := 0;
        begin
 
                -- level shift and convertion to integer
                -- 8-bit may (intentionally) overflow here
                int_Y  := conv_integer(signed(Y_i));
                int_Cb := conv_integer(signed(Cb_i));
                int_Cr := conv_integer(signed(Cr_i));
 
                -- to use integer arithmetic
                tmp_Y := 1024*(int_Y+128);
 
                -- YCbCr2RBG 
                tmp_R_D <= tmp_Y +                 1436*(int_Cr);
                tmp_G_D <= tmp_Y -  352*(int_Cb) -  731*(int_Cr);
                tmp_B_D <= tmp_Y + 1815*(int_Cb);
 
        end process;
 
 
        -- one additional clock cycle to meet timing constraints on the xup board
        process(Clk)
        begin
                if rising_edge(Clk) then
                        if ce='1' then
                                tmp_R <= tmp_R_D;
                                tmp_G <= tmp_G_D;
                                tmp_B <= tmp_B_D;
                        end if;
                end if;
        end process;
 
 
 
        process(tmp_R, tmp_G, tmp_B)
                variable tmp_R2, tmp_G2, tmp_B2 : integer := 0;
        begin
                tmp_R2 := tmp_R;
                tmp_G2 := tmp_G;
                tmp_B2 := tmp_B;
 
                -- check boundaries
                if(tmp_R<0) then
                        tmp_R2 := 0;
                elsif(tmp_R>255*1024) then
                        tmp_R2 := 255*1024;
                end if;
                if(tmp_G<0) then
                        tmp_G2 := 0;
                elsif(tmp_G>255*1024) then
                        tmp_G2 := 255*1024;
                end if;
                if(tmp_B<0) then
                        tmp_B2 := 0;
                elsif(tmp_B>255*1024) then
                        tmp_B2 := 255*1024;
                end if;
 
                R_D <= conv_std_logic_vector(tmp_R2/1024, 8);
                G_D <= conv_std_logic_vector(tmp_G2/1024, 8);
                B_D <= conv_std_logic_vector(tmp_B2/1024, 8);
 
        end process;
 
 
        -- flowcontroll
        ready_o         <= ready_i;
        ce                      <= ready_i;
 
        process(Clk)
        begin
                if rising_edge(Clk) then
                                context         <= context_i;
                                context_o       <= context;
                        if reset_i ='1' then
                                context         <= (others=>'0');
                                context_o       <= (others=>'0');
                                datavalid       <= '0';
                                datavalid_o     <= '0';
                        elsif ce='1' then
                                datavalid       <= datavalid_i;
                                datavalid_o     <= datavalid;
                                R_o <= R_D;
                                G_o <= G_D;
                                B_o <= B_D;
                        end if;
                end if;
        end process;
 
end IMP;

Line No.	Rev	Author	Line
1	2	smanz	`------------------------------------------------------------------`
2			`-- Two clock cycles delay`
3			`--`
4			`-- TODO:`
5			`-- - remove reset ???`
6			`------------------------------------------------------------------`
7
8			`library ieee;`
9			`use ieee.std_logic_1164.all;`
10			`use ieee.std_logic_arith.all;`
11			`use ieee.std_logic_unsigned.all;`
12
13			`entity jpeg_YCbCr2RGB is`
14			`port(`
15			`Clk : in std_logic;`
16			`reset_i : in std_logic;`
17
18			`context_i : in std_logic_vector(3 downto 0);`
19			`Y_i : in std_logic_vector(8 downto 0);`
20			`Cb_i : in std_logic_vector(8 downto 0);`
21			`Cr_i : in std_logic_vector(8 downto 0);`
22
23			`context_o : out std_logic_vector(3 downto 0);`
24			`R_o : out std_logic_vector(7 downto 0);`
25			`G_o : out std_logic_vector(7 downto 0);`
26			`B_o : out std_logic_vector(7 downto 0);`
27
28			`-- flow control`
29			`datavalid_i : in std_logic;`
30			`datavalid_o : out std_logic;`
31			`ready_i : in std_logic;`
32			`ready_o : out std_logic`
33			`);`
34			`end entity jpeg_YCbCr2RGB;`
35
36
37
38			`architecture IMP of jpeg_YCbCr2RGB is`
39
40			`signal datavalid, datavalid_D : std_logic := '0';`
41			`signal ready : std_logic := '0';`
42			`signal ce : std_logic :='1';`
43			`signal reset : std_logic :='1';`
44
45			`signal context, context_D : std_logic_vector(3 downto 0) := (others=>'0');`
46			`signal R, R_D, G, G_D, B, B_D : std_logic_vector(7 downto 0) := (others=>'0');`
47			`signal tmp_R, tmp_G, tmp_B : integer := 0;`
48			`signal tmp_R_D, tmp_G_D, tmp_B_D : integer := 0;`
49			`signal Y, Cb, Cr : std_logic_vector(7 downto 0) := (others=>'0');`
50
51			`begin`
52
53			`process(Y_i, Cb_i, Cr_i, R, G, B)`
54			`variable tmp_Y : integer := 0;`
55			`variable int_Y, int_Cb, int_Cr : integer := 0;`
56			`begin`
57
58			`-- level shift and convertion to integer`
59			`-- 8-bit may (intentionally) overflow here`
60			`int_Y := conv_integer(signed(Y_i));`
61			`int_Cb := conv_integer(signed(Cb_i));`
62			`int_Cr := conv_integer(signed(Cr_i));`
63
64			`-- to use integer arithmetic`
65			`tmp_Y := 1024*(int_Y+128);`
66
67			`-- YCbCr2RBG`
68			`tmp_R_D <= tmp_Y + 1436*(int_Cr);`
69			`tmp_G_D <= tmp_Y - 352(int_Cb) - 731(int_Cr);`
70			`tmp_B_D <= tmp_Y + 1815*(int_Cb);`
71
72			`end process;`
73
74
75			`-- one additional clock cycle to meet timing constraints on the xup board`
76			`process(Clk)`
77			`begin`
78			`if rising_edge(Clk) then`
79			`if ce='1' then`
80			`tmp_R <= tmp_R_D;`
81			`tmp_G <= tmp_G_D;`
82			`tmp_B <= tmp_B_D;`
83			`end if;`
84			`end if;`
85			`end process;`
86
87
88
89			`process(tmp_R, tmp_G, tmp_B)`
90			`variable tmp_R2, tmp_G2, tmp_B2 : integer := 0;`
91			`begin`
92			`tmp_R2 := tmp_R;`
93			`tmp_G2 := tmp_G;`
94			`tmp_B2 := tmp_B;`
95
96			`-- check boundaries`
97			`if(tmp_R<0) then`
98			`tmp_R2 := 0;`
99			`elsif(tmp_R>255*1024) then`
100			`tmp_R2 := 255*1024;`
101			`end if;`
102			`if(tmp_G<0) then`
103			`tmp_G2 := 0;`
104			`elsif(tmp_G>255*1024) then`
105			`tmp_G2 := 255*1024;`
106			`end if;`
107			`if(tmp_B<0) then`
108			`tmp_B2 := 0;`
109			`elsif(tmp_B>255*1024) then`
110			`tmp_B2 := 255*1024;`
111			`end if;`
112
113			`R_D <= conv_std_logic_vector(tmp_R2/1024, 8);`
114			`G_D <= conv_std_logic_vector(tmp_G2/1024, 8);`
115			`B_D <= conv_std_logic_vector(tmp_B2/1024, 8);`
116
117			`end process;`
118
119
120			`-- flowcontroll`
121			`ready_o <= ready_i;`
122			`ce <= ready_i;`
123
124			`process(Clk)`
125			`begin`
126			`if rising_edge(Clk) then`
127			`context <= context_i;`
128			`context_o <= context;`
129			`if reset_i ='1' then`
130			`context <= (others=>'0');`
131			`context_o <= (others=>'0');`
132			`datavalid <= '0';`
133			`datavalid_o <= '0';`
134			`elsif ce='1' then`
135			`datavalid <= datavalid_i;`
136			`datavalid_o <= datavalid;`
137			`R_o <= R_D;`
138			`G_o <= G_D;`
139			`B_o <= B_D;`
140			`end if;`
141			`end if;`
142			`end process;`
143
144			`end IMP;`

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Subversion Repositories mjpeg-decoder

[/] [mjpeg-decoder/] [trunk/] [mjpeg/] [pcores/] [myipif/] [hdl/] [vhdl/] [jpeg_YCbCr2RGB.vhd] - Blame information for rev 8