URL https://opencores.org/ocsvn/mjpeg-decoder/mjpeg-decoder/trunk

Subversion Repositories mjpeg-decoder

[/] [mjpeg-decoder/] [trunk/] [mjpeg/] [pcores/] [myipif/] [hdl/] [vhdl/] [jpeg_dequantize.vhd] - Blame information for rev 4

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
 
entity jpeg_dequantize is
  port
    (   Clk                             : in std_logic;
                reset_i                 : in std_logic;
 
                -- storing the tables
                header_select_i: in std_logic;
                qt_wea_i                : in std_logic;
                qt_select_i     : in std_logic_vector(1 downto 0);               -- bit 1 and 0: table-nr. (at the moment only two QTs supported)
                qt_data_i       : in std_logic_vector(7 downto 0);
 
                sampling_i      : in  std_logic_vector(3 downto 0);
 
                context_i               : in  std_logic_vector(3 downto 0);
                data_i                  : in  std_logic_vector(11 downto 0);
                context_o               : out std_logic_vector(3 downto 0) :=(others=>'0');
                data_o                  : out std_logic_vector(11 downto 0) :=(others=>'0');
 
                comp1_qt_number_i : in std_logic_vector(1 downto 0);
                comp2_qt_number_i : in std_logic_vector(1 downto 0);
                comp3_qt_number_i : in std_logic_vector(1 downto 0);
 
                -- flow control
                datavalid_i     : in std_logic;
                datavalid_o     : out std_logic;
                ready_i                 : in  std_logic;
                ready_o                 : out std_logic
    );
end entity jpeg_dequantize;
 
 
 
 
 
 
 
 
 
architecture IMP of jpeg_dequantize is
 
        component jpeg_dequant_multiplier
                port (
                a: IN std_logic_VECTOR(11 downto 0);
                b: IN std_logic_VECTOR(7 downto 0);
                o: OUT std_logic_VECTOR(19 downto 0));
        end component;
 
        -- store the tables in shift registers
        component jpeg_qt_sr IS
                port (
                d: IN std_logic_VECTOR(7 downto 0);
                clk: IN std_logic;
                ce: IN std_logic;
                q: OUT std_logic_VECTOR(7 downto 0));
        end component;
 
 
 
        signal qt0_0_data_in, qt1_0_data_in, qt0_1_data_in, qt1_1_data_in : std_logic_vector(7 downto 0) := (others=>'0');
        signal qt0_0_data_out, qt1_0_data_out, qt0_1_data_out, qt1_1_data_out : std_logic_vector(7 downto 0) := (others=>'0');
        signal qt0_0_ce, qt1_0_ce, qt0_1_ce, qt1_1_ce : std_logic :='0';
        signal qt_out : std_logic_vector(7 downto 0) :=(others=>'0');
 
        signal data : std_logic_vector(19 downto 0):=(others=>'0');
        signal context : std_logic_vector(3 downto 0) :=(others =>'0');
        signal select_qt, select_qt_D : std_logic_vector( 1 downto 0) :=(others=>'0');
        signal counter : std_logic_vector(5 downto 0) :=(others=>'0');
        signal sampling_counter, sampling_counter_D : std_logic_vector(2 downto 0) :=(others=>'0');
        signal sampling : std_logic_vector(1 downto 0) :=(others=>'0');
        signal comp1_qt_number : std_logic_vector(0 downto 0) :="0";
        signal comp2_qt_number : std_logic_vector(0 downto 0) :="0";
        signal comp3_qt_number : std_logic_vector(0 downto 0) :="0";
 
        -- flowcontroll
        signal datavalid : std_logic := '0';
        signal ce : std_logic :='0';
        signal reset : std_logic :='1';
 
 
 
 
 
begin
 
        ce                      <= datavalid_i and ready_i;
        datavalid       <= ce;
        ready_o                 <= ready_i;
        reset           <= reset_i;
 
        process(Clk)
        begin
                if rising_edge(Clk) then
 
                datavalid_o     <= datavalid;
                data_o          <= data(19) & data(10 downto 0);
                context         <= context_i;
                context_o       <= context;
 
                        if reset='1' then
                                datavalid_o     <= '0';
                                context_o       <= "0000";
                                context         <= "0000";
                        end if;
                end if;
        end process;
 
 
 
        process(Clk)
        begin
                if rising_edge(Clk) then
                        if reset='1' then
                                counter <= (others=>'0');
                        elsif(ce='1') then
                                counter <= counter + 1;
                        end if;
                end if;
        end process;
 
 
 
 
        -------------------------------------------------------------------------       
        -- store the context
        -------------------------------------------------------------------------       
        process(sampling_i, context(1))
        begin
                if (context(1)='0') then
                        sampling <= sampling_i(1 downto 0);
                        comp1_qt_number <= comp1_qt_number_i(0 downto 0);
                        comp2_qt_number <= comp2_qt_number_i(0 downto 0);
                        comp3_qt_number <= comp3_qt_number_i(0 downto 0);
                else
                        sampling <= sampling_i(3 downto 2);
                        comp1_qt_number <= comp1_qt_number_i(1 downto 1);
                        comp2_qt_number <= comp2_qt_number_i(1 downto 1);
                        comp3_qt_number <= comp3_qt_number_i(1 downto 1);
                end if;
        end process;
        -------------------------------------------------------------------------       
 
 
 
 
        -------------------------------------------------------------------------       
        -- count the data processed
        -------------------------------------------------------------------------       
        process(sampling_counter, sampling, counter)
        begin
                sampling_counter_D      <= sampling_counter;
 
                case sampling is
                ---------------------------------------
                -- gray         Y -> Y -> Y ...
                ---------------------------------------
                when "00" =>
                        sampling_counter_D      <= "000";
                ---------------------------------------
                -- 4:2:0                Y -> Y -> Y -> Y -> Cb -> Cr -> Y -> Y ...
                ---------------------------------------
                when "01" =>
                        if (counter=63) then
                                sampling_counter_D <= sampling_counter + 1;
                                if      (sampling_counter="101") then
                                        sampling_counter_D <= "000";
                                end if;
                        end if;
                ---------------------------------------
                -- 4:2:2                Y -> Y -> Cb -> Cr -> Y -> Y ...
                ---------------------------------------
                when "10" =>
                        if (counter=63) then
                                sampling_counter_D <= sampling_counter + 1;
                                if      (sampling_counter="011") then
                                        sampling_counter_D <= "000";
                                end if;
                        end if;
                ---------------------------------------
                -- 4:4:4                Y -> Cb -> Cr -> Y -> Cb ...
                ---------------------------------------
                when others =>
                        if (counter=63) then
                                sampling_counter_D <= sampling_counter + 1;
                                if      (sampling_counter="010") then
                                        sampling_counter_D <= "000";
                                end if;
                        end if;
                end case;
        end process;
 
 
        process(Clk)
        begin
                if (rising_edge(Clk)) then
                if (reset='1') then
                        sampling_counter        <= (others=>'0');
                elsif ce='1' then
                        sampling_counter        <= sampling_counter_D;
                end if;
                end if;
        end process;
        -------------------------------------------------------------------------       
 
 
 
        -------------------------------------------------------------------------       
        -- decide which table to use
        -------------------------------------------------------------------------       
        process(select_qt, sampling_counter, sampling)
        begin
                select_qt_D <= select_qt;
 
                case sampling is
 
                ---------------------------------------
                -- gray
                ---------------------------------------
                when "00" =>
                        select_qt_D <= context(1) & comp1_qt_number;
 
                ---------------------------------------
                -- 4:2:0
                ---------------------------------------
                when "01" =>
                        case sampling_counter is
                                when "000"|"001"|"010"|"011" =>
                                        select_qt_D <= context(1) & comp1_qt_number;
                                when "100" =>
                                        select_qt_D <= context(1) & comp2_qt_number;
                                when "101" =>
                                        select_qt_D <= context(1) & comp3_qt_number;
                                when others =>
                        end case;
 
                ---------------------------------------
                -- 4:2:2
                ---------------------------------------
                when "10" =>
                        case sampling_counter is
                                when "000"|"001" =>
                                        select_qt_D <= context(1) & comp1_qt_number;
                                when "010" =>
                                        select_qt_D <= context(1) & comp2_qt_number;
                                when "011" =>
                                        select_qt_D <= context(1) & comp3_qt_number;
                                when others =>
                        end case;
 
                ---------------------------------------
                -- 4:4:4
                ---------------------------------------
                when others =>
                        case sampling_counter is
                                when "000" =>
                                        select_qt_D <= context(1) & comp1_qt_number;
                                when "001" =>
                                        select_qt_D <= context(1) & comp2_qt_number;
                                when "010" =>
                                        select_qt_D <= context(1) & comp3_qt_number;
                                when others =>
                        end case;
 
                end case;
 
        end process;
 
 
        process(Clk)
        begin
                if rising_edge(Clk) then
                        select_qt <= select_qt_D;
                end if;
        end process;
        -------------------------------------------------------------------------       
 
 
 
 
        -------------------------------------------------------------------------       
        -- process the right table
        -------------------------------------------------------------------------       
        process(        qt0_0_data_out, qt1_0_data_out, qt0_1_data_out, qt1_1_data_out,
                                ce, context, select_qt, qt_wea_i, header_select_i, qt_select_i, qt_data_i)
        begin
 
                qt0_0_ce <= '0';
                qt1_0_ce <= '0';
                qt0_1_ce <= '0';
                qt1_1_ce <= '0';
                qt0_0_data_in <= qt0_0_data_out;
                qt1_0_data_in <= qt1_0_data_out;
                qt0_1_data_in <= qt0_1_data_out;
                qt1_1_data_in <= qt1_1_data_out;
 
                if ce='1' and context(1)='0' and select_qt(0)='0' then
                        qt0_0_ce <= '1';
                elsif ce='1' and context(1)='0' and select_qt(0)='1' then
                        qt1_0_ce <= '1';
                elsif ce='1' and context(1)='1' and select_qt(0)='0' then
                        qt0_1_ce <= '1';
                elsif ce='1' and context(1)='1' and select_qt(0)='1' then
                        qt1_1_ce <= '1';
                end if;
 
                -- fill the tables 
                if qt_wea_i='1' and header_select_i='0' and qt_select_i="00" then
                        qt0_0_ce <= '1';
                        qt0_0_data_in <= qt_data_i;
                elsif qt_wea_i='1' and header_select_i='0' and qt_select_i="01" then
                        qt1_0_ce <= '1';
                        qt1_0_data_in <= qt_data_i;
                elsif qt_wea_i='1' and header_select_i='1' and qt_select_i="00" then
                        qt0_1_ce <= '1';
                        qt0_1_data_in <= qt_data_i;
                elsif qt_wea_i='1' and header_select_i='1' and qt_select_i="01" then
                        qt1_1_ce <= '1';
                        qt1_1_data_in <= qt_data_i;
                end if;
 
--              end if;
        end process;
        -------------------------------------------------------------------------       
 
        -------------------------------------------------------------------------       
        -- select the right table for the multiplication 
        -------------------------------------------------------------------------       
        process(qt0_0_data_out, qt1_0_data_out, qt0_1_data_out, qt1_1_data_out, select_qt)
        begin
                if select_qt="00" then
                        qt_out <= qt0_0_data_out;
                elsif select_qt="01" then
                        qt_out <= qt1_0_data_out;
                elsif select_qt="10" then
                        qt_out <= qt0_1_data_out;
                elsif select_qt="11" then
                        qt_out <= qt1_1_data_out;
                end if;
        end process;
        -------------------------------------------------------------------------       
 
 
        -------------------------------------------------------------------------       
        -- Multiply
        -------------------------------------------------------------------------       
        jpeg_dequant_multiplier_p : jpeg_dequant_multiplier
                port map (
                        a => data_i,
                        b => qt_out,
                        o => data
                );
        -------------------------------------------------------------------------       
 
        -------------------------------------------------------------------------       
        -- circular shift registers for the tables 
        -------------------------------------------------------------------------       
        jpeg_qt_sr_0_0_p : jpeg_qt_sr
                port map(
                        d               => qt0_0_data_in,
                        clk     => Clk,
                        ce              => qt0_0_ce,
                        q               => qt0_0_data_out
                );
 
        jpeg_qt_sr_1_0_p : jpeg_qt_sr
                port map(
                        d               => qt1_0_data_in,
                        clk     => Clk,
                        ce              => qt1_0_ce,
                        q               => qt1_0_data_out
                );
 
        jpeg_qt_sr_0_1_p : jpeg_qt_sr
                port map(
                        d               => qt0_1_data_in,
                        clk     => Clk,
                        ce              => qt0_1_ce,
                        q               => qt0_1_data_out
                );
 
        jpeg_qt_sr_1_1_p : jpeg_qt_sr
                port map(
                        d               => qt1_1_data_in,
                        clk     => Clk,
                        ce              => qt1_1_ce,
                        q               => qt1_1_data_out
                );
        -------------------------------------------------------------------------       
 
 
end IMP;

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Subversion Repositories mjpeg-decoder

[/] [mjpeg-decoder/] [trunk/] [mjpeg/] [pcores/] [myipif/] [hdl/] [vhdl/] [jpeg_dequantize.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	smanz	`library ieee;`
2			`use ieee.std_logic_1164.all;`
3			`use ieee.std_logic_arith.all;`
4			`use ieee.std_logic_unsigned.all;`
5
6
7			`entity jpeg_dequantize is`
8			`port`
9			`( Clk : in std_logic;`
10			`reset_i : in std_logic;`
11
12			`-- storing the tables`
13			`header_select_i: in std_logic;`
14			`qt_wea_i : in std_logic;`
15			`qt_select_i : in std_logic_vector(1 downto 0); -- bit 1 and 0: table-nr. (at the moment only two QTs supported)`
16			`qt_data_i : in std_logic_vector(7 downto 0);`
17
18			`sampling_i : in std_logic_vector(3 downto 0);`
19
20			`context_i : in std_logic_vector(3 downto 0);`
21			`data_i : in std_logic_vector(11 downto 0);`
22			`context_o : out std_logic_vector(3 downto 0) :=(others=>'0');`
23			`data_o : out std_logic_vector(11 downto 0) :=(others=>'0');`
24
25			`comp1_qt_number_i : in std_logic_vector(1 downto 0);`
26			`comp2_qt_number_i : in std_logic_vector(1 downto 0);`
27			`comp3_qt_number_i : in std_logic_vector(1 downto 0);`
28
29			`-- flow control`
30			`datavalid_i : in std_logic;`
31			`datavalid_o : out std_logic;`
32			`ready_i : in std_logic;`
33			`ready_o : out std_logic`
34			`);`
35			`end entity jpeg_dequantize;`
36
37
38
39
40
41
42
43
44
45			`architecture IMP of jpeg_dequantize is`
46
47			`component jpeg_dequant_multiplier`
48			`port (`
49			`a: IN std_logic_VECTOR(11 downto 0);`
50			`b: IN std_logic_VECTOR(7 downto 0);`
51			`o: OUT std_logic_VECTOR(19 downto 0));`
52			`end component;`
53
54			`-- store the tables in shift registers`
55			`component jpeg_qt_sr IS`
56			`port (`
57			`d: IN std_logic_VECTOR(7 downto 0);`
58			`clk: IN std_logic;`
59			`ce: IN std_logic;`
60			`q: OUT std_logic_VECTOR(7 downto 0));`
61			`end component;`
62
63
64
65			`signal qt0_0_data_in, qt1_0_data_in, qt0_1_data_in, qt1_1_data_in : std_logic_vector(7 downto 0) := (others=>'0');`
66			`signal qt0_0_data_out, qt1_0_data_out, qt0_1_data_out, qt1_1_data_out : std_logic_vector(7 downto 0) := (others=>'0');`
67			`signal qt0_0_ce, qt1_0_ce, qt0_1_ce, qt1_1_ce : std_logic :='0';`
68			`signal qt_out : std_logic_vector(7 downto 0) :=(others=>'0');`
69
70			`signal data : std_logic_vector(19 downto 0):=(others=>'0');`
71			`signal context : std_logic_vector(3 downto 0) :=(others =>'0');`
72			`signal select_qt, select_qt_D : std_logic_vector( 1 downto 0) :=(others=>'0');`
73			`signal counter : std_logic_vector(5 downto 0) :=(others=>'0');`
74			`signal sampling_counter, sampling_counter_D : std_logic_vector(2 downto 0) :=(others=>'0');`
75			`signal sampling : std_logic_vector(1 downto 0) :=(others=>'0');`
76			`signal comp1_qt_number : std_logic_vector(0 downto 0) :="0";`
77			`signal comp2_qt_number : std_logic_vector(0 downto 0) :="0";`
78			`signal comp3_qt_number : std_logic_vector(0 downto 0) :="0";`
79
80			`-- flowcontroll`
81			`signal datavalid : std_logic := '0';`
82			`signal ce : std_logic :='0';`
83			`signal reset : std_logic :='1';`
84
85
86
87
88
89			`begin`
90
91			`ce <= datavalid_i and ready_i;`
92			`datavalid <= ce;`
93			`ready_o <= ready_i;`
94			`reset <= reset_i;`
95
96			`process(Clk)`
97			`begin`
98			`if rising_edge(Clk) then`
99
100			`datavalid_o <= datavalid;`
101			`data_o <= data(19) & data(10 downto 0);`
102			`context <= context_i;`
103			`context_o <= context;`
104
105			`if reset='1' then`
106			`datavalid_o <= '0';`
107			`context_o <= "0000";`
108			`context <= "0000";`
109			`end if;`
110			`end if;`
111			`end process;`
112
113
114
115			`process(Clk)`
116			`begin`
117			`if rising_edge(Clk) then`
118			`if reset='1' then`
119			`counter <= (others=>'0');`
120			`elsif(ce='1') then`
121			`counter <= counter + 1;`
122			`end if;`
123			`end if;`
124			`end process;`
125
126
127
128
129			`-------------------------------------------------------------------------`
130			`-- store the context`
131			`-------------------------------------------------------------------------`
132			`process(sampling_i, context(1))`
133			`begin`
134			`if (context(1)='0') then`
135			`sampling <= sampling_i(1 downto 0);`
136			`comp1_qt_number <= comp1_qt_number_i(0 downto 0);`
137			`comp2_qt_number <= comp2_qt_number_i(0 downto 0);`
138			`comp3_qt_number <= comp3_qt_number_i(0 downto 0);`
139			`else`
140			`sampling <= sampling_i(3 downto 2);`
141			`comp1_qt_number <= comp1_qt_number_i(1 downto 1);`
142			`comp2_qt_number <= comp2_qt_number_i(1 downto 1);`
143			`comp3_qt_number <= comp3_qt_number_i(1 downto 1);`
144			`end if;`
145			`end process;`
146			`-------------------------------------------------------------------------`
147
148
149
150
151			`-------------------------------------------------------------------------`
152			`-- count the data processed`
153			`-------------------------------------------------------------------------`
154			`process(sampling_counter, sampling, counter)`
155			`begin`
156			`sampling_counter_D <= sampling_counter;`
157
158			`case sampling is`
159			`---------------------------------------`
160			`-- gray Y -> Y -> Y ...`
161			`---------------------------------------`
162			`when "00" =>`
163			`sampling_counter_D <= "000";`
164			`---------------------------------------`
165			`-- 4:2:0 Y -> Y -> Y -> Y -> Cb -> Cr -> Y -> Y ...`
166			`---------------------------------------`
167			`when "01" =>`
168			`if (counter=63) then`
169			`sampling_counter_D <= sampling_counter + 1;`
170			`if (sampling_counter="101") then`
171			`sampling_counter_D <= "000";`
172			`end if;`
173			`end if;`
174			`---------------------------------------`
175			`-- 4:2:2 Y -> Y -> Cb -> Cr -> Y -> Y ...`
176			`---------------------------------------`
177			`when "10" =>`
178			`if (counter=63) then`
179			`sampling_counter_D <= sampling_counter + 1;`
180			`if (sampling_counter="011") then`
181			`sampling_counter_D <= "000";`
182			`end if;`
183			`end if;`
184			`---------------------------------------`
185			`-- 4:4:4 Y -> Cb -> Cr -> Y -> Cb ...`
186			`---------------------------------------`
187			`when others =>`
188			`if (counter=63) then`
189			`sampling_counter_D <= sampling_counter + 1;`
190			`if (sampling_counter="010") then`
191			`sampling_counter_D <= "000";`
192			`end if;`
193			`end if;`
194			`end case;`
195			`end process;`
196
197
198			`process(Clk)`
199			`begin`
200			`if (rising_edge(Clk)) then`
201			`if (reset='1') then`
202			`sampling_counter <= (others=>'0');`
203			`elsif ce='1' then`
204			`sampling_counter <= sampling_counter_D;`
205			`end if;`
206			`end if;`
207			`end process;`
208			`-------------------------------------------------------------------------`
209
210
211
212			`-------------------------------------------------------------------------`
213			`-- decide which table to use`
214			`-------------------------------------------------------------------------`
215			`process(select_qt, sampling_counter, sampling)`
216			`begin`
217			`select_qt_D <= select_qt;`
218
219			`case sampling is`
220
221			`---------------------------------------`
222			`-- gray`
223			`---------------------------------------`
224			`when "00" =>`
225			`select_qt_D <= context(1) & comp1_qt_number;`
226
227			`---------------------------------------`
228			`-- 4:2:0`
229			`---------------------------------------`
230			`when "01" =>`
231			`case sampling_counter is`
232			`when "000"\|"001"\|"010"\|"011" =>`
233			`select_qt_D <= context(1) & comp1_qt_number;`
234			`when "100" =>`
235			`select_qt_D <= context(1) & comp2_qt_number;`
236			`when "101" =>`
237			`select_qt_D <= context(1) & comp3_qt_number;`
238			`when others =>`
239			`end case;`
240
241			`---------------------------------------`
242			`-- 4:2:2`
243			`---------------------------------------`
244			`when "10" =>`
245			`case sampling_counter is`
246			`when "000"\|"001" =>`
247			`select_qt_D <= context(1) & comp1_qt_number;`
248			`when "010" =>`
249			`select_qt_D <= context(1) & comp2_qt_number;`
250			`when "011" =>`
251			`select_qt_D <= context(1) & comp3_qt_number;`
252			`when others =>`
253			`end case;`
254
255			`---------------------------------------`
256			`-- 4:4:4`
257			`---------------------------------------`
258			`when others =>`
259			`case sampling_counter is`
260			`when "000" =>`
261			`select_qt_D <= context(1) & comp1_qt_number;`
262			`when "001" =>`
263			`select_qt_D <= context(1) & comp2_qt_number;`
264			`when "010" =>`
265			`select_qt_D <= context(1) & comp3_qt_number;`
266			`when others =>`
267			`end case;`
268
269			`end case;`
270
271			`end process;`
272
273
274			`process(Clk)`
275			`begin`
276			`if rising_edge(Clk) then`
277			`select_qt <= select_qt_D;`
278			`end if;`
279			`end process;`
280			`-------------------------------------------------------------------------`
281
282
283
284
285			`-------------------------------------------------------------------------`
286			`-- process the right table`
287			`-------------------------------------------------------------------------`
288			`process( qt0_0_data_out, qt1_0_data_out, qt0_1_data_out, qt1_1_data_out,`
289			`ce, context, select_qt, qt_wea_i, header_select_i, qt_select_i, qt_data_i)`
290			`begin`
291
292			`qt0_0_ce <= '0';`
293			`qt1_0_ce <= '0';`
294			`qt0_1_ce <= '0';`
295			`qt1_1_ce <= '0';`
296			`qt0_0_data_in <= qt0_0_data_out;`
297			`qt1_0_data_in <= qt1_0_data_out;`
298			`qt0_1_data_in <= qt0_1_data_out;`
299			`qt1_1_data_in <= qt1_1_data_out;`
300
301			`if ce='1' and context(1)='0' and select_qt(0)='0' then`
302			`qt0_0_ce <= '1';`
303			`elsif ce='1' and context(1)='0' and select_qt(0)='1' then`
304			`qt1_0_ce <= '1';`
305			`elsif ce='1' and context(1)='1' and select_qt(0)='0' then`
306			`qt0_1_ce <= '1';`
307			`elsif ce='1' and context(1)='1' and select_qt(0)='1' then`
308			`qt1_1_ce <= '1';`
309			`end if;`
310
311			`-- fill the tables`
312			`if qt_wea_i='1' and header_select_i='0' and qt_select_i="00" then`
313			`qt0_0_ce <= '1';`
314			`qt0_0_data_in <= qt_data_i;`
315			`elsif qt_wea_i='1' and header_select_i='0' and qt_select_i="01" then`
316			`qt1_0_ce <= '1';`
317			`qt1_0_data_in <= qt_data_i;`
318			`elsif qt_wea_i='1' and header_select_i='1' and qt_select_i="00" then`
319			`qt0_1_ce <= '1';`
320			`qt0_1_data_in <= qt_data_i;`
321			`elsif qt_wea_i='1' and header_select_i='1' and qt_select_i="01" then`
322			`qt1_1_ce <= '1';`
323			`qt1_1_data_in <= qt_data_i;`
324			`end if;`
325
326			`-- end if;`
327			`end process;`
328			`-------------------------------------------------------------------------`
329
330			`-------------------------------------------------------------------------`
331			`-- select the right table for the multiplication`
332			`-------------------------------------------------------------------------`
333			`process(qt0_0_data_out, qt1_0_data_out, qt0_1_data_out, qt1_1_data_out, select_qt)`
334			`begin`
335			`if select_qt="00" then`
336			`qt_out <= qt0_0_data_out;`
337			`elsif select_qt="01" then`
338			`qt_out <= qt1_0_data_out;`
339			`elsif select_qt="10" then`
340			`qt_out <= qt0_1_data_out;`
341			`elsif select_qt="11" then`
342			`qt_out <= qt1_1_data_out;`
343			`end if;`
344			`end process;`
345			`-------------------------------------------------------------------------`
346
347
348			`-------------------------------------------------------------------------`
349			`-- Multiply`
350			`-------------------------------------------------------------------------`
351			`jpeg_dequant_multiplier_p : jpeg_dequant_multiplier`
352			`port map (`
353			`a => data_i,`
354			`b => qt_out,`
355			`o => data`
356			`);`
357			`-------------------------------------------------------------------------`
358
359			`-------------------------------------------------------------------------`
360			`-- circular shift registers for the tables`
361			`-------------------------------------------------------------------------`
362			`jpeg_qt_sr_0_0_p : jpeg_qt_sr`
363			`port map(`
364			`d => qt0_0_data_in,`
365			`clk => Clk,`
366			`ce => qt0_0_ce,`
367			`q => qt0_0_data_out`
368			`);`
369
370			`jpeg_qt_sr_1_0_p : jpeg_qt_sr`
371			`port map(`
372			`d => qt1_0_data_in,`
373			`clk => Clk,`
374			`ce => qt1_0_ce,`
375			`q => qt1_0_data_out`
376			`);`
377
378			`jpeg_qt_sr_0_1_p : jpeg_qt_sr`
379			`port map(`
380			`d => qt0_1_data_in,`
381			`clk => Clk,`
382			`ce => qt0_1_ce,`
383			`q => qt0_1_data_out`
384			`);`
385
386			`jpeg_qt_sr_1_1_p : jpeg_qt_sr`
387			`port map(`
388			`d => qt1_1_data_in,`
389			`clk => Clk,`
390			`ce => qt1_1_ce,`
391			`q => qt1_1_data_out`
392			`);`
393			`-------------------------------------------------------------------------`
394
395
396			`end IMP;`