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smanz |
----------------------------------------------------------------
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-- TODO:
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-- * select right Huffman-table according to compX_huff_Xc
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-- * store all tables in one bram (atm ht_nr_of_symbols are stored in distr.ram
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-- * continue to decode while write zrl and eob zeroes are written
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----------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity jpeg_huffman is
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port
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( Clk : in std_logic;
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reset_i : in std_logic;
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header_select_i: in std_logic;
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error_o : out std_logic;
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-- to initialize the bram
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ht_symbols_wea_i : in std_logic;
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ht_tables_wea_i : in std_logic;
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ht_select_i : in std_logic_vector(2 downto 0); -- bit 2: dc (low) or ac (high), bit 1 and 0: table-nr.
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ht_tables_address_i : in std_logic_vector(7 downto 0); -- address in bram: ht_select_i & ht_tables_address_i
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ht_nr_of_symbols_address_i : in std_logic_vector(3 downto 0); -- address in distrib-ram: ht_select_i & ht_nr_of_symbols_address_i
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ht_data_i : in std_logic_vector(7 downto 0);
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context_i : in std_logic_vector(3 downto 0);
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data_i : in std_logic_vector(7 downto 0);
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context_o : out std_logic_vector(3 downto 0);
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data_o : out std_logic_vector(15 downto 0);
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-- header data
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comp1_huff_dc_i : in std_logic_vector(3 downto 0);
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comp2_huff_dc_i : in std_logic_vector(3 downto 0);
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comp3_huff_dc_i : in std_logic_vector(3 downto 0);
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comp1_huff_ac_i : in std_logic_vector(3 downto 0);
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comp2_huff_ac_i : in std_logic_vector(3 downto 0);
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comp3_huff_ac_i : in std_logic_vector(3 downto 0);
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sampling_i : in std_logic_vector(3 downto 0); -- "00"->gray, "01"->4:2:0, "10"->4:2:2, "11"->4:4:4
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-- flow control
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datavalid_i : in std_logic;
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datavalid_o : out std_logic;
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ready_i : in std_logic;
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ready_o : out std_logic
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);
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end entity jpeg_huffman;
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architecture IMP of jpeg_huffman is
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-- store the number of huffman codes with length n (cf. jpeg-standard)
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component jpeg_ht_nr_of_symbols
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port (
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A : IN std_logic_VECTOR(7 downto 0); -- n = A+1
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CLK: IN std_logic;
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D : IN std_logic_VECTOR(7 downto 0);
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WE : IN std_logic;
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DPRA: IN std_logic_VECTOR(7 downto 0);
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DPO: OUT std_logic_VECTOR(7 downto 0);
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SPO: OUT std_logic_VECTOR(7 downto 0));
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end component;
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-- store the values of the huffman codes
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component jpeg_ht_tables
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port (
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clka : IN std_logic;
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dina : IN std_logic_VECTOR(7 downto 0);
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addra : IN std_logic_VECTOR(11 downto 0);
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wea : IN std_logic_VECTOR(0 downto 0);
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clkb: IN std_logic;
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addrb: IN std_logic_VECTOR(11 downto 0);
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doutb : OUT std_logic_VECTOR(7 downto 0));
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end component;
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-- Shiftregister, used to read 8-bits from imput and
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-- then provide it in the needed bit wise order
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component jpeg_huffman_input_sr
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port (
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CLK : IN std_logic;
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SDOUT : OUT std_logic;
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P_LOAD: IN std_logic;
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D : IN std_logic_VECTOR(7 downto 0);
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CE : IN std_logic;
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SCLR : IN std_logic);
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end component;
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signal err, err_D : std_logic :='0';
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type states is (st_start1, st_start2, st_start3, st_get_code, st_check_code1, st_check_code2, st_write_zeros_zrl, st_write_zeros_eob, st_write_zeros, st_get_value1, st_get_value2);
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signal state, state_D : states := st_start1;
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-- flow controll
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signal datavalid, datavalid_D : std_logic := '0';
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signal ready, ready_D : std_logic := '0';
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signal ce, ce_D : std_logic :='1';
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signal reset_flowcontroll : std_logic :='1';
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-- handle the "input shift register"
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signal sr_load, sr_load_D, last_ready, last_ready_D, sr_ce, sr_init : std_logic :='0';
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signal sr_empty : std_logic :='1';
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signal sr_counter, sr_counter_D : std_logic_vector(2 downto 0) := (others=>'0');
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-- final addresses
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signal ht_tables_address_ram_rd : std_logic_vector(11 downto 0) := (others=>'0');
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signal ht_tables_address_ram_wr : std_logic_vector(11 downto 0) := (others=>'0');
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signal ht_nr_of_symbols_address_ram_rd : std_logic_vector(7 downto 0) := (others=>'0');
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signal ht_nr_of_symbols_address_ram_wr : std_logic_vector(7 downto 0) := (others=>'0');
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-- data from the RAM
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signal data_symbols, data_tables : std_logic_vector(7 downto 0) := (others=>'0');
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-- signals to work with
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signal reset : std_logic :='0';
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signal context, context_D : std_logic_vector(3 downto 0) :=(others=>'0');
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signal data, data_D : std_logic_vector(15 downto 0) :=(others=>'0');
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signal get_bit, get_bit_D : std_logic :='0';
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signal dataready, dataready_D : std_logic :='0';
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signal data_intern : std_logic_vector(0 downto 0) := (others=>'0');
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signal code_read, code_read_D : std_logic_vector(15 downto 0) := (others=>'0');
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signal code_build, code_build_D : std_logic_vector(15 downto 0) := (others=>'0');
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signal symbols, symbols_D : std_logic_vector(7 downto 0) := (others=>'0');
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signal zeros_counter, zeros_counter_D : std_logic_vector(5 downto 0) := (others=>'0');
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-- internal address calculation
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signal ht_select, ht_select_D : std_logic_vector(2 downto 0) := (others=>'0');
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signal ht_tables_address, ht_tables_address_D : std_logic_vector(7 downto 0) := (others=>'0');
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signal ht_nr_of_symbols_address, ht_nr_of_symbols_address_D : std_logic_vector(3 downto 0) := (others=>'0');
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-- to choose between dc and ac table, also used as address to write data to -- TODO
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signal ac_dc_counter, ac_dc_counter_D : std_logic_vector(5 downto 0) := (others=>'0');
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-- to do the sampling
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signal sampling_counter, sampling_counter_D : std_logic_vector(2 downto 0) := (others=>'0');
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-- sign
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signal is_negative, is_negative_D : std_logic := '0';
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-- Context
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signal eob, eob_D : std_logic :='0';
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signal eoi, last_eoi : std_logic :='0';
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signal header_valid_out : std_logic := '0';
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signal header_select_out : std_logic := '0';
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signal header_select : std_logic := '0';
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signal sampling, sampling_D : std_logic_vector(1 downto 0) :=(others=>'0');
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-- remember the dc-coeffizient
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signal last_dc , last_dc_D, last_dc_reg : std_logic_vector(15 downto 0) := (others=>'0');
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signal last_dc_Y , last_dc_Cb, last_dc_Cr : std_logic_vector(15 downto 0) := (others=>'0');
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signal last_dc_Y_ce , last_dc_Cb_ce, last_dc_Cr_ce : std_logic := '0';
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signal last_dc_select, last_dc_select_D : std_logic_vector(1 downto 0) := (others=>'0');
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begin
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--***********************************************************************
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-- portmaps
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--***********************************************************************
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ht_nr_of_symbols : jpeg_ht_nr_of_symbols
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port map (
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A => ht_nr_of_symbols_address_ram_wr,
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CLK => Clk,
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D => ht_data_i,
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WE => ht_symbols_wea_i,
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DPRA => ht_nr_of_symbols_address_ram_rd,
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DPO => data_symbols
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);
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ht_table : jpeg_ht_tables
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port map (
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clka => Clk,
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dina => ht_data_i,
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addra => ht_tables_address_ram_wr,
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wea(0) => ht_tables_wea_i,
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clkb => Clk,
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addrb => ht_tables_address_ram_rd,
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doutb => data_tables
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);
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jpeg_huffman_input_sr_p : jpeg_huffman_input_sr
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port map (
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CLK => Clk,
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SDOUT => data_intern(0),
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P_LOAD => sr_load,
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D => data_i,
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CE => sr_ce,
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SCLR => reset); -- TODO: care about stuffed bits
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sr_ce <= (get_bit and ce) or sr_init;
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--***********************************************************************
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--***********************************************************************
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-- processes and wires
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--***********************************************************************
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-------------------------------------------------------------------------
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-- connect signal to outside
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-------------------------------------------------------------------------
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ready_o <= ready;
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error_o <= err;
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data_o <= data;
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reset <= reset_i or (eoi and not last_eoi);
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process(Clk)
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begin
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if rising_edge(Clk) then
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last_eoi <= eoi;
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end if;
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end process;
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--------------------------------------------------
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-- sampling
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process(header_select, sampling_i)
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begin
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if (header_select='0') then
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sampling_D <= sampling_i(1 downto 0);
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else
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sampling_D <= sampling_i(3 downto 2);
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end if;
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end process;
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process(Clk)
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begin
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if(rising_edge(Clk)) then
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if reset='1' then
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sampling <= (others=>'0');
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elsif(sr_ce='1') then
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sampling <= sampling_D;
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end if;
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end if;
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end process;
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--------------------------------------------------
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-- context_o <= eoi & eob & context_D(1 downto 0); -- This may cause problems :(
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context_o <= eoi & eob & header_select_out & header_valid_out;
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header_select <= context(1);
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process(Clk)
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begin
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if rising_edge(Clk) then
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if sr_ce = '1' then
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eoi <= context(3);
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header_select_out <= context(1);
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header_valid_out <= context(0);
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end if;
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end if;
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end process;
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process(Clk)
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begin
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if rising_edge(Clk) then
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if sr_ce = '1' and sr_load='1' then
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context <= context_i;
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end if;
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end if;
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end process;
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process(code_read, last_dc, ac_dc_counter, is_negative, dataready)
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begin
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data_D <= (others=>'0');
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last_dc_D <= last_dc;
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if(ac_dc_counter = 1 and dataready ='1') then
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if(is_negative='1') then
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data_D <= last_dc - code_read;
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last_dc_D <= last_dc - code_read;
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else
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data_D <= last_dc + code_read;
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last_dc_D <= last_dc + code_read;
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end if;
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elsif(dataready='1') then
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if(is_negative='1') then
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data_D <= 0 - code_read;
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else
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data_D <= code_read;
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end if;
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end if;
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end process;
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-- last_dc_D handled later to do the right sampling-method
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process(Clk)
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begin
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if rising_edge(Clk) then
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if reset='1' then
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data <= (others=>'0');
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elsif ce='1' then
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data <= data_D;
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end if;
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end if;
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end process;
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-------------------------------------------------------------------------
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-------------------------------------------------------------------------
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-- count the bits remaining in the shift register, refill it if neccessary
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-------------------------------------------------------------------------
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process(sr_ce, sr_counter, sr_load, datavalid_i)
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begin
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| 329 |
|
|
sr_counter_D <= sr_counter;
|
| 330 |
|
|
sr_load_D <= sr_load;
|
| 331 |
|
|
|
| 332 |
|
|
if (sr_ce='1') then
|
| 333 |
|
|
sr_counter_D <= sr_counter+1;
|
| 334 |
|
|
end if;
|
| 335 |
|
|
|
| 336 |
|
|
if (sr_counter="000" and sr_ce='1') then
|
| 337 |
|
|
sr_load_D <= '1';
|
| 338 |
|
|
end if;
|
| 339 |
|
|
|
| 340 |
|
|
if sr_load='1' and datavalid_i='1' and sr_ce='1' then
|
| 341 |
|
|
sr_load_D <='0';
|
| 342 |
|
|
end if;
|
| 343 |
|
|
|
| 344 |
|
|
ready_D <= sr_load and sr_ce and not last_ready;
|
| 345 |
|
|
last_ready_D <= (ready or last_ready) and sr_load; -- last_ready to prevent multiple loads on ce=0
|
| 346 |
|
|
end process;
|
| 347 |
|
|
|
| 348 |
|
|
process(Clk)
|
| 349 |
|
|
begin
|
| 350 |
|
|
if rising_edge(Clk) then
|
| 351 |
|
|
sr_counter <= sr_counter;
|
| 352 |
|
|
sr_load <= sr_load;
|
| 353 |
|
|
sr_init <= '0';
|
| 354 |
|
|
ready <= ready_D;
|
| 355 |
|
|
last_ready <= last_ready_D;
|
| 356 |
|
|
sr_empty <= sr_empty;
|
| 357 |
|
|
|
| 358 |
|
|
if reset='1' then
|
| 359 |
|
|
sr_counter <= "000";
|
| 360 |
|
|
sr_load <= '0';
|
| 361 |
|
|
last_ready <= '0';
|
| 362 |
|
|
ready <= '0';
|
| 363 |
|
|
sr_empty <= '1';
|
| 364 |
|
|
elsif sr_empty='1' and datavalid_i='1' then
|
| 365 |
|
|
sr_counter <= "001";
|
| 366 |
|
|
sr_load <= '1';
|
| 367 |
|
|
sr_init <= '1';
|
| 368 |
|
|
sr_empty <= '0';
|
| 369 |
|
|
elsif ce='1' then
|
| 370 |
|
|
sr_load <= sr_load_D;
|
| 371 |
|
|
sr_counter <= sr_counter_D;
|
| 372 |
|
|
end if;
|
| 373 |
|
|
|
| 374 |
|
|
end if;
|
| 375 |
|
|
end process;
|
| 376 |
|
|
-------------------------------------------------------------------------
|
| 377 |
|
|
|
| 378 |
|
|
|
| 379 |
|
|
-------------------------------------------------------------------------
|
| 380 |
|
|
-- flowcontroll with reset
|
| 381 |
|
|
-------------------------------------------------------------------------
|
| 382 |
|
|
datavalid_o <= datavalid and not (reset_i or reset_flowcontroll);
|
| 383 |
|
|
ce <= datavalid_i and (ready_i or not datavalid) and not (reset_i or reset_flowcontroll);
|
| 384 |
|
|
datavalid_D <= (dataready or (datavalid and (not ready_i))) and not (reset_i or reset_flowcontroll);
|
| 385 |
|
|
|
| 386 |
|
|
process(Clk)
|
| 387 |
|
|
begin
|
| 388 |
|
|
if rising_edge(Clk) then
|
| 389 |
|
|
datavalid <= datavalid_D; -- or (eoi and not last_eoi);
|
| 390 |
|
|
reset_flowcontroll <= reset_i;
|
| 391 |
|
|
end if;
|
| 392 |
|
|
end process;
|
| 393 |
|
|
-------------------------------------------------------------------------
|
| 394 |
|
|
|
| 395 |
|
|
|
| 396 |
|
|
|
| 397 |
|
|
-------------------------------------------------------------------------
|
| 398 |
|
|
-- store and recall the right diff-value for the dc-components
|
| 399 |
|
|
-------------------------------------------------------------------------
|
| 400 |
|
|
process(last_dc_select, sampling_counter, sampling)
|
| 401 |
|
|
begin
|
| 402 |
|
|
last_dc_select_D <= last_dc_select;
|
| 403 |
|
|
|
| 404 |
|
|
case sampling is
|
| 405 |
|
|
|
| 406 |
|
|
---------------------------------------
|
| 407 |
|
|
-- gray
|
| 408 |
|
|
---------------------------------------
|
| 409 |
|
|
when "00" =>
|
| 410 |
|
|
last_dc_select_D <= "00";
|
| 411 |
|
|
|
| 412 |
|
|
---------------------------------------
|
| 413 |
|
|
-- 4:2:0
|
| 414 |
|
|
---------------------------------------
|
| 415 |
|
|
when "01" =>
|
| 416 |
|
|
case sampling_counter is
|
| 417 |
|
|
when "000"|"001"|"010"|"011" =>
|
| 418 |
|
|
last_dc_select_D <= "00";
|
| 419 |
|
|
when "100" =>
|
| 420 |
|
|
last_dc_select_D <= "01";
|
| 421 |
|
|
when "101" =>
|
| 422 |
|
|
last_dc_select_D <= "10";
|
| 423 |
|
|
when others =>
|
| 424 |
|
|
last_dc_select_D <= "11";
|
| 425 |
|
|
end case;
|
| 426 |
|
|
|
| 427 |
|
|
---------------------------------------
|
| 428 |
|
|
-- 4:2:2
|
| 429 |
|
|
---------------------------------------
|
| 430 |
|
|
when "10" =>
|
| 431 |
|
|
case sampling_counter is
|
| 432 |
|
|
when "000"|"001" =>
|
| 433 |
|
|
last_dc_select_D <= "00";
|
| 434 |
|
|
when "010" =>
|
| 435 |
|
|
last_dc_select_D <= "01";
|
| 436 |
|
|
when "011" =>
|
| 437 |
|
|
last_dc_select_D <= "10";
|
| 438 |
|
|
when others =>
|
| 439 |
|
|
last_dc_select_D <= "11";
|
| 440 |
|
|
end case;
|
| 441 |
|
|
|
| 442 |
|
|
---------------------------------------
|
| 443 |
|
|
-- 4:4:4
|
| 444 |
|
|
---------------------------------------
|
| 445 |
|
|
when others =>
|
| 446 |
|
|
case sampling_counter is
|
| 447 |
|
|
when "000" =>
|
| 448 |
|
|
last_dc_select_D <= "00";
|
| 449 |
|
|
when "001" =>
|
| 450 |
|
|
last_dc_select_D <= "01";
|
| 451 |
|
|
when "010" =>
|
| 452 |
|
|
last_dc_select_D <= "10";
|
| 453 |
|
|
when others =>
|
| 454 |
|
|
last_dc_select_D <= "11";
|
| 455 |
|
|
end case;
|
| 456 |
|
|
|
| 457 |
|
|
end case;
|
| 458 |
|
|
|
| 459 |
|
|
end process;
|
| 460 |
|
|
|
| 461 |
|
|
|
| 462 |
|
|
process(last_dc_select, last_dc_Y ,last_dc_Cr, last_dc_Cb)
|
| 463 |
|
|
begin
|
| 464 |
|
|
last_dc_Y_ce <= '0';
|
| 465 |
|
|
last_dc_Cb_ce <= '0';
|
| 466 |
|
|
last_dc_Cr_ce <= '0';
|
| 467 |
|
|
last_dc <= (others=>'0');
|
| 468 |
|
|
|
| 469 |
|
|
case last_dc_select is
|
| 470 |
|
|
when "00" =>
|
| 471 |
|
|
last_dc_Y_ce <= '1';
|
| 472 |
|
|
last_dc <= last_dc_Y;
|
| 473 |
|
|
when "01" =>
|
| 474 |
|
|
last_dc_Cb_ce <= '1';
|
| 475 |
|
|
last_dc <= last_dc_Cb;
|
| 476 |
|
|
when "10" =>
|
| 477 |
|
|
last_dc_Cr_ce <= '1';
|
| 478 |
|
|
last_dc <= last_dc_Cr;
|
| 479 |
|
|
when others =>
|
| 480 |
|
|
-- this should not happen, maybe put some errordetection here
|
| 481 |
|
|
end case;
|
| 482 |
|
|
end process;
|
| 483 |
|
|
|
| 484 |
|
|
|
| 485 |
|
|
process(Clk)
|
| 486 |
|
|
begin
|
| 487 |
|
|
if rising_edge(Clk) then
|
| 488 |
|
|
if (reset='1') then
|
| 489 |
|
|
last_dc_select <= (others=>'0');
|
| 490 |
|
|
elsif ce='1' then
|
| 491 |
|
|
last_dc_select <= last_dc_select_D;
|
| 492 |
|
|
end if;
|
| 493 |
|
|
|
| 494 |
|
|
if (reset='1') then
|
| 495 |
|
|
last_dc_Y <= (others=>'0');
|
| 496 |
|
|
elsif ce='1' and last_dc_Y_ce='1' then
|
| 497 |
|
|
last_dc_Y <= last_dc_D;
|
| 498 |
|
|
end if;
|
| 499 |
|
|
|
| 500 |
|
|
if (reset='1') then
|
| 501 |
|
|
last_dc_Cb <= (others=>'0');
|
| 502 |
|
|
elsif ce='1' and last_dc_Cb_ce='1' then
|
| 503 |
|
|
last_dc_Cb <= last_dc_D;
|
| 504 |
|
|
end if;
|
| 505 |
|
|
|
| 506 |
|
|
if (reset='1') then
|
| 507 |
|
|
last_dc_Cr <= (others=>'0');
|
| 508 |
|
|
elsif ce='1' and last_dc_Cr_ce='1' then
|
| 509 |
|
|
last_dc_Cr <= last_dc_D;
|
| 510 |
|
|
end if;
|
| 511 |
|
|
end if;
|
| 512 |
|
|
end process;
|
| 513 |
|
|
-------------------------------------------------------------------------
|
| 514 |
|
|
|
| 515 |
|
|
|
| 516 |
|
|
|
| 517 |
|
|
|
| 518 |
|
|
|
| 519 |
|
|
|
| 520 |
|
|
|
| 521 |
|
|
|
| 522 |
|
|
-------------------------------------------------------------------------
|
| 523 |
|
|
-- choose right address for bram/distr-ram.
|
| 524 |
|
|
-------------------------------------------------------------------------
|
| 525 |
|
|
ht_tables_address_ram_wr <= header_select_i & ht_select_i & ht_tables_address_i;
|
| 526 |
|
|
ht_nr_of_symbols_address_ram_wr <= header_select_i & ht_select_i & ht_nr_of_symbols_address_i;
|
| 527 |
|
|
ht_tables_address_ram_rd <= header_select & ht_select & ht_tables_address;
|
| 528 |
|
|
ht_nr_of_symbols_address_ram_rd <= header_select & ht_select & ht_nr_of_symbols_address;
|
| 529 |
|
|
-------------------------------------------------------------------------
|
| 530 |
|
|
|
| 531 |
|
|
|
| 532 |
|
|
|
| 533 |
|
|
|
| 534 |
|
|
|
| 535 |
|
|
|
| 536 |
|
|
|
| 537 |
|
|
|
| 538 |
|
|
|
| 539 |
|
|
-------------------------------------------------------------------------
|
| 540 |
|
|
-- switch between ac/dc and between Y/Cb/Cr decoding by choosing right huffman-table
|
| 541 |
|
|
-------------------------------------------------------------------------
|
| 542 |
|
|
process(dataready, eob, sampling_counter, ht_select, sampling, state)
|
| 543 |
|
|
begin
|
| 544 |
|
|
ht_select_D <= ht_select;
|
| 545 |
|
|
sampling_counter_D <= sampling_counter;
|
| 546 |
|
|
|
| 547 |
|
|
|
| 548 |
|
|
case sampling is
|
| 549 |
|
|
|
| 550 |
|
|
---------------------------------------
|
| 551 |
|
|
-- gray Y -> Y -> Y ...
|
| 552 |
|
|
---------------------------------------
|
| 553 |
|
|
when "00" =>
|
| 554 |
|
|
ht_select_D(1 downto 0) <= "00";
|
| 555 |
|
|
|
| 556 |
|
|
if (eob='1') then
|
| 557 |
|
|
ht_select_D(2) <= '0';
|
| 558 |
|
|
elsif(dataready='1' and state/=st_write_zeros_eob) then
|
| 559 |
|
|
ht_select_D(2) <= '1';
|
| 560 |
|
|
end if;
|
| 561 |
|
|
|
| 562 |
|
|
---------------------------------------
|
| 563 |
|
|
-- 4:2:0 Y -> Y -> Y -> Y -> Cb -> Cr -> Y -> Y ...
|
| 564 |
|
|
---------------------------------------
|
| 565 |
|
|
when "01" =>
|
| 566 |
|
|
if (sampling_counter < 4) then
|
| 567 |
|
|
ht_select_D(1 downto 0) <= "00";
|
| 568 |
|
|
elsif (sampling_counter="100") then
|
| 569 |
|
|
ht_select_D(1 downto 0) <= "01";
|
| 570 |
|
|
elsif (sampling_counter="101") then
|
| 571 |
|
|
ht_select_D(1 downto 0) <= "01";
|
| 572 |
|
|
end if;
|
| 573 |
|
|
|
| 574 |
|
|
if (eob='1') then
|
| 575 |
|
|
ht_select_D(2) <= '0';
|
| 576 |
|
|
sampling_counter_D <= sampling_counter + 1;
|
| 577 |
|
|
if (sampling_counter="101") then
|
| 578 |
|
|
sampling_counter_D <= "000";
|
| 579 |
|
|
end if;
|
| 580 |
|
|
elsif(dataready='1' and state/=st_write_zeros_eob) then
|
| 581 |
|
|
ht_select_D(2) <= '1';
|
| 582 |
|
|
end if;
|
| 583 |
|
|
|
| 584 |
|
|
---------------------------------------
|
| 585 |
|
|
-- 4:2:2 Y -> Y -> Cb -> Cr -> Y -> Y ...
|
| 586 |
|
|
---------------------------------------
|
| 587 |
|
|
when "10" =>
|
| 588 |
|
|
if (sampling_counter < 2) then
|
| 589 |
|
|
ht_select_D(1 downto 0) <= "00";
|
| 590 |
|
|
else
|
| 591 |
|
|
ht_select_D(1 downto 0) <= "01";
|
| 592 |
|
|
end if;
|
| 593 |
|
|
|
| 594 |
|
|
if (eob='1') then
|
| 595 |
|
|
ht_select_D(2) <= '0';
|
| 596 |
|
|
sampling_counter_D <= sampling_counter + 1;
|
| 597 |
|
|
if (sampling_counter="011") then
|
| 598 |
|
|
sampling_counter_D <= "000";
|
| 599 |
|
|
end if;
|
| 600 |
|
|
elsif(dataready='1' and state/=st_write_zeros_eob) then
|
| 601 |
|
|
ht_select_D(2) <= '1';
|
| 602 |
|
|
end if;
|
| 603 |
|
|
|
| 604 |
|
|
---------------------------------------
|
| 605 |
|
|
-- 4:4:4 Y -> Cb -> Cr -> Y -> Cb ...
|
| 606 |
|
|
---------------------------------------
|
| 607 |
|
|
when others =>
|
| 608 |
|
|
if (sampling_counter = 0) then
|
| 609 |
|
|
ht_select_D(1 downto 0) <= "00";
|
| 610 |
|
|
else
|
| 611 |
|
|
ht_select_D(1 downto 0) <= "01";
|
| 612 |
|
|
end if;
|
| 613 |
|
|
|
| 614 |
|
|
if (eob='1') then
|
| 615 |
|
|
ht_select_D(2) <= '0';
|
| 616 |
|
|
sampling_counter_D <= sampling_counter + 1;
|
| 617 |
|
|
if (sampling_counter="010") then
|
| 618 |
|
|
sampling_counter_D <= "000";
|
| 619 |
|
|
end if;
|
| 620 |
|
|
elsif(dataready='1' and state/=st_write_zeros_eob) then
|
| 621 |
|
|
ht_select_D(2) <= '1';
|
| 622 |
|
|
end if;
|
| 623 |
|
|
|
| 624 |
|
|
end case;
|
| 625 |
|
|
|
| 626 |
|
|
end process;
|
| 627 |
|
|
|
| 628 |
|
|
|
| 629 |
|
|
process(Clk)
|
| 630 |
|
|
begin
|
| 631 |
|
|
if (rising_edge(Clk)) then
|
| 632 |
|
|
if (reset='1') then
|
| 633 |
|
|
ht_select <= (others=>'0');
|
| 634 |
|
|
sampling_counter <= (others=>'0');
|
| 635 |
|
|
elsif ce='1' then
|
| 636 |
|
|
ht_select <= ht_select_D;
|
| 637 |
|
|
sampling_counter <= sampling_counter_D;
|
| 638 |
|
|
end if;
|
| 639 |
|
|
end if;
|
| 640 |
|
|
end process;
|
| 641 |
|
|
-------------------------------------------------------------------------
|
| 642 |
|
|
|
| 643 |
|
|
|
| 644 |
|
|
|
| 645 |
|
|
|
| 646 |
|
|
|
| 647 |
|
|
|
| 648 |
|
|
|
| 649 |
|
|
|
| 650 |
|
|
-------------------------------------------------------------------------
|
| 651 |
|
|
-- the huffman decoding
|
| 652 |
|
|
-------------------------------------------------------------------------
|
| 653 |
|
|
process(data_intern, datavalid_i, ready_i, state, code_read, code_build,
|
| 654 |
|
|
symbols, data_symbols, data_tables, get_bit, err, ht_tables_address,
|
| 655 |
|
|
ht_nr_of_symbols_address, is_negative, ac_dc_counter, zeros_counter,
|
| 656 |
|
|
ht_select, dataready)
|
| 657 |
|
|
begin
|
| 658 |
|
|
err_D <= err;
|
| 659 |
|
|
state_D <= state;
|
| 660 |
|
|
dataready_D <= '0';
|
| 661 |
|
|
get_bit_D <= '0';
|
| 662 |
|
|
code_read_D <= code_read;
|
| 663 |
|
|
code_build_D <= code_build;
|
| 664 |
|
|
ht_tables_address_D <= ht_tables_address;
|
| 665 |
|
|
ht_nr_of_symbols_address_D <= ht_nr_of_symbols_address;
|
| 666 |
|
|
symbols_D <= symbols;
|
| 667 |
|
|
is_negative_D <= is_negative;
|
| 668 |
|
|
ac_dc_counter_D<= ac_dc_counter;
|
| 669 |
|
|
zeros_counter_D<= zeros_counter;
|
| 670 |
|
|
eob_D <= eob;
|
| 671 |
|
|
|
| 672 |
|
|
|
| 673 |
|
|
-- with the last of the 64 words signal eob as well
|
| 674 |
|
|
if ((ac_dc_counter = 0) and (dataready = '1')) then
|
| 675 |
|
|
eob_D <= '1';
|
| 676 |
|
|
else
|
| 677 |
|
|
eob_D <= '0';
|
| 678 |
|
|
end if;
|
| 679 |
|
|
|
| 680 |
|
|
|
| 681 |
|
|
|
| 682 |
|
|
case state is
|
| 683 |
|
|
when st_start1 =>
|
| 684 |
|
|
-- start reading a new huffman code
|
| 685 |
|
|
state_D <= st_start2;
|
| 686 |
|
|
ht_tables_address_D <= (others=>'0');
|
| 687 |
|
|
ht_nr_of_symbols_address_D <= (others=>'0');
|
| 688 |
|
|
code_build_D <= (others=>'0');
|
| 689 |
|
|
code_read_D <= (others=>'0');
|
| 690 |
|
|
|
| 691 |
|
|
-- important, do not remove
|
| 692 |
|
|
when st_start2 =>
|
| 693 |
|
|
state_D <= st_start3;
|
| 694 |
|
|
|
| 695 |
|
|
when st_start3 =>
|
| 696 |
|
|
state_D <= st_get_code;
|
| 697 |
|
|
get_bit_D <= '1';
|
| 698 |
|
|
|
| 699 |
|
|
-- append bit to existing code
|
| 700 |
|
|
when st_get_code =>
|
| 701 |
|
|
state_D <= st_check_code1;
|
| 702 |
|
|
code_read_D <= code_read(14 downto 0) & data_intern;
|
| 703 |
|
|
code_build_D <= code_build(14 downto 0) & '0';
|
| 704 |
|
|
ht_nr_of_symbols_address_D <= ht_nr_of_symbols_address + 1;
|
| 705 |
|
|
symbols_D <= data_symbols;
|
| 706 |
|
|
if (data_symbols=0) then
|
| 707 |
|
|
state_D <= st_get_code;
|
| 708 |
|
|
get_bit_D <= '1';
|
| 709 |
|
|
end if;
|
| 710 |
|
|
|
| 711 |
|
|
|
| 712 |
|
|
-- decode
|
| 713 |
|
|
when st_check_code1 =>
|
| 714 |
|
|
if (symbols = 0) then
|
| 715 |
|
|
state_D <= st_get_code;
|
| 716 |
|
|
get_bit_D <= '1';
|
| 717 |
|
|
elsif (code_build < code_read) then
|
| 718 |
|
|
code_build_D <= code_build + 1;
|
| 719 |
|
|
ht_tables_address_D <= ht_tables_address + 1;
|
| 720 |
|
|
symbols_D <= symbols - 1;
|
| 721 |
|
|
elsif (code_build = code_read) then
|
| 722 |
|
|
state_D <= st_check_code2;
|
| 723 |
|
|
code_read_D <= (others=>'0');
|
| 724 |
|
|
code_build_D <= (others=>'0');
|
| 725 |
|
|
else
|
| 726 |
|
|
state_D <= st_start1;
|
| 727 |
|
|
err_D <= '1';
|
| 728 |
|
|
end if;
|
| 729 |
|
|
|
| 730 |
|
|
|
| 731 |
|
|
-- check for EOB and ZRL, initialize value-readout otherwise
|
| 732 |
|
|
when st_check_code2 =>
|
| 733 |
|
|
if (data_tables = 0 and (ht_select(2) = '1')) then -- EOB
|
| 734 |
|
|
state_D <= st_write_zeros_eob;
|
| 735 |
|
|
dataready_D <='1';
|
| 736 |
|
|
zeros_counter_D <= 64 - ac_dc_counter;
|
| 737 |
|
|
ac_dc_counter_D <= ac_dc_counter + 1;
|
| 738 |
|
|
|
| 739 |
|
|
elsif (data_tables = 0 and (ht_select(2) = '0')) then -- to avoid overflow of code_build in next cycle
|
| 740 |
|
|
state_D <= st_start1;
|
| 741 |
|
|
ac_dc_counter_D <= ac_dc_counter + 1;
|
| 742 |
|
|
if (ac_dc_counter=0) then -- value 0 for dc component must be written (diff-value 0)
|
| 743 |
|
|
dataready_D <= '1';
|
| 744 |
|
|
end if;
|
| 745 |
|
|
|
| 746 |
|
|
elsif (data_tables = X"F0" and not (ht_select(2) = '0')) then -- ZRL
|
| 747 |
|
|
state_D <= st_write_zeros_zrl;
|
| 748 |
|
|
dataready_D<='1';
|
| 749 |
|
|
zeros_counter_D <= "010000";
|
| 750 |
|
|
ac_dc_counter_D <= ac_dc_counter + 1;
|
| 751 |
|
|
|
| 752 |
|
|
elsif(data_tables(7 downto 4)="0000") then
|
| 753 |
|
|
state_D <= st_get_value1;
|
| 754 |
|
|
code_build_D <= X"000" & data_tables(3 downto 0); -- in the next state this will be the counter
|
| 755 |
|
|
get_bit_D <= '1';
|
| 756 |
|
|
else
|
| 757 |
|
|
state_D <= st_write_zeros;
|
| 758 |
|
|
dataready_D<='1';
|
| 759 |
|
|
code_build_D <= X"000" & data_tables(3 downto 0); -- in the state st_get_valueX this will be the counter
|
| 760 |
|
|
zeros_counter_D <= "00" & data_tables(7 downto 4);
|
| 761 |
|
|
ac_dc_counter_D <= ac_dc_counter+1;
|
| 762 |
|
|
end if;
|
| 763 |
|
|
|
| 764 |
|
|
|
| 765 |
|
|
-- write zeroes and start with new code
|
| 766 |
|
|
when st_write_zeros_zrl | st_write_zeros_eob =>
|
| 767 |
|
|
dataready_D <='1';
|
| 768 |
|
|
ac_dc_counter_D <= ac_dc_counter+1;
|
| 769 |
|
|
zeros_counter_D <= zeros_counter-1;
|
| 770 |
|
|
if (zeros_counter=1) then
|
| 771 |
|
|
ac_dc_counter_D <= ac_dc_counter;
|
| 772 |
|
|
state_D <= st_start1;
|
| 773 |
|
|
dataready_D <='0';
|
| 774 |
|
|
end if;
|
| 775 |
|
|
|
| 776 |
|
|
-- write zeroes and read code
|
| 777 |
|
|
when st_write_zeros =>
|
| 778 |
|
|
dataready_D<='1';
|
| 779 |
|
|
ac_dc_counter_D <= ac_dc_counter+1;
|
| 780 |
|
|
zeros_counter_D <= zeros_counter-1;
|
| 781 |
|
|
if (zeros_counter=1) then
|
| 782 |
|
|
ac_dc_counter_D <= ac_dc_counter;
|
| 783 |
|
|
state_D <= st_get_value1;
|
| 784 |
|
|
dataready_D<='0';
|
| 785 |
|
|
get_bit_D <= '1';
|
| 786 |
|
|
end if;
|
| 787 |
|
|
|
| 788 |
|
|
|
| 789 |
|
|
-- read value
|
| 790 |
|
|
when st_get_value1 =>
|
| 791 |
|
|
if (data_intern = "1") then
|
| 792 |
|
|
code_read_D <= code_read(14 downto 0) & data_intern;
|
| 793 |
|
|
is_negative_D <= '0';
|
| 794 |
|
|
else
|
| 795 |
|
|
code_read_D <= code_read(14 downto 0) & (not data_intern);
|
| 796 |
|
|
is_negative_D <= '1';
|
| 797 |
|
|
end if;
|
| 798 |
|
|
|
| 799 |
|
|
if (code_build = 1) then
|
| 800 |
|
|
state_D <= st_start1;
|
| 801 |
|
|
dataready_D <='1';
|
| 802 |
|
|
ac_dc_counter_D <= ac_dc_counter + 1;
|
| 803 |
|
|
else
|
| 804 |
|
|
code_build_D <= code_build - 1;
|
| 805 |
|
|
get_bit_D <= '1';
|
| 806 |
|
|
state_D <= st_get_value2;
|
| 807 |
|
|
end if;
|
| 808 |
|
|
|
| 809 |
|
|
|
| 810 |
|
|
|
| 811 |
|
|
|
| 812 |
|
|
when st_get_value2 =>
|
| 813 |
|
|
if (is_negative='0') then
|
| 814 |
|
|
code_read_D <= code_read(14 downto 0) & data_intern;
|
| 815 |
|
|
else
|
| 816 |
|
|
code_read_D <= code_read(14 downto 0) & (not data_intern);
|
| 817 |
|
|
end if;
|
| 818 |
|
|
|
| 819 |
|
|
if (code_build = 1) then
|
| 820 |
|
|
state_D <= st_start1;
|
| 821 |
|
|
dataready_D <='1';
|
| 822 |
|
|
ac_dc_counter_D <= ac_dc_counter + 1;
|
| 823 |
|
|
else
|
| 824 |
|
|
code_build_D <= code_build - 1;
|
| 825 |
|
|
get_bit_D <= '1';
|
| 826 |
|
|
state_D <= st_get_value2;
|
| 827 |
|
|
end if;
|
| 828 |
|
|
|
| 829 |
|
|
end case;
|
| 830 |
|
|
|
| 831 |
|
|
|
| 832 |
|
|
end process;
|
| 833 |
|
|
-------------------------------------------------------------------------
|
| 834 |
|
|
|
| 835 |
|
|
|
| 836 |
|
|
|
| 837 |
|
|
|
| 838 |
|
|
|
| 839 |
|
|
-------------------------------------------------------------------------
|
| 840 |
|
|
-- Update registers on rising edge
|
| 841 |
|
|
-------------------------------------------------------------------------
|
| 842 |
|
|
process(Clk)
|
| 843 |
|
|
begin
|
| 844 |
|
|
if (rising_edge(Clk)) then
|
| 845 |
|
|
if(reset = '1') then
|
| 846 |
|
|
err <= '0';
|
| 847 |
|
|
state <= st_start1;
|
| 848 |
|
|
dataready <= '0';
|
| 849 |
|
|
get_bit <= '0';
|
| 850 |
|
|
code_read <= (others =>'0');
|
| 851 |
|
|
code_build <= (others =>'0');
|
| 852 |
|
|
ht_tables_address <= (others =>'0');
|
| 853 |
|
|
ht_nr_of_symbols_address <= (others =>'0');
|
| 854 |
|
|
symbols <= (others =>'0');
|
| 855 |
|
|
ac_dc_counter <= (others =>'0');
|
| 856 |
|
|
zeros_counter <= (others =>'0');
|
| 857 |
|
|
is_negative <= '0';
|
| 858 |
|
|
eob <= '0';
|
| 859 |
|
|
elsif ce='1' then
|
| 860 |
|
|
err <= err_D;
|
| 861 |
|
|
state <= state_D;
|
| 862 |
|
|
dataready <= dataready_D;
|
| 863 |
|
|
get_bit <= get_bit_D;
|
| 864 |
|
|
code_read <= code_read_D;
|
| 865 |
|
|
code_build <= code_build_D;
|
| 866 |
|
|
ht_tables_address <= ht_tables_address_D;
|
| 867 |
|
|
ht_nr_of_symbols_address <= ht_nr_of_symbols_address_D;
|
| 868 |
|
|
symbols <= symbols_D;
|
| 869 |
|
|
ac_dc_counter <= ac_dc_counter_D;
|
| 870 |
|
|
zeros_counter <= zeros_counter_D;
|
| 871 |
|
|
is_negative <= is_negative_D;
|
| 872 |
|
|
eob <= eob_D;
|
| 873 |
|
|
end if;
|
| 874 |
|
|
end if;
|
| 875 |
|
|
end process;
|
| 876 |
|
|
-------------------------------------------------------------------------
|
| 877 |
|
|
|
| 878 |
|
|
|
| 879 |
|
|
|
| 880 |
|
|
end IMP;
|
