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[/] [mjpeg-decoder/] [trunk/] [mjpeg/] [pcores/] [myipif/] [hdl/] [vhdl/] [jpeg_idct.vhd] - Blame information for rev 8

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Line No. Rev Author Line
1 2 smanz 
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity jpeg_idct is
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  port
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    (   Clk                             : in std_logic;
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                reset_i                 : in std_logic;
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                context_i               : in  std_logic_vector(3 downto 0);
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                data_i                  : in  std_logic_vector(11 downto 0);
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                context_o               : out std_logic_vector(3 downto 0);
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                data_o                  : out std_logic_vector(8 downto 0);
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                -- flow control
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                datavalid_i     : in std_logic;
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                datavalid_o     : out std_logic;
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                ready_i                 : in  std_logic;
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                ready_o                 : out std_logic
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    );
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end entity jpeg_idct;
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architecture IMP of jpeg_idct is
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        --------------------------------------------------------------
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        -- IDCT-Core
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        --------------------------------------------------------------
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        component jpeg_idct_core_12
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                port (
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                ND: IN std_logic;
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                RDY: OUT std_logic;
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                RFD: OUT std_logic;
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                CLK: IN std_logic;
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                RST: IN std_logic;
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                DIN: IN std_logic_VECTOR(11 downto 0);
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                DOUT: OUT std_logic_VECTOR(8 downto 0));
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        end component;
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        --------------------------------------------------------------
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        signal datavalid : std_logic :='0';
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        signal ready, last_ready : std_logic :='0';
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        signal block_counter : std_logic_vector(1 downto 0) :=(others=>'0');
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        signal out_counter, out_counter_D : std_logic_vector(7 downto 0) :=(others=>'0');
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        signal in_counter,  in_counter_D  : std_logic_vector(7 downto 0) :=(others=>'0');
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        signal eoi, eoi_D : std_logic_vector(3 downto 0) :=(others=>'0');
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        signal eoi_out, eoi_out_D : std_logic :='0';
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        signal header_select, header_select_D : std_logic_vector(3 downto 0) :=(others=>'0');
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        signal header_select_out, header_select_out_D : std_logic :='0';
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        signal context : std_logic_vector(3 downto 0) := (others=>'0');
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begin
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        --------------------------------------------------------------
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        -- dataflow
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        --------------------------------------------------------------
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        datavalid_o <= datavalid;
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        ready_o <= ready and last_ready and ready_i;
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        process(Clk)
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        begin
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                if rising_edge(Clk) then
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                        last_ready <= ready;
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                end if;
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        end process;
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        --------------------------------------------------------------
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        --------------------------------------------------------------
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        -- context (esp. eoi)
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        --------------------------------------------------------------
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        context_o <= context;
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        -- count to see when block is finished
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        out_counter_D   <= out_counter +1;
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        in_counter_D    <= in_counter +1;
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        process(Clk)
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        begin
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                if rising_edge(Clk) then
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                        if reset_i='1' then
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                                out_counter     <= (others=>'0');
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                        elsif(datavalid='1') then
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                                out_counter     <= out_counter_D;
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                        end if;
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                        if reset_i='1' then
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                                in_counter      <= (others=>'0');
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                        elsif(datavalid_i='1' and ready='1') then
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                                in_counter      <= in_counter_D;
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                        end if;
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                end if;
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        end process;
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        -- remember header_select to write while block is shifted out
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        process(context_i, in_counter, out_counter, header_select)
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        begin
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                header_select_D <= header_select;
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                if in_counter(5 downto 0) = "111101" then                --      just a random counter_value less than "1111111" and greater than "000000"
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                        case in_counter(7 downto 6) is
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                        when "00" =>
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                                header_select_D(0) <= context_i(1);
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                        when "01" =>
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                                header_select_D(1) <= context_i(1);
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                        when "10" =>
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                                header_select_D(2) <= context_i(1);
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                        when others =>
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                                header_select_D(3) <= context_i(1);
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                        end case;
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                end if;
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                case out_counter(7 downto 6) is
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                when "00" =>
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                        header_select_out_D <= header_select(0);
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                when "01" =>
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                        header_select_out_D <= header_select(1);
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                when "10" =>
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                        header_select_out_D <= header_select(2);
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                when others =>
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                        header_select_out_D <= header_select(3);
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                end case;
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        end process;
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        -- remember received eoi to write after block is finished
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        process(eoi, context_i, in_counter, out_counter)
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        begin
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                eoi_D <= eoi;
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                eoi_out_D <='0';
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                if context_i(3)='1' then
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                        case in_counter(7 downto 6) is
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                        when "00" =>
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                                eoi_D(0) <= '1';
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                        when "01" =>
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                                eoi_D(1) <= '1';
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                        when "10" =>
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                                eoi_D(2) <= '1';
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                        when others =>
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                                eoi_D(3) <= '1';
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                        end case;
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                elsif(out_counter(5 downto 0)="000000") then
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                        case out_counter(7 downto 6) is
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                        when "00" =>
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                                eoi_D(0) <= '0';
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                                eoi_out_D <= eoi(0);
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                        when "01" =>
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                                eoi_D(1) <= '0';
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                                eoi_out_D <= eoi(1);
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                        when "10" =>
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                                eoi_D(2) <= '0';
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                                eoi_out_D <= eoi(2);
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                        when others =>
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                                eoi_D(3) <= '0';
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                                eoi_out_D <= eoi(3);
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                        end case;
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                end if;
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        end process;
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        process(Clk)
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        begin
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                if rising_edge(Clk) then
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                        eoi                                     <= eoi_D;
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                        eoi_out                                 <= eoi_out_D;
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                        header_select           <= header_select_D;
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                        header_select_out       <= header_select_out_D;
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                        context <= '0' & context(2 downto 0);
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                        if reset_i='1' then
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                                eoi             <= "0000";
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                                eoi_out <= '0';
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                                context <= (others=>'0');
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                                header_select           <= (others=>'0');
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                                header_select_out       <= '0';
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                        elsif(out_counter(5 downto 0)="000000") then
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                                context <= eoi_out & '0' & header_select_out & '0';
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                        end if;
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                end if;
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        end process;
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        --------------------------------------------------------------
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        --------------------------------------------------------------
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        -- IDCT-Core
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        --------------------------------------------------------------
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        jpeg_idct_core_12_p : jpeg_idct_core_12
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                        port map (
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                        ND => datavalid_i,
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                                RDY => datavalid,
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                                RFD => ready,
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                                CLK => CLK,
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                                RST => reset_i,
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                                DIN => data_i,
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                                DOUT => data_o);
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        --------------------------------------------------------------
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end IMP;
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