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smanz |
---------------------------------------------------------------
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-- This code is a simplified port from the Verilog sources that can be found here:
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-- http://embedded.olin.edu/xilinx_docs/projects/bitvga-v2p.php
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-- The Verilog sources are based on code from Xilinx and released under
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-- "Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License"
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-- with the note, that Xilinx claims the following copyright:
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
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-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
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-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
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-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
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-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
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-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
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-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
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-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
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-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
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-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
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-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE.
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--
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-- (c) Copyright 2004 Xilinx, Inc.
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-- All rights reserved.
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---------------------------------------------------------------
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------------------------------
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-- Suffix vga for 25MHz-clock-domain
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------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity vga is
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generic(
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MAX_LINE_COUNT : integer := 479
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);
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port(
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Clk : in std_logic;
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reset_i : in std_logic;
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eoi_i : in std_logic;
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red_i : in STD_LOGIC_VECTOR (7 downto 0);
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green_i : in STD_LOGIC_VECTOR (7 downto 0);
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blue_i : in STD_LOGIC_VECTOR (7 downto 0);
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width_i : in std_logic_vector(15 downto 0);
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height_i : in std_logic_vector(15 downto 0);
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sampling_i : in std_logic_vector( 1 downto 0);
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VGA_OUT_PIXEL_CLOCK: out STD_LOGIC;
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VGA_COMP_SYNCH: out STD_LOGIC;
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VGA_OUT_BLANK_Z: out STD_LOGIC;
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VGA_HSYNCH: out STD_LOGIC;
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VGA_VSYNCH: out STD_LOGIC;
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VGA_OUT_RED: out STD_LOGIC_VECTOR (7 downto 0);
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VGA_OUT_GREEN: out STD_LOGIC_VECTOR (7 downto 0);
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VGA_OUT_BLUE: out STD_LOGIC_VECTOR (7 downto 0);
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-- -- chipscope-debugging
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-- chipscope_o : out std_logic_vector(127 downto 0);
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-- flow controll
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datavalid_i : in std_logic;
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ready_o : out std_logic
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);
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end entity vga;
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architecture IMP of vga is
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------------------------------------------------------------
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-- VGA output
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------------------------------------------------------------
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component vga_signals is
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port (
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SYSTEM_CLOCK: in STD_LOGIC;
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VGA_OUT_PIXEL_CLOCK: out STD_LOGIC;
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VGA_COMP_SYNCH: out STD_LOGIC;
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VGA_OUT_BLANK_Z: out STD_LOGIC;
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VGA_HSYNCH: out STD_LOGIC;
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VGA_VSYNCH: out STD_LOGIC;
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o_pixel_clock: out STD_LOGIC;
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o_pixel_count: out STD_LOGIC_VECTOR (10 downto 0);
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o_line_count: out STD_LOGIC_VECTOR (9 downto 0)
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);
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end component vga_signals;
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------------------------------------------------------------
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------------------------------------------------------------
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-- VGA Memory Buffer
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------------------------------------------------------------
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component vga_memory
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port (
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clka: IN std_logic;
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dina: IN std_logic_VECTOR(7 downto 0);
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addra: IN std_logic_VECTOR(14 downto 0);
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wea: IN std_logic_VECTOR(0 downto 0);
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clkb: IN std_logic;
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addrb: IN std_logic_VECTOR(14 downto 0);
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doutb: OUT std_logic_VECTOR(7 downto 0));
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end component;
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------------------------------------------------------------
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-- Clock domain crossing
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signal eoi, vga_eoi, vga_eoi_D : std_logic :='0'; -- opb-Clk -> vga-clk
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signal reset, vga_reset, vga_reset_D : std_logic :='0'; -- opb-Clk -> vga-clk
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signal reset_hold, reset_hold_D : std_logic_vector(3 downto 0) :=(others=>'0');
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signal width, vga_width, vga_width_D : std_logic_vector(15 downto 0) :=(others=>'0'); -- opb-Clk -> vga-clk
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signal height, vga_height, vga_height_D : std_logic_vector(15 downto 0) :=(others=>'0'); -- opb-Clk -> vga-clk
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signal sampling, vga_sampling, vga_sampling_D : std_logic_vector(1 downto 0) := (others=>'0'); -- opb-Clk -> vga-clk
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signal vga_pixel_count : std_logic_vector(10 downto 0) := (others=>'0'); -- vga-clk -> OPB-clk
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signal line_count, line_count_D, vga_line_count : std_logic_vector(9 downto 0) := (others=>'0'); -- vga-clk -> OPB-clk
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signal memory_select, memory_select_D : std_logic :='0'; -- vga-clk -> OPB-clk
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signal vga_memory_select, vga_memory_select_D : std_logic :='0';
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signal vga_out_of_picture, vga_out_of_picture_D : std_logic :='0';
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signal blocks_per_line, blocks_per_line_D : std_logic_vector(7 downto 0); -- opb-Clk -> vga-clk
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signal vga_blocks_per_line, vga_blocks_per_line_D : std_logic_vector(7 downto 0);
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-- OPB-Clk
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signal stop_writing, stop_writing_D : std_logic :='1';
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signal ready, ready_D : std_logic :='0';
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signal last_memory_select, last_memory_select_D : std_logic :='0';
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signal memory_addra, memory_addra_D : std_logic_vector(13 downto 0) :=(others=>'0');
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signal memory_addra_final : std_logic_vector(14 downto 0) :=(others=>'0');
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-- vga-clk
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signal vga_pixel_clock : std_logic :='0';
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signal vga_out_blank_z_intern : std_logic :='0';
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signal vga_memory_red, vga_memory_green, vga_memory_blue : std_logic_vector(7 downto 0) :=(others=>'0');
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signal vga_memory_addrb, vga_memory_addrb_D : std_logic_vector(13 downto 0) :=(others=>'0');
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signal vga_memory_addrb_final : std_logic_vector(14 downto 0) :=(others=>'0');
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signal vga_last_line_count, vga_last_line_count_D : std_logic :='0';
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begin
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-- **********************************************************************************************
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-- * Wires
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-- **********************************************************************************************
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--chipscope_o <= red_i & green_i & blue_i & sampling_i & eoi_i & reset_i & datavalid_i & '0' & ready & vga_out_of_picture &
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-- vga_memory_red & vga_memory_green & vga_memory_blue & vga_out_blank_z_intern & (vga_out_blank_z_intern and not vga_out_of_picture and not vga_reset) & "000000" &
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-- X"0" & blocks_per_line & memory_addra_final & vga_memory_addrb_final &
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-- "0" & vga_pixel_count & vga_line_count;
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--VGA_OUT_RED <= vga_memory_red;
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--VGA_OUT_GREEN <= memory_addra_final(14 downto 7);
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--VGA_OUT_BLUE <= vga_memory_addrb(7 downto 0);
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VGA_OUT_RED <= vga_memory_red;
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VGA_OUT_GREEN <= vga_memory_green;
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VGA_OUT_BLUE <= vga_memory_blue;
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VGA_OUT_BLANK_Z <= vga_out_blank_z_intern and not vga_out_of_picture and not vga_reset;
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eoi <= eoi_i;
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width <= width_i;
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height <= height_i;
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sampling <= sampling_i;
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ready_o <= ready;
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reset <= reset_i;
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-- **********************************************************************************************
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-- * OPB-Clk domain (100 MHz)
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-- **********************************************************************************************
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-- to control writing
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process(line_count, eoi, stop_writing, height)
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begin
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stop_writing_D <= stop_writing;
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if (line_count=0) then
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stop_writing_D <= '0';
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end if;
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if (line_count= MAX_LINE_COUNT or line_count=height-1) then -- maybe height-1
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stop_writing_D <='1';
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end if;
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end process;
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process(Clk)
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begin
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if rising_edge(Clk) then
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if (reset='1' or eoi='1') then
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stop_writing <= '1';
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else
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stop_writing <= stop_writing_D;
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end if;
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end if;
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end process;
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--------------------------------------------------------------
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-- Calc blocks per line - this is necessary because jpeg fills
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-- the picture on the right (and bottom) side to have a width
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-- (and height) that is a multiple of 8
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--------------------------------------------------------------
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process(width, sampling)
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begin
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case sampling is
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when "01" | "10" => -- 4:2:2 and 4:2:0
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if width(3 downto 0)="0000" then
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blocks_per_line_D <= width(11 downto 4);
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else
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blocks_per_line_D <= width(11 downto 4) + 1;
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end if;
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when others => -- 4:4:4 and gray
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if width(2 downto 0)="000" then
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blocks_per_line_D <= width(10 downto 3);
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else
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blocks_per_line_D <= width(10 downto 3) + 1;
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end if;
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end case;
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end process;
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process(Clk)
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begin
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if rising_edge(Clk) then
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blocks_per_line <= blocks_per_line_D;
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end if;
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end process;
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--------------------------------------------------------------
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--------------------------------------------------------------
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-- Calc the write-address for vga_memory
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--------------------------------------------------------------
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process(memory_addra, datavalid_i, ready, memory_select, last_memory_select)
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begin
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last_memory_select_D <= memory_select;
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memory_addra_D <= memory_addra;
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if(memory_select /= last_memory_select) then
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memory_addra_D <= (others=>'0');
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elsif (datavalid_i='1' and ready='1') then
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memory_addra_D <= memory_addra + 1;
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end if;
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end process;
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process(Clk)
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begin
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if rising_edge(Clk) then
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last_memory_select <= last_memory_select_D;
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if reset='1' or eoi='1' then
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memory_addra <= (others=>'0');
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else
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memory_addra <= memory_addra_D;
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end if;
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end if;
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end process;
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--------------------------------------------------------------
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--------------------------------------------------------------
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-- calc vga-ready
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--------------------------------------------------------------
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process(memory_addra, ready, blocks_per_line, sampling, stop_writing)
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begin
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ready_D <= ready;
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case sampling is
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when "01" =>
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if( (memory_addra = (blocks_per_line & "00000000") ) or
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(stop_writing='1') ) then
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ready_D <= '0';
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end if;
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when "10" =>
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if( (memory_addra = (blocks_per_line & "0000000") ) or
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(stop_writing='1') ) then
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ready_D <= '0';
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end if;
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when others =>
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if( (memory_addra = (blocks_per_line & "000000") ) or
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(stop_writing='1') ) then
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ready_D <= '0';
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end if;
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end case;
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if(memory_addra = 0 and stop_writing='0') then
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ready_D <= '1';
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end if;
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end process;
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process(Clk)
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begin
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if rising_edge(Clk) then
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if reset='1' or eoi='1'then
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ready <= '0';
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else
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ready <= ready_D;
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end if;
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end if;
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end process;
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--------------------------------------------------------------
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-- **********************************************************************************************
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-- * Clock Domain Crossing
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-- **********************************************************************************************
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------------------------------------------------------------
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-- Dual port bram for data (opb-clk -> vga-clk)
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------------------------------------------------------------
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vga_memory_red_p:vga_memory
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port map (
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clka => Clk,
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dina => red_i,
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addra => memory_addra_final,
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wea(0)=> datavalid_i,
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clkb => vga_pixel_clock,
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addrb => vga_memory_addrb_final,
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doutb => vga_memory_red
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);
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vga_memory_green_p:vga_memory
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345 |
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port map (
|
346 |
|
|
clka => Clk,
|
347 |
|
|
dina => green_i,
|
348 |
|
|
addra => memory_addra_final,
|
349 |
|
|
wea(0)=> datavalid_i,
|
350 |
|
|
clkb => vga_pixel_clock,
|
351 |
|
|
addrb => vga_memory_addrb_final,
|
352 |
|
|
doutb => vga_memory_green
|
353 |
|
|
);
|
354 |
|
|
vga_memory_blue_p:vga_memory
|
355 |
|
|
port map (
|
356 |
|
|
clka => Clk,
|
357 |
|
|
dina => blue_i,
|
358 |
|
|
addra => memory_addra_final,
|
359 |
|
|
wea(0)=> datavalid_i,
|
360 |
|
|
clkb => vga_pixel_clock,
|
361 |
|
|
addrb => vga_memory_addrb_final,
|
362 |
|
|
doutb => vga_memory_blue
|
363 |
|
|
);
|
364 |
|
|
|
365 |
|
|
memory_addra_final <= memory_select & (memory_addra);
|
366 |
|
|
vga_memory_addrb_final <= not vga_memory_select & vga_memory_addrb;
|
367 |
|
|
------------------------------------------------------------
|
368 |
|
|
|
369 |
|
|
|
370 |
|
|
|
371 |
|
|
------------------------------------------------------------
|
372 |
|
|
-- vga-clk -> opb-clk
|
373 |
|
|
------------------------------------------------------------
|
374 |
|
|
process(Clk)
|
375 |
|
|
begin
|
376 |
|
|
if rising_edge(Clk) then
|
377 |
|
|
|
378 |
|
|
line_count_D <= vga_line_count;
|
379 |
|
|
line_count <= line_count_D;
|
380 |
|
|
|
381 |
|
|
memory_select_D <= vga_memory_select;
|
382 |
|
|
memory_select <= memory_select_D;
|
383 |
|
|
|
384 |
|
|
end if;
|
385 |
|
|
end process;
|
386 |
|
|
------------------------------------------------------------
|
387 |
|
|
|
388 |
|
|
|
389 |
|
|
|
390 |
|
|
------------------------------------------------------------
|
391 |
|
|
-- opb-clk -> vga-clk
|
392 |
|
|
------------------------------------------------------------
|
393 |
|
|
process(vga_pixel_clock)
|
394 |
|
|
begin
|
395 |
|
|
if rising_edge(Clk) then
|
396 |
|
|
|
397 |
|
|
vga_sampling_D <= sampling;
|
398 |
|
|
vga_sampling <= vga_sampling_D;
|
399 |
|
|
|
400 |
|
|
vga_width_D <= width;
|
401 |
|
|
vga_width <= vga_width_D;
|
402 |
|
|
|
403 |
|
|
vga_height_D<= height;
|
404 |
|
|
vga_height <= vga_height_D;
|
405 |
|
|
|
406 |
|
|
end if;
|
407 |
|
|
end process;
|
408 |
|
|
------------------------------------------------------------
|
409 |
|
|
|
410 |
|
|
|
411 |
|
|
|
412 |
|
|
|
413 |
|
|
|
414 |
|
|
|
415 |
|
|
|
416 |
|
|
|
417 |
|
|
-- **********************************************************************************************
|
418 |
|
|
-- * VGA-Clock-Domain (25 MHz)
|
419 |
|
|
-- **********************************************************************************************
|
420 |
|
|
|
421 |
|
|
------------------------------------------------------------
|
422 |
|
|
-- Generate VGA-Signals and VGA-Clock
|
423 |
|
|
------------------------------------------------------------
|
424 |
|
|
vgacard:vga_signals
|
425 |
|
|
Port map (
|
426 |
|
|
SYSTEM_CLOCK => Clk,
|
427 |
|
|
|
428 |
|
|
VGA_OUT_PIXEL_CLOCK => VGA_OUT_PIXEL_CLOCK,
|
429 |
|
|
VGA_COMP_SYNCH => VGA_COMP_SYNCH,
|
430 |
|
|
VGA_OUT_BLANK_Z => vga_out_blank_z_intern,
|
431 |
|
|
VGA_HSYNCH => VGA_HSYNCH,
|
432 |
|
|
VGA_VSYNCH => VGA_VSYNCH,
|
433 |
|
|
o_pixel_clock => vga_pixel_clock,
|
434 |
|
|
o_pixel_count => vga_pixel_count,
|
435 |
|
|
o_line_count => vga_line_count
|
436 |
|
|
);
|
437 |
|
|
------------------------------------------------------------
|
438 |
|
|
|
439 |
|
|
--------------------------------------------------------------
|
440 |
|
|
-- is VGA-Coordinate "outside of the picture"?
|
441 |
|
|
--------------------------------------------------------------
|
442 |
|
|
process(vga_pixel_count, vga_line_count, vga_height, vga_width)
|
443 |
|
|
begin
|
444 |
|
|
if( (vga_pixel_count-1 >= vga_width) or (vga_line_count-16 >= vga_height) ) then -- TODO
|
445 |
|
|
vga_out_of_picture_D <= '1';
|
446 |
|
|
else
|
447 |
|
|
vga_out_of_picture_D <= '0';
|
448 |
|
|
end if;
|
449 |
|
|
end process;
|
450 |
|
|
|
451 |
|
|
process(vga_pixel_clock)
|
452 |
|
|
begin
|
453 |
|
|
if rising_edge(vga_pixel_clock) then
|
454 |
|
|
vga_out_of_picture <= vga_out_of_picture_D;
|
455 |
|
|
end if;
|
456 |
|
|
end process;
|
457 |
|
|
--------------------------------------------------------------
|
458 |
|
|
|
459 |
|
|
|
460 |
|
|
--------------------------------------------------------------
|
461 |
|
|
-- Calc the read-address for vga_memory
|
462 |
|
|
--------------------------------------------------------------
|
463 |
|
|
process(vga_memory_addrb, vga_memory_select, vga_pixel_count, vga_line_count, vga_sampling)
|
464 |
|
|
begin
|
465 |
|
|
|
466 |
|
|
vga_last_line_count_D <= vga_line_count(0);
|
467 |
|
|
vga_memory_select_D <= vga_memory_select;
|
468 |
|
|
vga_memory_addrb_D <= vga_memory_addrb;
|
469 |
|
|
|
470 |
|
|
case vga_sampling is
|
471 |
|
|
when "01" => -- 4:2:0
|
472 |
|
|
if ( vga_line_count(3 downto 0) = "0000" and vga_last_line_count /= vga_line_count(0)) then
|
473 |
|
|
vga_memory_select_D <= not vga_memory_select;
|
474 |
|
|
vga_memory_addrb_D <= (others=>'0');
|
475 |
|
|
elsif (vga_last_line_count /= vga_line_count(0)) then
|
476 |
|
|
vga_memory_addrb_D <= "000000" & (vga_line_count(3 downto 0)) & "0000";
|
477 |
|
|
elsif ( vga_pixel_count(3 downto 0)="0000" ) then
|
478 |
|
|
vga_memory_addrb_D <= vga_memory_addrb + 241;
|
479 |
|
|
else
|
480 |
|
|
vga_memory_addrb_D <= vga_memory_addrb + 1;
|
481 |
|
|
end if;
|
482 |
|
|
when "10" => -- 4:2:2
|
483 |
|
|
if ( vga_line_count(2 downto 0) = "000" and vga_last_line_count /= vga_line_count(0)) then
|
484 |
|
|
vga_memory_select_D <= not vga_memory_select;
|
485 |
|
|
vga_memory_addrb_D <= (others=>'0');
|
486 |
|
|
elsif (vga_last_line_count /= vga_line_count(0)) then
|
487 |
|
|
vga_memory_addrb_D <= "0000000" & (vga_line_count(2 downto 0)) & "0000";
|
488 |
|
|
elsif ( vga_pixel_count(3 downto 0)="0000" ) then
|
489 |
|
|
vga_memory_addrb_D <= vga_memory_addrb + 113;
|
490 |
|
|
else
|
491 |
|
|
vga_memory_addrb_D <= vga_memory_addrb + 1;
|
492 |
|
|
end if;
|
493 |
|
|
when others=> -- gray or 4:4:4
|
494 |
|
|
if ( vga_line_count(2 downto 0) = "000" and vga_last_line_count /= vga_line_count(0)) then
|
495 |
|
|
vga_memory_select_D <= not vga_memory_select;
|
496 |
|
|
vga_memory_addrb_D <= (others=>'0');
|
497 |
|
|
elsif (vga_last_line_count /= vga_line_count(0)) then
|
498 |
|
|
vga_memory_addrb_D <= "00000000" & (vga_line_count(2 downto 0)) & "000";
|
499 |
|
|
elsif ( vga_pixel_count(2 downto 0)="000" ) then
|
500 |
|
|
vga_memory_addrb_D <= vga_memory_addrb + 57;
|
501 |
|
|
else
|
502 |
|
|
vga_memory_addrb_D <= vga_memory_addrb + 1;
|
503 |
|
|
end if;
|
504 |
|
|
end case;
|
505 |
|
|
|
506 |
|
|
end process;
|
507 |
|
|
|
508 |
|
|
process(vga_pixel_clock)
|
509 |
|
|
begin
|
510 |
|
|
if rising_edge(vga_pixel_clock) then
|
511 |
|
|
vga_last_line_count <= vga_last_line_count_D;
|
512 |
|
|
vga_memory_select <= vga_memory_select_D;
|
513 |
|
|
vga_memory_addrb <= vga_memory_addrb_D;
|
514 |
|
|
end if;
|
515 |
|
|
end process;
|
516 |
|
|
--------------------------------------------------------------
|
517 |
|
|
|
518 |
|
|
|
519 |
|
|
|
520 |
|
|
end IMP;
|