OpenCores
URL https://opencores.org/ocsvn/mjpeg-decoder/mjpeg-decoder/trunk

Subversion Repositories mjpeg-decoder

[/] [mjpeg-decoder/] [trunk/] [mjpeg/] [system.make] - Blame information for rev 8

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 smanz
#################################################################
2
# Makefile generated by Xilinx Platform Studio
3
# Project:/home/smanz/Diplomarbeit/main/trunk/mjpeg/system.xmp
4
#################################################################
5
 
6
# Name of the Microprocessor system
7
# The hardware specification of the system is in file :
8
# /home/smanz/Diplomarbeit/main/trunk/mjpeg/system.mhs
9
# The software specification of the system is in file :
10
# /home/smanz/Diplomarbeit/main/trunk/mjpeg/system.mss
11
 
12
include system_incl.make
13
 
14
 
15
#################################################################
16
# EXTERNAL TARGETS
17
#################################################################
18
all:
19
        @echo "Makefile to build a Microprocessor system :"
20
        @echo "Run make with any of the following targets"
21
        @echo " "
22
        @echo "  netlist  : Generates the netlist for the given MHS "
23
        @echo "  bits     : Runs Implementation tools to generate the bitstream"
24
        @echo "  exporttopn:Export to ProjNav"
25
        @echo " "
26
        @echo "  libs     : Configures the sw libraries for this system"
27
        @echo "  program  : Compiles the program sources for all the processor instances"
28
        @echo " "
29
        @echo "  init_bram: Initializes bitstream with BRAM data"
30
        @echo "  ace      : Generate ace file from bitstream and elf"
31
        @echo "  download : Downloads the bitstream onto the board"
32
        @echo " "
33
        @echo "  sim      : Generates HDL simulation models and runs simulator for chosen simulation mode"
34
        @echo "  simmodel : Generates HDL simulation models for chosen simulation mode"
35
        @echo "  behavioral:Generates behavioral HDL models with BRAM initialization"
36
        @echo "  structural:Generates structural simulation HDL models with BRAM initialization"
37
        @echo "  timing   : Generates timing simulation HDL models with BRAM initialization"
38
        @echo "  vp       : Generates virtual platform model"
39
        @echo " "
40
        @echo "  netlistclean: Deletes netlist"
41
        @echo "  bitsclean: Deletes bit, ncd, bmm files"
42
        @echo "  hwclean  : Deletes implementation dir"
43
        @echo "  libsclean: Deletes sw libraries"
44
        @echo "  programclean: Deletes compiled ELF files"
45
        @echo "  swclean  : Deletes sw libraries and ELF files"
46
        @echo "  simclean : Deletes simulation dir"
47
        @echo "  vpclean  : Deletes virtualplatform dir"
48
        @echo "  clean    : Deletes all generated files/directories"
49
        @echo " "
50
        @echo "  make  : (Default)"
51
        @echo "      Creates a Microprocessor system using default initializations"
52
        @echo "      specified for each processor in MSS file"
53
 
54
 
55
bits: $(SYSTEM_BIT)
56
 
57
ace: $(SYSTEM_ACE)
58
 
59
netlist: $(POSTSYN_NETLIST)
60
 
61
libs: $(LIBRARIES)
62
 
63
program: $(ALL_USER_ELF_FILES)
64
 
65
download: $(DOWNLOAD_BIT) dummy
66
        @echo "*********************************************"
67
        @echo "Downloading Bitstream onto the target board"
68
        @echo "*********************************************"
69
        impact -batch etc/download.cmd
70
 
71
init_bram: $(DOWNLOAD_BIT)
72
 
73
sim: $(DEFAULT_SIM_SCRIPT)
74
        cd simulation/behavioral; \
75
        $(SIM_CMD)  &
76
 
77
simmodel: $(DEFAULT_SIM_SCRIPT)
78
 
79
behavioral_model: $(BEHAVIORAL_SIM_SCRIPT)
80
 
81
structural_model: $(STRUCTURAL_SIM_SCRIPT)
82
 
83
vp: $(VPEXEC)
84
 
85
clean: hwclean libsclean programclean simclean vpclean
86
        rm -f _impact.cmd
87
 
88
hwclean: netlistclean bitsclean
89
        rm -rf implementation synthesis xst hdl
90
        rm -rf xst.srp $(SYSTEM).srp
91
 
92
netlistclean:
93
        rm -f $(POSTSYN_NETLIST)
94
        rm -f $(BMM_FILE)
95
 
96
bitsclean:
97
        rm -f $(SYSTEM_BIT)
98
        rm -f implementation/$(SYSTEM).ncd
99
        rm -f implementation/$(SYSTEM)_bd.bmm
100
 
101
bitsclean:
102
 
103
simclean:
104
        rm -rf simulation/behavioral
105
 
106
swclean: libsclean programclean
107
        @echo ""
108
 
109
libsclean: $(LIBSCLEAN_TARGETS)
110
 
111
programclean: $(PROGRAMCLEAN_TARGETS)
112
 
113
vpclean:
114
        rm -rf virtualplatform
115
 
116
#################################################################
117
# SOFTWARE PLATFORM FLOW
118
#################################################################
119
 
120
 
121
$(LIBRARIES): $(MHSFILE) $(MSSFILE) __xps/libgen.opt
122
        @echo "*********************************************"
123
        @echo "Creating software libraries..."
124
        @echo "*********************************************"
125
        libgen $(LIBGEN_OPTIONS) $(MSSFILE)
126
 
127
 
128
ppc405_0_libsclean:
129
        rm -rf ppc405_0/lib/
130
 
131
ppc405_1_libsclean:
132
        rm -rf ppc405_1/lib/
133
 
134
#################################################################
135
# SOFTWARE APPLICATION TESTAPP_MEMORY
136
#################################################################
137
 
138
TestApp_Memory_program: $(TESTAPP_MEMORY_OUTPUT)
139
 
140
$(TESTAPP_MEMORY_OUTPUT) : $(TESTAPP_MEMORY_SOURCES) $(TESTAPP_MEMORY_HEADERS) $(TESTAPP_MEMORY_LINKER_SCRIPT) \
141
                    $(LIBRARIES) __xps/testapp_memory_compiler.opt
142
        @mkdir -p $(TESTAPP_MEMORY_OUTPUT_DIR)
143
        $(TESTAPP_MEMORY_CC) $(TESTAPP_MEMORY_CC_OPT) $(TESTAPP_MEMORY_SOURCES) -o $(TESTAPP_MEMORY_OUTPUT) \
144
        $(TESTAPP_MEMORY_OTHER_CC_FLAGS) $(TESTAPP_MEMORY_INCLUDES) $(TESTAPP_MEMORY_LIBPATH) \
145
        $(TESTAPP_MEMORY_CFLAGS) $(TESTAPP_MEMORY_LFLAGS)
146
        $(TESTAPP_MEMORY_CC_SIZE) $(TESTAPP_MEMORY_OUTPUT)
147
        @echo ""
148
 
149
TestApp_Memory_programclean:
150
        rm -f $(TESTAPP_MEMORY_OUTPUT)
151
 
152
#################################################################
153
# SOFTWARE APPLICATION TESTAPP_PERIPHERAL
154
#################################################################
155
 
156
TestApp_Peripheral_program: $(TESTAPP_PERIPHERAL_OUTPUT)
157
 
158
$(TESTAPP_PERIPHERAL_OUTPUT) : $(TESTAPP_PERIPHERAL_SOURCES) $(TESTAPP_PERIPHERAL_HEADERS) $(TESTAPP_PERIPHERAL_LINKER_SCRIPT) \
159
                    $(LIBRARIES) __xps/testapp_peripheral_compiler.opt
160
        @mkdir -p $(TESTAPP_PERIPHERAL_OUTPUT_DIR)
161
        $(TESTAPP_PERIPHERAL_CC) $(TESTAPP_PERIPHERAL_CC_OPT) $(TESTAPP_PERIPHERAL_SOURCES) -o $(TESTAPP_PERIPHERAL_OUTPUT) \
162
        $(TESTAPP_PERIPHERAL_OTHER_CC_FLAGS) $(TESTAPP_PERIPHERAL_INCLUDES) $(TESTAPP_PERIPHERAL_LIBPATH) \
163
        $(TESTAPP_PERIPHERAL_CFLAGS) $(TESTAPP_PERIPHERAL_LFLAGS)
164
        $(TESTAPP_PERIPHERAL_CC_SIZE) $(TESTAPP_PERIPHERAL_OUTPUT)
165
        @echo ""
166
 
167
TestApp_Peripheral_programclean:
168
        rm -f $(TESTAPP_PERIPHERAL_OUTPUT)
169
 
170
#################################################################
171
# BOOTLOOP ELF FILES
172
#################################################################
173
 
174
 
175
 
176
$(PPC405_0_BOOTLOOP): $(PPC405_BOOTLOOP)
177
        @mkdir -p $(BOOTLOOP_DIR)
178
        cp -f $(PPC405_BOOTLOOP) $(PPC405_0_BOOTLOOP)
179
 
180
$(PPC405_1_BOOTLOOP): $(PPC405_BOOTLOOP)
181
        @mkdir -p $(BOOTLOOP_DIR)
182
        cp -f $(PPC405_BOOTLOOP) $(PPC405_1_BOOTLOOP)
183
 
184
#################################################################
185
# HARDWARE IMPLEMENTATION FLOW
186
#################################################################
187
 
188
 
189
$(BMM_FILE) \
190
$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \
191
                      $(CORE_STATE_DEVELOPMENT_FILES)
192
        @echo "****************************************************"
193
        @echo "Creating system netlist for hardware specification.."
194
        @echo "****************************************************"
195
        platgen $(PLATGEN_OPTIONS) $(MHSFILE)
196
 
197
$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES)
198
        @echo "Running synthesis..."
199
        bash -c "cd synthesis; ./synthesis.sh"
200
 
201
$(SYSTEM_BIT): $(FPGA_IMP_DEPENDENCY)
202
        @echo "*********************************************"
203
        @echo "Running Xilinx Implementation tools.."
204
        @echo "*********************************************"
205
        @cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf
206
        @cp -f $(XFLOW_OPT_FILE) implementation/xflow.opt
207
        xflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngc
208
        @echo "*********************************************"
209
        @echo "Running Bitgen.."
210
        @echo "*********************************************"
211
        @cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut
212
        cd implementation; bitgen -w -f bitgen.ut $(SYSTEM)
213
 
214
exporttopn:
215
        @echo "You have chosen XPS for implementation tool flow."
216
        @echo "Please select ProjNav as your implementation flow in Project Options."
217
        @echo "In batch mode, use commad xset pnproj ."
218
 
219
$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_FILES) __xps/bitinit.opt
220
        @cp -f implementation/$(SYSTEM)_bd.bmm .
221
        @echo "*********************************************"
222
        @echo "Initializing BRAM contents of the bitstream"
223
        @echo "*********************************************"
224
        bitinit $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_FILE_ARGS) \
225
        -bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT)
226
        @rm -f $(SYSTEM)_bd.bmm
227
 
228
$(SYSTEM_ACE):
229
        @echo "In order to generate ace file, you must have:-"
230
        @echo "- exactly one processor."
231
        @echo "- opb_mdm, if using microblaze."
232
 
233
#################################################################
234
# SIMULATION FLOW
235
#################################################################
236
 
237
 
238
################## BEHAVIORAL SIMULATION ##################
239
 
240
$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \
241
                          $(BRAMINIT_ELF_FILES)
242
        @echo "*********************************************"
243
        @echo "Creating behavioral simulation models..."
244
        @echo "*********************************************"
245
        simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE)
246
 
247
################## STRUCTURAL SIMULATION ##################
248
 
249
$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \
250
                          $(BRAMINIT_ELF_FILES)
251
        @echo "*********************************************"
252
        @echo "Creating structural simulation models..."
253
        @echo "*********************************************"
254
        simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE)
255
 
256
 
257
################## TIMING SIMULATION ##################
258
 
259
$(TIMING_SIM_SCRIPT): $(SYSTEM_BIT) __xps/simgen.opt \
260
                      $(BRAMINIT_ELF_FILES)
261
        @echo "*********************************************"
262
        @echo "Creating timing simulation models..."
263
        @echo "*********************************************"
264
        simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE)
265
 
266
#################################################################
267
# VIRTUAL PLATFORM FLOW
268
#################################################################
269
 
270
 
271
$(VPEXEC): $(MHSFILE) __xps/vpgen.opt
272
        @echo "****************************************************"
273
        @echo "Creating virtual platform for hardware specification.."
274
        @echo "****************************************************"
275
        vpgen $(VPGEN_OPTIONS) $(MHSFILE)
276
 
277
dummy:
278
        @echo ""
279
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.