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[/] [mjpeg-decoder/] [trunk/] [mjpeg/] [system.mhs] - Blame information for rev 8

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1 2 smanz 
# ##############################################################################
2 
# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
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# Fri Jun 22 12:14:26 2007
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# Target Board:  Xilinx XUP Virtex-II Pro Development System Rev C
5 
# Family:        virtex2p
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# Device:        xc2vp30
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# Package:       ff896
8 
# Speed Grade:   -7
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# Processor: PPC 405
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# Processor clock frequency: 100.000000 MHz
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# Bus clock frequency: 100.000000 MHz
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# Debug interface: FPGA JTAG
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# On Chip Memory : 128 KB
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# Total Off Chip Memory : 512 MB
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# - DDR_SDRAM_64Mx64 Dual Rank = 256 MB
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# - DDR_512MB_64Mx64_rank2_row13_col10_cl2_5 = 256 MB
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# ##############################################################################
18 
 
19 
 
20 
 PARAMETER VERSION = 2.1.0
21 
 
22 
 
23 
 PORT fpga_0_RS232_Uart_1_RX_pin = fpga_0_RS232_Uart_1_RX, DIR = I
24 
 PORT fpga_0_RS232_Uart_1_TX_pin = fpga_0_RS232_Uart_1_TX, DIR = O
25 
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk, DIR = O, VEC = [0:2]
26 
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn, DIR = O, VEC = [0:2]
27 
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr, DIR = O, VEC = [0:12]
28 
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr, DIR = O, VEC = [0:1]
29 
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn, DIR = O
30 
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn, DIR = O
31 
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn, DIR = O
32 
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM, DIR = O, VEC = [0:7]
33 
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS, DIR = IO, VEC = [0:7]
34 
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ, DIR = IO, VEC = [0:63]
35 
 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE, DIR = O, VEC = [0:1]
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 PORT fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn_pin = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn, DIR = O, VEC = [0:1]
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 PORT fpga_0_DDR_CLK_FB = ddr_feedback_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
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 PORT fpga_0_DDR_CLK_FB_OUT = ddr_clk_feedback_out_s, DIR = O
39 
 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
40 
 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
41 
 PORT myipif_0_LEDs_pin = myipif_0_LEDs, DIR = O, VEC = [3:0]
42 
 PORT myipif_0_VGA_OUT_PIXEL_CLOCK_pin = myipif_0_VGA_OUT_PIXEL_CLOCK, DIR = O
43 
 PORT myipif_0_VGA_COMP_SYNCH_pin = myipif_0_VGA_COMP_SYNCH, DIR = O
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 PORT myipif_0_VGA_OUT_BLANK_Z_pin = myipif_0_VGA_OUT_BLANK_Z, DIR = O
45 
 PORT myipif_0_VGA_HSYNCH_pin = myipif_0_VGA_HSYNCH, DIR = O
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 PORT myipif_0_VGA_VSYNCH_pin = myipif_0_VGA_VSYNCH, DIR = O
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 PORT myipif_0_VGA_OUT_RED_pin = myipif_0_VGA_OUT_RED, DIR = O, VEC = [7:0]
48 
 PORT myipif_0_VGA_OUT_GREEN_pin = myipif_0_VGA_OUT_GREEN, DIR = O, VEC = [7:0]
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 PORT myipif_0_VGA_OUT_BLUE_pin = myipif_0_VGA_OUT_BLUE, DIR = O, VEC = [7:0]
50 
 PORT myipif_0_SWITCHEs_pin = myipif_0_SWITCHEs, DIR = I, VEC = [3:0]
51 
 PORT myipif_0_BUTTONs_pin = myipif_0_BUTTONs, DIR = I, VEC = [4:0]
52 
 
53 
 
54 
BEGIN ppc405
55 
 PARAMETER INSTANCE = ppc405_0
56 
 PARAMETER HW_VER = 2.00.c
57 
 BUS_INTERFACE IPLB = plb
58 
 BUS_INTERFACE DPLB = plb
59 
 BUS_INTERFACE JTAGPPC = jtagppc_0_JTAGPPC0
60 
 PORT PLBCLK = sys_clk_s
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 PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
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 PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
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 PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
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 PORT RSTC405RESETCHIP = RSTC405RESETCHIP
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 PORT RSTC405RESETCORE = RSTC405RESETCORE
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 PORT RSTC405RESETSYS = RSTC405RESETSYS
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 PORT CPMC405CLOCK = sys_clk_s
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END
69 
 
70 
BEGIN jtagppc_cntlr
71 
 PARAMETER INSTANCE = jtagppc_0
72 
 PARAMETER HW_VER = 2.00.a
73 
 BUS_INTERFACE JTAGPPC0 = jtagppc_0_JTAGPPC0
74 
 BUS_INTERFACE JTAGPPC1 = jtagppc_0_JTAGPPC1
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END
76 
 
77 
BEGIN proc_sys_reset
78 
 PARAMETER INSTANCE = reset_block
79 
 PARAMETER HW_VER = 1.00.a
80 
 PARAMETER C_EXT_RESET_HIGH = 0
81 
 PORT Ext_Reset_In = sys_rst_s
82 
 PORT Slowest_sync_clk = sys_clk_s
83 
 PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
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 PORT Core_Reset_Req = C405RSTCORERESETREQ
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 PORT System_Reset_Req = C405RSTSYSRESETREQ
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 PORT Rstc405resetchip = RSTC405RESETCHIP
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 PORT Rstc405resetcore = RSTC405RESETCORE
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 PORT Rstc405resetsys = RSTC405RESETSYS
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 PORT Bus_Struct_Reset = sys_bus_reset
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 PORT Dcm_locked = dcm_1_lock
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END
92 
 
93 
BEGIN plb_v34
94 
 PARAMETER INSTANCE = plb
95 
 PARAMETER HW_VER = 1.02.a
96 
 PARAMETER C_DCR_INTFCE = 0
97 
 PARAMETER C_EXT_RESET_HIGH = 1
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 PORT SYS_Rst = sys_bus_reset
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 PORT PLB_Clk = sys_clk_s
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END
101 
 
102 
BEGIN opb_v20
103 
 PARAMETER INSTANCE = opb
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 PARAMETER HW_VER = 1.10.c
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 PARAMETER C_EXT_RESET_HIGH = 1
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 PORT SYS_Rst = sys_bus_reset
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 PORT OPB_Clk = sys_clk_s
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END
109 
 
110 
BEGIN plb2opb_bridge
111 
 PARAMETER INSTANCE = plb2opb
112 
 PARAMETER HW_VER = 1.01.a
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 PARAMETER C_DCR_INTFCE = 0
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 PARAMETER C_NUM_ADDR_RNG = 1
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 PARAMETER C_RNG0_BASEADDR = 0x00000000
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 PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
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 BUS_INTERFACE MOPB = opb
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 BUS_INTERFACE SPLB = plb
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END
120 
 
121 
BEGIN opb_uartlite
122 
 PARAMETER INSTANCE = RS232_Uart_1
123 
 PARAMETER HW_VER = 1.00.b
124 
 PARAMETER C_BAUDRATE = 9600
125 
 PARAMETER C_DATA_BITS = 8
126 
 PARAMETER C_ODD_PARITY = 0
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 PARAMETER C_USE_PARITY = 0
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 PARAMETER C_CLK_FREQ = 100000000
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 PARAMETER C_BASEADDR = 0x40600000
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 PARAMETER C_HIGHADDR = 0x4060ffff
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 BUS_INTERFACE SOPB = opb
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 PORT RX = fpga_0_RS232_Uart_1_RX
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 PORT TX = fpga_0_RS232_Uart_1_TX
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END
135 
 
136 
BEGIN opb_ddr
137 
 PARAMETER INSTANCE = DDR_512MB_64Mx64_rank2_row13_col10_cl2_5
138 
 PARAMETER HW_VER = 2.00.c
139 
 PARAMETER C_OPB_CLK_PERIOD_PS = 10000
140 
 PARAMETER C_NUM_BANKS_MEM = 2
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 PARAMETER C_NUM_CLK_PAIRS = 4
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 PARAMETER C_REG_DIMM = 0
143 
 PARAMETER C_DDR_TMRD = 20000
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 PARAMETER C_DDR_TWR = 20000
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 PARAMETER C_DDR_TRAS = 60000
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 PARAMETER C_DDR_TRC = 90000
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 PARAMETER C_DDR_TRFC = 100000
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 PARAMETER C_DDR_TRCD = 30000
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 PARAMETER C_DDR_TRRD = 20000
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 PARAMETER C_DDR_TRP = 30000
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 PARAMETER C_DDR_TREFC = 70300000
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 PARAMETER C_DDR_AWIDTH = 13
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 PARAMETER C_DDR_COL_AWIDTH = 10
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 PARAMETER C_DDR_BANK_AWIDTH = 2
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 PARAMETER C_DDR_DWIDTH = 64
156 
 PARAMETER C_MEM0_BASEADDR = 0x00000000
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 PARAMETER C_MEM0_HIGHADDR = 0x0fffffff
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 PARAMETER C_MEM1_BASEADDR = 0x10000000
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 PARAMETER C_MEM1_HIGHADDR = 0x1fffffff
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 PARAMETER C_INCLUDE_BURST_SUPPORT = 1
161 
 BUS_INTERFACE SOPB = opb
162 
 PORT DDR_Addr = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Addr
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 PORT DDR_BankAddr = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_BankAddr
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 PORT DDR_CASn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CASn
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 PORT DDR_CKE = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CKE
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 PORT DDR_CSn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_CSn
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 PORT DDR_RASn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_RASn
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 PORT DDR_WEn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_WEn
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 PORT DDR_DM = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DM
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 PORT DDR_DQS = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQS
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 PORT DDR_DQ = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_DQ
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 PORT DDR_Clk = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clk & ddr_clk_feedback_out_s
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 PORT DDR_Clkn = fpga_0_DDR_512MB_64Mx64_rank2_row13_col10_cl2_5_DDR_Clkn & 0b0
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 PORT Device_Clk90_in = clk_90_s
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 PORT Device_Clk90_in_n = clk_90_n_s
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 PORT Device_Clk = sys_clk_s
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 PORT Device_Clk_n = sys_clk_n_s
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 PORT DDR_Clk90_in = ddr_clk_90_s
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 PORT DDR_Clk90_in_n = ddr_clk_90_n_s
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END
181 
 
182 
BEGIN plb_bram_if_cntlr
183 
 PARAMETER INSTANCE = plb_bram_if_cntlr_1
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 PARAMETER HW_VER = 1.00.b
185 
 PARAMETER c_plb_clk_period_ps = 10000
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 PARAMETER c_baseaddr = 0xfffe0000
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 PARAMETER c_highaddr = 0xffffffff
188 
 BUS_INTERFACE SPLB = plb
189 
 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
190 
END
191 
 
192 
BEGIN bram_block
193 
 PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
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 PARAMETER HW_VER = 1.00.a
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 BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
196 
END
197 
 
198 
BEGIN util_vector_logic
199 
 PARAMETER INSTANCE = sysclk_inv
200 
 PARAMETER HW_VER = 1.00.a
201 
 PARAMETER C_SIZE = 1
202 
 PARAMETER C_OPERATION = not
203 
 PORT Op1 = sys_clk_s
204 
 PORT Res = sys_clk_n_s
205 
END
206 
 
207 
BEGIN util_vector_logic
208 
 PARAMETER INSTANCE = clk90_inv
209 
 PARAMETER HW_VER = 1.00.a
210 
 PARAMETER C_SIZE = 1
211 
 PARAMETER C_OPERATION = not
212 
 PORT Op1 = clk_90_s
213 
 PORT Res = clk_90_n_s
214 
END
215 
 
216 
BEGIN util_vector_logic
217 
 PARAMETER INSTANCE = ddr_clk90_inv
218 
 PARAMETER HW_VER = 1.00.a
219 
 PARAMETER C_SIZE = 1
220 
 PARAMETER C_OPERATION = not
221 
 PORT Op1 = ddr_clk_90_s
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 PORT Res = ddr_clk_90_n_s
223 
END
224 
 
225 
BEGIN dcm_module
226 
 PARAMETER INSTANCE = dcm_0
227 
 PARAMETER HW_VER = 1.00.a
228 
 PARAMETER C_CLK0_BUF = TRUE
229 
 PARAMETER C_CLK90_BUF = TRUE
230 
 PARAMETER C_CLKIN_PERIOD = 10.000000
231 
 PARAMETER C_CLK_FEEDBACK = 1X
232 
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
233 
 PARAMETER C_EXT_RESET_HIGH = 1
234 
 PORT CLKIN = dcm_clk_s
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 PORT CLK0 = sys_clk_s
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 PORT CLK90 = clk_90_s
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 PORT CLKFB = sys_clk_s
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 PORT RST = net_gnd
239 
 PORT LOCKED = dcm_0_lock
240 
END
241 
 
242 
BEGIN dcm_module
243 
 PARAMETER INSTANCE = dcm_1
244 
 PARAMETER HW_VER = 1.00.a
245 
 PARAMETER C_CLK0_BUF = TRUE
246 
 PARAMETER C_CLK90_BUF = TRUE
247 
 PARAMETER C_CLKIN_PERIOD = 10.000000
248 
 PARAMETER C_CLK_FEEDBACK = 1X
249 
 PARAMETER C_DLL_FREQUENCY_MODE = LOW
250 
 PARAMETER C_PHASE_SHIFT = 60
251 
 PARAMETER C_CLKOUT_PHASE_SHIFT = FIXED
252 
 PARAMETER C_EXT_RESET_HIGH = 0
253 
 PORT CLKIN = ddr_feedback_s
254 
 PORT CLK90 = ddr_clk_90_s
255 
 PORT CLK0 = dcm_1_FB
256 
 PORT CLKFB = dcm_1_FB
257 
 PORT RST = dcm_0_lock
258 
 PORT LOCKED = dcm_1_lock
259 
END
260 
 
261 
BEGIN myipif
262 
 PARAMETER INSTANCE = myipif_0
263 
 PARAMETER C_BASEADDR = 0x50000000
264 
 PARAMETER C_HIGHADDR = 0x5000FFFF
265 
 BUS_INTERFACE MSOPB = opb
266 
 PORT LEDs = myipif_0_LEDs
267 
 PORT BUTTONs = myipif_0_BUTTONs
268 
 PORT SWITCHEs = myipif_0_SWITCHEs
269 
 PORT VGA_OUT_PIXEL_CLOCK = myipif_0_VGA_OUT_PIXEL_CLOCK
270 
 PORT VGA_COMP_SYNCH = myipif_0_VGA_COMP_SYNCH
271 
 PORT VGA_OUT_BLANK_Z = myipif_0_VGA_OUT_BLANK_Z
272 
 PORT VGA_HSYNCH = myipif_0_VGA_HSYNCH
273 
 PORT VGA_VSYNCH = myipif_0_VGA_VSYNCH
274 
 PORT VGA_OUT_RED = myipif_0_VGA_OUT_RED
275 
 PORT VGA_OUT_GREEN = myipif_0_VGA_OUT_GREEN
276 
 PORT VGA_OUT_BLUE = myipif_0_VGA_OUT_BLUE
277 
END
278 
 
279 
BEGIN ppc405
280 
 PARAMETER INSTANCE = ppc405_1
281 
 PARAMETER HW_VER = 2.00.c
282 
 BUS_INTERFACE JTAGPPC = jtagppc_0_JTAGPPC1
283 
END
284 
 

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