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[/] [mkjpeg/] [branches/] [16rgb/] [trunk/] [design/] [JFIFGen/] [HeaderRAM.v] - Blame information for rev 37

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1 37 mikel262
module HeaderRam(d, waddr, raddr, we, clk, q);
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output [7:0] q;
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input [7:0] d;
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input[9:0] raddr;
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input[9:0] waddr;
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input clk, we;
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reg [9:0] read_addr;
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reg[7:0] mem [1023:0] /* synthesis syn_ramstyle="block_ram" */;
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initial $readmemh("header.hex", mem);
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assign q = mem[read_addr];
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always @(posedge clk) begin
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if (we)
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mem[waddr] <= d;
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read_addr <= raddr;
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end
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endmodule

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