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[/] [mkjpeg/] [branches/] [16rgb/] [trunk/] [design/] [rle/] [RLE.VHD] - Blame information for rev 48

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1 25 mikel262
--------------------------------------------------------------------------------
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--                                                                            --
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--                          V H D L    F I L E                                --
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--                          COPYRIGHT (C) 2009                                --
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--                                                                            --
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--------------------------------------------------------------------------------
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--                                                                            --
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-- Title       : RLE                                                          --
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-- Design      : MDCT CORE                                                    --
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-- Author      : Michal Krepa                                                 --
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--                                                                            --
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--------------------------------------------------------------------------------
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--                                                                            --
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-- File        : RLE.VHD                                                      --
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-- Created     : Wed Mar 04 2009                                              --
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--                                                                            --
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--------------------------------------------------------------------------------
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--                                                                            --
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--  Description : Run Length Encoder                                          --
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--                Baseline Entropy Coding                                     --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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25
library IEEE;
26
  use IEEE.STD_LOGIC_1164.All;
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  use IEEE.NUMERIC_STD.all;
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29
library work;
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  use work.JPEG_PKG.all;
31
 
32
entity rle is
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  generic
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    (
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      RAMADDR_W     : INTEGER := 6;
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      RAMDATA_W     : INTEGER := 12
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    );
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  port
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    (
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      rst        : in  STD_LOGIC;
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      clk        : in  STD_LOGIC;
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      di         : in  STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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      start_pb   : in  std_logic;
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      sof        : in  std_logic;
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      rle_sm_settings : in T_SM_SETTINGS;
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47
      runlength  : out STD_LOGIC_VECTOR(3 downto 0);
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      size       : out STD_LOGIC_VECTOR(3 downto 0);
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      amplitude  : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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      dovalid    : out STD_LOGIC;
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      rd_addr    : out STD_LOGIC_VECTOR(5 downto 0)
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    );
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end rle;
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55
architecture rtl of rle is
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57
 
58
 
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  constant SIZE_REG_C      : INTEGER := 4;
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  constant ZEROS_32_C      : UNSIGNED(31 downto 0) := (others => '0');
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62
  signal prev_dc_reg_0   : SIGNED(RAMDATA_W-1 downto 0);
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  signal prev_dc_reg_1   : SIGNED(RAMDATA_W-1 downto 0);
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  signal prev_dc_reg_2   : SIGNED(RAMDATA_W-1 downto 0);
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  signal acc_reg         : SIGNED(RAMDATA_W downto 0);
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  signal size_reg        : UNSIGNED(SIZE_REG_C-1 downto 0);
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  signal ampli_vli_reg   : SIGNED(RAMDATA_W downto 0);
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  signal runlength_reg   : UNSIGNED(3 downto 0);
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  signal dovalid_reg     : STD_LOGIC;
70 36 mikel262
  signal zero_cnt        : unsigned(5 downto 0);
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  signal wr_cnt_d1       : unsigned(5 downto 0);
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  signal wr_cnt          : unsigned(5 downto 0);
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  signal rd_cnt         : unsigned(5 downto 0);
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  signal rd_en          : std_logic;
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77
  signal divalid        : STD_LOGIC;
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  signal divalid_en     : std_logic;
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  signal zrl_proc       : std_logic;
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  signal zrl_di         : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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begin
82
 
83
  size      <= STD_LOGIC_VECTOR(size_reg);
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  amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
85
 
86 36 mikel262
  rd_addr <= STD_LOGIC_VECTOR(rd_cnt);
87
 
88
  -------------------------------------------
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  -- MAIN PROCESSING
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  -------------------------------------------
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  process(clk,rst)
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  begin
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    if rst = '1' then
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      wr_cnt_d1       <= (others => '0');
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      prev_dc_reg_0   <= (others => '0');
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      prev_dc_reg_1   <= (others => '0');
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      prev_dc_reg_2   <= (others => '0');
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      dovalid_reg     <= '0';
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      acc_reg         <= (others => '0');
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      runlength_reg   <= (others => '0');
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      runlength       <= (others => '0');
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      dovalid         <= '0';
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      zero_cnt        <= (others => '0');
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      zrl_proc        <= '0';
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      rd_en           <= '0';
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      rd_cnt          <= (others => '0');
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      divalid_en      <= '0';
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    elsif clk = '1' and clk'event then
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      dovalid_reg     <= '0';
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      runlength_reg   <= (others => '0');
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      wr_cnt_d1       <= wr_cnt;
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      runlength       <= std_logic_vector(runlength_reg);
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      dovalid         <= dovalid_reg;
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      divalid         <= rd_en;
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116
      if start_pb = '1' then
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        rd_cnt     <= (others => '0');
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        rd_en      <= '1';
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        divalid_en <= '1';
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      end if;
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122 41 mikel262
      if divalid = '1' and wr_cnt = 63 then
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        divalid_en <= '0';
124
      end if;
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      -- input read enable
127
      if rd_en = '1' then
128
        if rd_cnt = 64-1 then
129
          rd_cnt <= (others => '0');
130
          rd_en  <= '0';
131
        else
132
          rd_cnt <= rd_cnt + 1;
133
        end if;
134
      end if;
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136
      -- input data valid
137 40 mikel262
      if divalid = '1' then
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        wr_cnt <= wr_cnt + 1;
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140
        -- first DCT coefficient received, DC data
141
        if wr_cnt = 0 then
142
          -- differental coding of DC data per component
143
          case rle_sm_settings.cmp_idx is
144
            when "00" =>
145
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
146
              prev_dc_reg_0 <= SIGNED(di);
147
            when "01" =>
148
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
149
              prev_dc_reg_1 <= SIGNED(di);
150
            when "10" =>
151
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
152
              prev_dc_reg_2 <= SIGNED(di);
153
            when others =>
154
              null;
155
          end case;
156
          runlength_reg    <= (others => '0');
157
          dovalid_reg      <= '1';
158
        -- AC coefficient
159
        else
160
          -- zero AC
161
          if signed(di) = 0 then
162
            -- EOB
163
            if wr_cnt = 63 then
164
              acc_reg          <= (others => '0');
165
              runlength_reg    <= (others => '0');
166
              dovalid_reg      <= '1';
167
            -- no EOB
168
            else
169
              zero_cnt <= zero_cnt + 1;
170
            end if;
171
          -- non-zero AC
172 25 mikel262
          else
173 36 mikel262
            -- normal RLE case
174
            if zero_cnt <= 15 then
175 25 mikel262
              acc_reg        <= RESIZE(SIGNED(di),RAMDATA_W+1);
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              runlength_reg  <= zero_cnt(3 downto 0);
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              zero_cnt       <= (others => '0');
178
              dovalid_reg    <= '1';
179 36 mikel262
            -- zero_cnt > 15
180
            else
181
              -- generate ZRL
182
              acc_reg        <= (others => '0');
183
              runlength_reg  <= X"F";
184
              zero_cnt       <= zero_cnt - 16;
185
              dovalid_reg    <= '1';
186
              -- stall input until ZRL is handled
187
              zrl_proc       <= '1';
188
              zrl_di         <= di;
189 40 mikel262
              divalid <= '0';
190
              rd_cnt  <= rd_cnt;
191 25 mikel262
            end if;
192
          end if;
193
        end if;
194 36 mikel262
      end if;
195
 
196
      -- ZRL processing
197
      if zrl_proc = '1' then
198
        if zero_cnt <= 15 then
199
          acc_reg        <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);
200
          runlength_reg  <= zero_cnt(3 downto 0);
201 40 mikel262
          if signed(zrl_di) = 0 then
202 39 mikel262
            zero_cnt     <= to_unsigned(1,zero_cnt'length);
203
          else
204
            zero_cnt     <= (others => '0');
205
          end if;
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          dovalid_reg    <= '1';
207 41 mikel262
          divalid <= divalid_en;
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          -- continue input handling
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          zrl_proc <= '0';
210
        -- zero_cnt > 15
211
        else
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          -- generate ZRL
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          acc_reg        <= (others => '0');
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          runlength_reg  <= X"F";
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          zero_cnt       <= zero_cnt - 16;
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          dovalid_reg    <= '1';
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          divalid <= '0';
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          rd_cnt <= rd_cnt;
219 36 mikel262
        end if;
220
      end if;
221
 
222
      -- start of 8x8 block processing
223
      if start_pb = '1' then
224
        zero_cnt <= (others => '0');
225
        wr_cnt   <= (others => '0');
226
      end if;
227
 
228
      if sof = '1' then
229
        prev_dc_reg_0 <= (others => '0');
230
        prev_dc_reg_1 <= (others => '0');
231
        prev_dc_reg_2 <= (others => '0');
232
      end if;
233 25 mikel262
 
234
    end if;
235
  end process;
236
 
237
  -------------------------------------------------------------------
238
  -- Entropy Coder
239
  -------------------------------------------------------------------
240
  p_entropy_coder : process(CLK, RST)
241
  begin
242
    if RST = '1' then
243
      ampli_vli_reg <= (others => '0');
244
      size_reg      <= (others => '0');
245
    elsif CLK'event and CLK = '1' then
246
      -- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude)
247
      -- positive input
248
      if acc_reg >= 0 then
249
        ampli_vli_reg <= acc_reg;
250
      else
251
        ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1);
252
      end if;
253
 
254
      -- compute Symbol-1 Size
255
      if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then
256
        size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
257
      elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then
258
        size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
259
      elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then
260
        size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
261
      elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then
262
        size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
263
      elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then
264
        size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
265
      elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then
266
        size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
267
      elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then
268
        size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
269
      elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then
270
        size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
271
      elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then
272
        size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
273
      elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then
274
        size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
275
      elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then
276
        size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
277
      end if;
278
 
279
      -- compute Symbol-1 Size
280
      -- positive input
281
      if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then
282
        size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
283
      elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then
284
        size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
285
      elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then
286
        size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
287
      elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then
288
        size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
289
      elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then
290
        size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
291
      elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then
292
        size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
293
      elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then
294
        size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
295
      elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then
296
        size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
297
      elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then
298
        size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
299
      elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then
300
        size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
301
      elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then
302
        size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
303
      end if;
304
 
305
      -- DC coefficient amplitude=0 case OR EOB
306
      if acc_reg = 0 then
307
         size_reg <= TO_UNSIGNED(0,SIZE_REG_C);
308
      end if;
309
    end if;
310
  end process;
311
 
312
end rtl;
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--------------------------------------------------------------------------------
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