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[/] [mkjpeg/] [trunk/] [design/] [BufFifo/] [BUF_FIFO.vhd] - Blame information for rev 25

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1 25 mikel262 
-------------------------------------------------------------------------------
2 
-- File Name : BUF_FIFO.vhd
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--
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-- Project   : JPEG_ENC
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--
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-- Module    : BUF_FIFO
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--
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-- Content   : Input FIFO Buffer
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--
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-- Description :
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--
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-- Spec.     :
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--
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-- Author    : Michal Krepa
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--
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-------------------------------------------------------------------------------
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-- History :
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-- 20090311: (MK): Initial Creation.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- LIBRARY/PACKAGE ---------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- generic packages/libraries:
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-------------------------------------------------------------------------------
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.numeric_std.all;
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-------------------------------------------------------------------------------
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-- user packages/libraries:
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-------------------------------------------------------------------------------
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library work;
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  use work.JPEG_PKG.all;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ENTITY ------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity BUF_FIFO is
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  port
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  (
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        CLK                : in  std_logic;
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        RST                : in  std_logic;
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        -- HOST PROG
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        img_size_x         : in  std_logic_vector(15 downto 0);
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        img_size_y         : in  std_logic_vector(15 downto 0);
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        sof                : in  std_logic;
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        -- HOST DATA
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        iram_wren          : in  std_logic;
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        iram_wdata         : in  std_logic_vector(23 downto 0);
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        fifo_almost_full   : out std_logic;
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        -- FDCT
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        fdct_block_cnt     : in  std_logic_vector(12 downto 0);
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        fdct_fifo_rd       : in  std_logic;
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        fdct_fifo_empty    : out std_logic;
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        fdct_fifo_q        : out std_logic_vector(23 downto 0);
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        fdct_fifo_hf_full  : out std_logic
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    );
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end entity BUF_FIFO;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ARCHITECTURE ------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture RTL of BUF_FIFO is
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  constant C_NUM_SUBF     : integer := ((C_MAX_LINE_WIDTH/8));
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  type T_DATA_ARR is array (0 to C_NUM_SUBF-1) of std_logic_vector(23 downto 0);
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  type T_CNT_ARR  is array (0 to C_NUM_SUBF-1) of
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    std_logic_vector(7-C_MEMORY_OPTIMIZED downto 0);
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  signal fifo_rd          : std_logic_vector(C_NUM_SUBF-1 downto 0);
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  signal fifo_wr          : std_logic_vector(C_NUM_SUBF-1 downto 0);
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  signal fifo_data        : std_logic_vector(23 downto 0);
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  signal fifo_data_d1     : std_logic_vector(23 downto 0);
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  signal fifo_q           : T_DATA_ARR;
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  signal fifo_full        : std_logic_vector(C_NUM_SUBF-1 downto 0);
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  signal fifo_empty       : std_logic_vector(C_NUM_SUBF-1 downto 0);
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  signal fifo_half_full   : std_logic_vector(C_NUM_SUBF-1 downto 0);
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  signal fifo_count       : T_CNT_ARR;
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  signal pixel_cnt        : unsigned(15 downto 0);
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  signal wblock_cnt       : unsigned(12 downto 0);
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  signal last_idx         : unsigned(12 downto 0);
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  signal idx_reg          : unsigned(log2(C_NUM_SUBF)-1 downto 0);
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-------------------------------------------------------------------------------
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-- Architecture: begin
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-------------------------------------------------------------------------------
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begin
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  -------------------------------------------------------------------
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  -- SUB_FIFOs
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  -------------------------------------------------------------------
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  G_SUB_FIFO : for i in 0 to C_NUM_SUBF-1 generate
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    U_SUB_FIFO : entity work.FIFO
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    generic map
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    (
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          DATA_WIDTH        => 24,
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          ADDR_WIDTH        => 7-C_MEMORY_OPTIMIZED
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    )
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    port map
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    (
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          rst               => RST,
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          clk               => CLK,
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          rinc              => fifo_rd(i),
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          winc              => fifo_wr(i),
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          datai             => fifo_data,
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          datao             => fifo_q(i),
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          fullo             => fifo_full(i),
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          emptyo            => fifo_empty(i),
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          count             => fifo_count(i)
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    );
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  end generate G_SUB_FIFO;
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  -------------------------------------------------------------------
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  -- FIFO almost full
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  -------------------------------------------------------------------
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  p_fifo_almost_full : process(CLK, RST)
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  begin
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    if RST = '1' then
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      fifo_almost_full   <= '1';
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      last_idx           <= (others => '0');
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    elsif CLK'event and CLK = '1' then
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      if img_size_x = (img_size_x'range => '0') then
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        last_idx <= (others => '0');
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      else
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        last_idx <= unsigned(img_size_x(15 downto 3))-1;
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      end if;
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      if last_idx > 0 then
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        if C_MEMORY_OPTIMIZED = 0 then
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          if unsigned(fifo_count(to_integer(last_idx)-2)) > to_unsigned(128-2*8,8) then
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            fifo_almost_full <= '1';
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          else
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            fifo_almost_full <= '0';
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          end if;
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        else
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           if unsigned(fifo_count(to_integer(last_idx))) = to_unsigned(64,8) then
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            fifo_almost_full <= '1';
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          else
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            fifo_almost_full <= '0';
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          end if;
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        end if;
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      end if;
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    end if;
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  end process;
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  -------------------------------------------------------------------
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  -- pixel_cnt
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  -------------------------------------------------------------------
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  p_pixel_cnt : process(CLK, RST)
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  begin
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    if RST = '1' then
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      pixel_cnt   <= (others => '0');
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    elsif CLK'event and CLK = '1' then
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      if iram_wren = '1' then
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        if pixel_cnt = unsigned(img_size_x)-1 then
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          pixel_cnt <= (others => '0');
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        else
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          pixel_cnt <= pixel_cnt + 1;
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        end if;
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      end if;
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      if sof = '1' then
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        pixel_cnt <= (others => '0');
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      end if;
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    end if;
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  end process;
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  wblock_cnt <= pixel_cnt(pixel_cnt'high downto 3);
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  -------------------------------------------------------------------
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  -- FIFO half full
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  -------------------------------------------------------------------
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  p_half_full : process(CLK, RST)
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  begin
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    if RST = '1' then
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      for i in 0 to C_NUM_SUBF-1 loop
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        fifo_half_full(i) <= '0';
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      end loop;
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    elsif CLK'event and CLK = '1' then
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      for i in 0 to C_NUM_SUBF-1 loop
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        if unsigned(fifo_count(i)) >= 64 then
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          fifo_half_full(i) <= '1';
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        else
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          fifo_half_full(i) <= '0';
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        end if;
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      end loop;
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    end if;
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  end process;
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  -------------------------------------------------------------------
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  -- Mux1
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  -------------------------------------------------------------------
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  p_mux1 : process(CLK, RST)
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  begin
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    if RST = '1' then
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      fifo_data <= (others => '0');
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      for i in 0 to C_NUM_SUBF-1 loop
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        fifo_wr(i) <= '0';
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      end loop;
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    elsif CLK'event and CLK = '1' then
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      for i in 0 to C_NUM_SUBF-1 loop
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        if wblock_cnt(log2(C_NUM_SUBF)-1 downto 0) = i then
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          fifo_wr(i) <= iram_wren;
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        else
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          fifo_wr(i) <= '0';
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        end if;
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      end loop;
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      fifo_data <= iram_wdata;
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    end if;
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  end process;
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  -------------------------------------------------------------------
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  -- Mux2
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  -------------------------------------------------------------------
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  p_mux2 : process(CLK, RST)
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  begin
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    if RST = '1' then
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      for i in 0 to C_NUM_SUBF-1 loop
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        fifo_rd(i)    <= '0';
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      end loop;
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      fdct_fifo_empty <= '0';
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      fdct_fifo_q     <= (others => '0');
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      fdct_fifo_hf_full    <= '0';
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      idx_reg              <= (others => '0');
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    elsif CLK'event and CLK = '1' then
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      idx_reg <= unsigned(fdct_block_cnt(log2(C_NUM_SUBF)-1 downto 0));
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      for i in 0 to C_NUM_SUBF-1 loop
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        if idx_reg = i then
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          fifo_rd(i)      <= fdct_fifo_rd;
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        else
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          fifo_rd(i) <= '0';
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        end if;
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      end loop;
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      fdct_fifo_empty   <= fifo_empty(to_integer(idx_reg));
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      fdct_fifo_q       <= fifo_q(to_integer(idx_reg));
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      fdct_fifo_hf_full <= fifo_half_full(to_integer(idx_reg));
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    end if;
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  end process;
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end architecture RTL;
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-------------------------------------------------------------------------------
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-- Architecture: end
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-------------------------------------------------------------------------------

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