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[/] [mkjpeg/] [trunk/] [design/] [BufFifo/] [BUF_FIFO.vhd] - Blame information for rev 40

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-------------------------------------------------------------------------------
2
-- File Name : BUF_FIFO.vhd
3
--
4
-- Project   : JPEG_ENC
5
--
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-- Module    : BUF_FIFO
7
--
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-- Content   : Input FIFO Buffer
9
--
10
-- Description : 
11
--
12
-- Spec.     : 
13
--
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-- Author    : Michal Krepa
15
--
16
-------------------------------------------------------------------------------
17
-- History :
18
-- 20090311: (MK): Initial Creation.
19
-------------------------------------------------------------------------------
20
 
21
-------------------------------------------------------------------------------
22
-------------------------------------------------------------------------------
23
----------------------------------- LIBRARY/PACKAGE ---------------------------
24
-------------------------------------------------------------------------------
25
-------------------------------------------------------------------------------
26
 
27
-------------------------------------------------------------------------------
28
-- generic packages/libraries:
29
-------------------------------------------------------------------------------
30
library ieee;
31
  use ieee.std_logic_1164.all;
32
  use ieee.numeric_std.all;
33
 
34
-------------------------------------------------------------------------------
35
-- user packages/libraries:
36
-------------------------------------------------------------------------------
37
library work;
38
  use work.JPEG_PKG.all;
39
-------------------------------------------------------------------------------
40
-------------------------------------------------------------------------------
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----------------------------------- ENTITY ------------------------------------
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-------------------------------------------------------------------------------
43
-------------------------------------------------------------------------------
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entity BUF_FIFO is
45
  port
46
  (
47
        CLK                : in  std_logic;
48
        RST                : in  std_logic;
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        -- HOST PROG
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        img_size_x         : in  std_logic_vector(15 downto 0);
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        img_size_y         : in  std_logic_vector(15 downto 0);
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        sof                : in  std_logic;
53
 
54
        -- HOST DATA
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        iram_wren          : in  std_logic;
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        iram_wdata         : in  std_logic_vector(23 downto 0);
57
        fifo_almost_full   : out std_logic;
58
 
59
        -- FDCT
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        fdct_block_cnt     : in  std_logic_vector(12 downto 0);
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        fdct_fifo_rd       : in  std_logic;
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        fdct_fifo_empty    : out std_logic;
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        fdct_fifo_q        : out std_logic_vector(23 downto 0);
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        fdct_fifo_hf_full  : out std_logic
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    );
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end entity BUF_FIFO;
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68
-------------------------------------------------------------------------------
69
-------------------------------------------------------------------------------
70
----------------------------------- ARCHITECTURE ------------------------------
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-------------------------------------------------------------------------------
72
-------------------------------------------------------------------------------
73
architecture RTL of BUF_FIFO is
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  constant C_NUM_SUBF      : integer := C_MAX_LINE_WIDTH/8;
76
  constant C_PIXEL_BITS    : integer := 24;
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  constant C_SUBF_ADDRW    : integer := 7-C_MEMORY_OPTIMIZED;
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  --constant C_LOG2_NUM_SUBF : integer := integer(log2(real(C_NUM_SUBF))); 
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80
  type T_DATA_ARR is array (0 to C_NUM_SUBF-1) of std_logic_vector(23 downto 0);
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  type T_CNT_ARR  is array (0 to C_NUM_SUBF-1) of
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    std_logic_vector(C_SUBF_ADDRW downto 0);
83
 
84
  type T_FIFO_RAMADDR     is array (0 to C_NUM_SUBF-1) of
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                            STD_LOGIC_VECTOR(C_SUBF_ADDRW-1 downto 0);
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87
  signal fifo_rd          : std_logic_vector(C_NUM_SUBF-1 downto 0);
88
  signal fifo_wr          : std_logic_vector(C_NUM_SUBF-1 downto 0);
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  signal fifo_data        : std_logic_vector(23 downto 0);
90
  signal fifo_data_d1     : std_logic_vector(23 downto 0);
91
  signal fifo_full        : std_logic_vector(C_NUM_SUBF-1 downto 0);
92
  signal fifo_empty       : std_logic_vector(C_NUM_SUBF-1 downto 0);
93
  signal fifo_half_full   : std_logic_vector(C_NUM_SUBF-1 downto 0);
94
  signal fifo_count       : T_CNT_ARR;
95
 
96
  signal pixel_cnt        : unsigned(15 downto 0);
97
  signal wblock_cnt       : unsigned(12 downto 0);
98
  signal last_idx         : unsigned(12 downto 0);
99
  signal idx_reg          : unsigned(log2(C_NUM_SUBF)-1 downto 0);
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  signal wr_idx_reg       : unsigned(log2(C_NUM_SUBF)-1 downto 0);
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  signal ramq             : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
103
  signal ramd             : STD_LOGIC_VECTOR (C_PIXEL_BITS-1 downto 0);
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  signal ramwaddr         : STD_LOGIC_VECTOR
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                            (log2(C_NUM_SUBF)+C_SUBF_ADDRW-1 downto 0);
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  signal ramwaddr_offset  : unsigned(C_SUBF_ADDRW-1 downto 0);
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  signal ramwaddr_base    : unsigned(log2(C_NUM_SUBF)+C_SUBF_ADDRW downto 0);
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  signal ramenw           : STD_LOGIC;
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  signal ramenw_m1        : STD_LOGIC;
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  signal ramenw_m2        : STD_LOGIC;
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  signal ramraddr         : STD_LOGIC_VECTOR
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                            (log2(C_NUM_SUBF)+C_SUBF_ADDRW-1 downto 0);
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  signal ramraddr_base    : unsigned(log2(C_NUM_SUBF)+C_SUBF_ADDRW downto 0);
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  signal ramraddr_offset  : unsigned(C_SUBF_ADDRW-1 downto 0);
115
  signal ramenr           : STD_LOGIC;
116
 
117
  signal fifo_ramwaddr    : T_FIFO_RAMADDR;
118
  signal fifo_ramenw      : STD_LOGIC_VECTOR(C_NUM_SUBF-1 downto 0);
119
  signal fifo_ramraddr    : T_FIFO_RAMADDR;
120
  signal fifo_ramenr      : STD_LOGIC_VECTOR(C_NUM_SUBF-1 downto 0);
121
 
122
  signal offset_ramwaddr  : STD_LOGIC_VECTOR(C_SUBF_ADDRW-1 downto 0);
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-------------------------------------------------------------------------------
124
-- Architecture: begin
125
-------------------------------------------------------------------------------
126
begin
127
 
128
  -------------------------------------------------------------------
129
  -- SUB_FIFOs
130
  -------------------------------------------------------------------
131
  G_SUB_FIFO : for i in 0 to C_NUM_SUBF-1 generate
132
 
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    U_SUB_FIFO : entity work.SUB_FIFO
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    generic map
135
    (
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          DATA_WIDTH        => C_PIXEL_BITS,
137
          ADDR_WIDTH        => C_SUBF_ADDRW
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    )
139
    port map
140
    (
141
          rst               => RST,
142
          clk               => CLK,
143
          rinc              => fifo_rd(i),
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          winc              => fifo_wr(i),
145
 
146
          fullo             => fifo_full(i),
147
          emptyo            => fifo_empty(i),
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          count             => fifo_count(i),
149
 
150
          ramwaddr          => fifo_ramwaddr(i),
151
          ramenw            => fifo_ramenw(i),
152
          ramraddr          => fifo_ramraddr(i),
153
          ramenr            => fifo_ramenr(i)
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    );
155
  end generate G_SUB_FIFO;
156
 
157
  -------------------------------------------------------------------
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  -- RAM for SUB_FIFOs
159
  -------------------------------------------------------------------
160
  U_SUB_RAMZ : entity work.SUB_RAMZ
161
  generic map
162
  (
163
           RAMADDR_W => log2(C_NUM_SUBF)+C_SUBF_ADDRW,
164
           RAMDATA_W => C_PIXEL_BITS
165
  )
166
  port map
167
  (
168
        d            => ramd,
169
        waddr        => ramwaddr,
170
        raddr        => ramraddr,
171
        we           => ramenw,
172
        clk          => clk,
173
 
174
        q            => ramq
175
  );
176
 
177
  -------------------------------------------------------------------
178 25 mikel262
  -- FIFO almost full
179
  -------------------------------------------------------------------
180
  p_fifo_almost_full : process(CLK, RST)
181
  begin
182
    if RST = '1' then
183
      fifo_almost_full   <= '1';
184
      last_idx           <= (others => '0');
185
    elsif CLK'event and CLK = '1' then
186
      if img_size_x = (img_size_x'range => '0') then
187
        last_idx <= (others => '0');
188
      else
189
        last_idx <= unsigned(img_size_x(15 downto 3))-1;
190
      end if;
191
 
192 40 mikel262
      if C_MEMORY_OPTIMIZED = 0 then
193
        if unsigned(fifo_count(to_integer(wblock_cnt))) > to_unsigned(128-2*8,8) then
194
          fifo_almost_full <= '1';
195
        else
196
          fifo_almost_full <= '0';
197
        end if;
198
      else
199
        if unsigned(fifo_count(to_integer(wblock_cnt))) >= to_unsigned(62,8) then
200
          fifo_almost_full <= '1';
201
        -- due to FIFO full latency next subFIFO is in danger of being
202
        -- overwritten thus its fifo full must be checked ahead
203
        else
204
          -- next=0 when current is last
205
          if wblock_cnt = last_idx then
206
            -- latency from FIFO full till it is recognized by Host is 2T (64-2)=62
207
            if unsigned(fifo_count(0)) >= to_unsigned(62,8) then
208
              fifo_almost_full <= '1';
209
            else
210
              fifo_almost_full <= '0';
211
            end if;
212
          -- next is just current+1
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          else
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            -- latency from FIFO full till it is recognized by Host is 2T (64-2)=62
215
            if unsigned(fifo_count(to_integer(wblock_cnt)+1)) >= to_unsigned(62,8) then
216
              fifo_almost_full <= '1';
217
            else
218
              fifo_almost_full <= '0';
219
            end if;
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          end if;
221
        end if;
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223 25 mikel262
      end if;
224
    end if;
225
  end process;
226
 
227
  -------------------------------------------------------------------
228
  -- pixel_cnt
229
  -------------------------------------------------------------------
230
  p_pixel_cnt : process(CLK, RST)
231
  begin
232
    if RST = '1' then
233
      pixel_cnt   <= (others => '0');
234
    elsif CLK'event and CLK = '1' then
235
      if iram_wren = '1' then
236
        if pixel_cnt = unsigned(img_size_x)-1 then
237
          pixel_cnt <= (others => '0');
238
        else
239
          pixel_cnt <= pixel_cnt + 1;
240
        end if;
241
      end if;
242
 
243
      if sof = '1' then
244
        pixel_cnt <= (others => '0');
245
      end if;
246
    end if;
247
  end process;
248
 
249
  wblock_cnt <= pixel_cnt(pixel_cnt'high downto 3);
250
 
251
  -------------------------------------------------------------------
252
  -- FIFO half full
253
  -------------------------------------------------------------------
254
  p_half_full : process(CLK, RST)
255
  begin
256
    if RST = '1' then
257
      for i in 0 to C_NUM_SUBF-1 loop
258
        fifo_half_full(i) <= '0';
259
      end loop;
260
    elsif CLK'event and CLK = '1' then
261
      for i in 0 to C_NUM_SUBF-1 loop
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        if C_MEMORY_OPTIMIZED = 0 then
263
          if unsigned(fifo_count(i)) >= 64 then
264
            fifo_half_full(i) <= '1';
265
          else
266
            fifo_half_full(i) <= '0';
267
          end if;
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        else
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          fifo_half_full(i) <= fifo_full(i);
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        end if;
271
      end loop;
272
    end if;
273
  end process;
274
 
275
  -------------------------------------------------------------------
276
  -- Mux1
277
  -------------------------------------------------------------------
278
  p_mux1 : process(CLK, RST)
279
  begin
280
    if RST = '1' then
281
      for i in 0 to C_NUM_SUBF-1 loop
282
        fifo_wr(i) <= '0';
283
      end loop;
284
    elsif CLK'event and CLK = '1' then
285
      for i in 0 to C_NUM_SUBF-1 loop
286
        if wblock_cnt(log2(C_NUM_SUBF)-1 downto 0) = i then
287
          fifo_wr(i) <= iram_wren;
288
        else
289
          fifo_wr(i) <= '0';
290
        end if;
291
      end loop;
292
    end if;
293
  end process;
294
 
295
  -------------------------------------------------------------------
296
  -- Mux2
297
  -------------------------------------------------------------------
298
  p_mux2 : process(CLK, RST)
299
  begin
300
    if RST = '1' then
301
      for i in 0 to C_NUM_SUBF-1 loop
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        fifo_rd(i)      <= '0';
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      end loop;
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      fdct_fifo_empty   <= '0';
305
      fdct_fifo_hf_full <= '0';
306
      idx_reg           <= (others => '0');
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    elsif CLK'event and CLK = '1' then
308
      idx_reg <= unsigned(fdct_block_cnt(log2(C_NUM_SUBF)-1 downto 0));
309
 
310
      for i in 0 to C_NUM_SUBF-1 loop
311
        if idx_reg = i then
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          fifo_rd(i) <= fdct_fifo_rd;
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        else
314
          fifo_rd(i) <= '0';
315
        end if;
316
      end loop;
317
 
318
      fdct_fifo_empty   <= fifo_empty(to_integer(idx_reg));
319
      fdct_fifo_hf_full <= fifo_half_full(to_integer(idx_reg));
320
    end if;
321
  end process;
322
 
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  fdct_fifo_q  <= ramq;
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325 28 mikel262
  -------------------------------------------------------------------
326
  -- Mux3
327
  -------------------------------------------------------------------
328
  p_mux3 : process(CLK, RST)
329
  begin
330
    if RST = '1' then
331
      ramwaddr         <= (others => '0');
332
      ramwaddr_offset  <= (others => '0');
333
      ramwaddr_base    <= (others => '0');
334
      ramenw           <= '0';
335
      ramenw_m1        <= '0';
336
      wr_idx_reg       <= (others => '0');
337
      ramd             <= (others => '0');
338
      fifo_data        <= (others => '0');
339
      fifo_data_d1     <= (others => '0');
340
    elsif CLK'event and CLK = '1' then
341
      wr_idx_reg    <= unsigned(wblock_cnt(log2(C_NUM_SUBF)-1 downto 0));
342
 
343
      fifo_data    <= iram_wdata;
344
      fifo_data_d1 <= fifo_data;
345
      ramd         <= fifo_data_d1;
346
 
347
      ramenw_m1 <= fifo_ramenw(to_integer(wr_idx_reg));
348
      ramenw    <= ramenw_m1;
349
 
350
      ramwaddr_offset <= unsigned(fifo_ramwaddr(to_integer(wr_idx_reg)));
351
      ramwaddr_base   <= to_unsigned(2**C_SUBF_ADDRW, C_SUBF_ADDRW+1) *
352
                         wr_idx_reg;
353
      ramwaddr  <= std_logic_vector(ramwaddr_base(ramwaddr'range) +
354
                  resize(ramwaddr_offset, ramwaddr'length));
355
    end if;
356
  end process;
357
 
358
  -------------------------------------------------------------------
359
  -- Mux4
360
  -------------------------------------------------------------------
361
  p_mux4 : process(CLK, RST)
362
  begin
363
    if RST = '1' then
364
      ramraddr          <= (others => '0');
365
      ramraddr_base     <= (others => '0');
366
      ramraddr_offset   <= (others => '0');
367
    elsif CLK'event and CLK = '1' then
368
      ramraddr_offset <= unsigned(fifo_ramraddr(to_integer(idx_reg)));
369
      ramraddr_base   <= to_unsigned(2**C_SUBF_ADDRW, C_SUBF_ADDRW+1) *
370
                         idx_reg;
371
      ramraddr <= std_logic_vector(ramraddr_base(ramraddr'range) +
372
                  resize(unsigned(ramraddr_offset), ramraddr'length));
373
    end if;
374
  end process;
375 25 mikel262
 
376
end architecture RTL;
377
-------------------------------------------------------------------------------
378
-- Architecture: end
379
-------------------------------------------------------------------------------

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