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[/] [mkjpeg/] [trunk/] [design/] [BufFifo/] [BUF_FIFO.vhd] - Blame information for rev 58

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-------------------------------------------------------------------------------
2
-- File Name : BUF_FIFO.vhd
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--
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-- Project   : JPEG_ENC
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--
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-- Module    : BUF_FIFO
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--
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-- Content   : Input FIFO Buffer
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--
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-- Description : 
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--
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-- Spec.     : 
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--
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-- Author    : Michal Krepa
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--
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-------------------------------------------------------------------------------
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-- History :
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-- 20090311: (MK): Initial Creation.
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- LIBRARY/PACKAGE ---------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- generic packages/libraries:
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-------------------------------------------------------------------------------
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.numeric_std.all;
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-------------------------------------------------------------------------------
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-- user packages/libraries:
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-------------------------------------------------------------------------------
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library work;
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  use work.JPEG_PKG.all;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ENTITY ------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity BUF_FIFO is
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  port
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  (
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        CLK                : in  std_logic;
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        RST                : in  std_logic;
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        -- HOST PROG
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        img_size_x         : in  std_logic_vector(15 downto 0);
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        img_size_y         : in  std_logic_vector(15 downto 0);
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        sof                : in  std_logic;
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        -- HOST DATA
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        iram_wren          : in  std_logic;
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        iram_wdata         : in  std_logic_vector(C_PIXEL_BITS-1 downto 0);
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        fifo_almost_full   : out std_logic;
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        -- FDCT
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        fdct_fifo_rd       : in  std_logic;
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        fdct_fifo_q        : out std_logic_vector(23 downto 0);
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        fdct_fifo_hf_full  : out std_logic
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    );
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end entity BUF_FIFO;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ARCHITECTURE ------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture RTL of BUF_FIFO is
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  constant C_NUM_LINES    : integer := 8 + C_EXTRA_LINES;
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  signal pixel_cnt        : unsigned(15 downto 0);
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  signal line_cnt         : unsigned(15 downto 0);
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  signal ramq             : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
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  signal ramd             : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
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  signal ramwaddr         : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
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  signal ramenw           : STD_LOGIC;
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  signal ramraddr         : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
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  signal pix_inblk_cnt    : unsigned(2 downto 0);
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  signal pix_inblk_cnt_d1 : unsigned(2 downto 0);
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  signal line_inblk_cnt   : unsigned(2 downto 0);
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  signal read_block_cnt   : unsigned(12 downto 0);
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  signal read_block_cnt_d1 : unsigned(12 downto 0);
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  signal write_block_cnt  : unsigned(12 downto 0);
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  signal ramraddr_int     : unsigned(16+log2(C_NUM_LINES)-1 downto 0);
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  signal raddr_base_line  : unsigned(16+log2(C_NUM_LINES)-1 downto 0);
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  signal raddr_tmp        : unsigned(15 downto 0);
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  signal ramwaddr_d1      : unsigned(ramwaddr'range);
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  signal line_lock        : unsigned(log2(C_NUM_LINES)-1 downto 0);
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  signal memwr_line_cnt   : unsigned(log2(C_NUM_LINES)-1 downto 0);
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  signal memrd_offs_cnt   : unsigned(log2(C_NUM_LINES)-1+1 downto 0);
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  signal memrd_line       : unsigned(log2(C_NUM_LINES)-1 downto 0);
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  signal wr_line_idx      : unsigned(15 downto 0);
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  signal rd_line_idx      : unsigned(15 downto 0);
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108
  signal image_write_end  : std_logic;
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110
 
111
 
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-------------------------------------------------------------------------------
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-- Architecture: begin
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-------------------------------------------------------------------------------
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begin
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  -------------------------------------------------------------------
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  -- RAM for SUB_FIFOs
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  -------------------------------------------------------------------
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  U_SUB_RAMZ : entity work.SUB_RAMZ
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  generic map
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  (
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           RAMADDR_W => log2( C_MAX_LINE_WIDTH*C_NUM_LINES ),
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           RAMDATA_W => C_PIXEL_BITS
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  )
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  port map
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  (
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        d            => ramd,
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        waddr        => std_logic_vector(ramwaddr_d1),
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        raddr        => std_logic_vector(ramraddr),
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        we           => ramenw,
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        clk          => clk,
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133
        q            => ramq
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  );
135
 
136
  -------------------------------------------------------------------
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  -- register RAM data input
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  -------------------------------------------------------------------
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  p_mux1 : process(CLK, RST)
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  begin
141
    if RST = '1' then
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      ramenw           <= '0';
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      ramd             <= (others => '0');
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    elsif CLK'event and CLK = '1' then
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      ramd      <= iram_wdata;
146
      ramenw    <= iram_wren;
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    end if;
148
  end process;
149
 
150
  -------------------------------------------------------------------
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  -- resolve RAM write address
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  -------------------------------------------------------------------
153
  p_pixel_cnt : process(CLK, RST)
154
  begin
155
    if RST = '1' then
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      pixel_cnt      <= (others => '0');
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      memwr_line_cnt <= (others => '0');
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      wr_line_idx    <= (others => '0');
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      ramwaddr       <= (others => '0');
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      ramwaddr_d1    <= (others => '0');
161
      image_write_end <= '0';
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    elsif CLK'event and CLK = '1' then
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      ramwaddr_d1 <= ramwaddr;
164
 
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      if iram_wren = '1' then
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        -- end of line
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        if pixel_cnt = unsigned(img_size_x)-1 then
168
          pixel_cnt <= (others => '0');
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          -- absolute write line index
170
          wr_line_idx <= wr_line_idx + 1;
171
 
172
          if wr_line_idx = unsigned(img_size_y)-1 then
173
            image_write_end <= '1';
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          end if;
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176
          -- memory line index
177
          if memwr_line_cnt = C_NUM_LINES-1 then
178
            memwr_line_cnt <= (others => '0');
179
            ramwaddr       <= (others => '0');
180
          else
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            memwr_line_cnt <= memwr_line_cnt + 1;
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            ramwaddr       <= ramwaddr + 1;
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          end if;
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        else
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          pixel_cnt <= pixel_cnt + 1;
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          ramwaddr  <= ramwaddr + 1;
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        end if;
188
      end if;
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190
      if sof = '1' then
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        pixel_cnt      <= (others => '0');
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        ramwaddr       <= (others => '0');
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        memwr_line_cnt <= (others => '0');
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        wr_line_idx    <= (others => '0');
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        image_write_end <= '0';
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      end if;
197
    end if;
198
  end process;
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  -------------------------------------------------------------------
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  -- FIFO half full / almost full flag generation
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  -------------------------------------------------------------------
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  p_mux3 : process(CLK, RST)
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  begin
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    if RST = '1' then
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      fdct_fifo_hf_full   <= '0';
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      fifo_almost_full    <= '0';
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    elsif CLK'event and CLK = '1' then
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      if rd_line_idx + 8 <= wr_line_idx then
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        fdct_fifo_hf_full <= '1';
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      else
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        fdct_fifo_hf_full <= '0';
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      end if;
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      fifo_almost_full <= '0';
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      if C_EXTRA_LINES = 0 then
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        if wr_line_idx = rd_line_idx + C_NUM_LINES-1 then
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          if pixel_cnt >= unsigned(img_size_x)-1-1 then
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            fifo_almost_full <= '1';
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          end if;
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        elsif wr_line_idx > rd_line_idx + C_NUM_LINES-1 then
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          fifo_almost_full <= '1';
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        end if;
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      else
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        if wr_line_idx > rd_line_idx + C_NUM_LINES-1 then
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          fifo_almost_full <= '1';
228
        end if;
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      end if;
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    end if;
232
  end process;
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  -------------------------------------------------------------------
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  -- read side
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  -------------------------------------------------------------------
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  p_mux5 : process(CLK, RST)
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  begin
239
    if RST = '1' then
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      memrd_offs_cnt <= (others => '0');
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      read_block_cnt <= (others => '0');
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      pix_inblk_cnt  <= (others => '0');
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      line_inblk_cnt <= (others => '0');
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      rd_line_idx    <= (others => '0');
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      pix_inblk_cnt_d1  <= (others => '0');
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      read_block_cnt_d1 <= (others => '0');
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    elsif CLK'event and CLK = '1' then
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      pix_inblk_cnt_d1 <= pix_inblk_cnt;
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      read_block_cnt_d1 <= read_block_cnt;
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251
      -- BUF FIFO read
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      if fdct_fifo_rd = '1' then
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        -- last pixel in block
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        if pix_inblk_cnt = 8-1 then
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          pix_inblk_cnt <= (others => '0');
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          -- last line in 8
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          if line_inblk_cnt = 8-1 then
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            line_inblk_cnt <= (others => '0');
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            -- last block in last line
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            if read_block_cnt = unsigned(img_size_x(15 downto 3))-1 then
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              read_block_cnt <= (others => '0');
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              rd_line_idx <= rd_line_idx + 8;
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              if memrd_offs_cnt + 8 > C_NUM_LINES-1 then
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                memrd_offs_cnt <= memrd_offs_cnt + 8 - C_NUM_LINES;
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              else
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                memrd_offs_cnt <= memrd_offs_cnt + 8;
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              end if;
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            else
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              read_block_cnt <= read_block_cnt + 1;
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            end if;
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          else
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            line_inblk_cnt <= line_inblk_cnt + 1;
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          end if;
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        else
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          pix_inblk_cnt <= pix_inblk_cnt + 1;
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        end if;
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      end if;
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      if memrd_offs_cnt + (line_inblk_cnt) > C_NUM_LINES-1 then
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        memrd_line <= memrd_offs_cnt(memrd_line'range) + (line_inblk_cnt) - (C_NUM_LINES);
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      else
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        memrd_line <= memrd_offs_cnt(memrd_line'range) + (line_inblk_cnt);
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      end if;
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      if sof = '1' then
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        memrd_line     <= (others => '0');
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        memrd_offs_cnt <= (others => '0');
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        read_block_cnt <= (others => '0');
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        pix_inblk_cnt  <= (others => '0');
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        line_inblk_cnt <= (others => '0');
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        rd_line_idx    <= (others => '0');
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      end if;
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297 25 mikel262
    end if;
298
  end process;
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  -- generate RAM data output based on 16 or 24 bit mode selection
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  fdct_fifo_q <= (ramq(15 downto 11) & "000" &
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                 ramq(10 downto 5) & "00" &
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                 ramq(4 downto 0) & "000") when C_PIXEL_BITS = 16 else
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                 std_logic_vector(resize(unsigned(ramq), 24));
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307 52 mikel262
  ramraddr <= ramraddr_int(ramraddr'range);
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309 28 mikel262
  -------------------------------------------------------------------
310 52 mikel262
  -- resolve RAM read address
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  -------------------------------------------------------------------
312
  p_mux4 : process(CLK, RST)
313
  begin
314
    if RST = '1' then
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      ramraddr_int          <= (others => '0');
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    elsif CLK'event and CLK = '1' then
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      raddr_base_line <= (memrd_line) * unsigned(img_size_x);
318
      raddr_tmp       <= (read_block_cnt_d1 & "000") + pix_inblk_cnt_d1;
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320
      ramraddr_int <= raddr_tmp + raddr_base_line;
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    end if;
322
  end process;
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324
end architecture RTL;
325
-------------------------------------------------------------------------------
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-- Architecture: end
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-------------------------------------------------------------------------------

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