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[/] [mkjpeg/] [trunk/] [design/] [BufFifo/] [BUF_FIFO.vhd] - Blame information for rev 58

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-------------------------------------------------------------------------------
-- File Name : BUF_FIFO.vhd
--
-- Project   : JPEG_ENC
--
-- Module    : BUF_FIFO
--
-- Content   : Input FIFO Buffer
--
-- Description : 
--
-- Spec.     : 
--
-- Author    : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090311: (MK): Initial Creation.
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
 
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
  use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity BUF_FIFO is
  port
  (
        CLK                : in  std_logic;
        RST                : in  std_logic;
        -- HOST PROG
        img_size_x         : in  std_logic_vector(15 downto 0);
        img_size_y         : in  std_logic_vector(15 downto 0);
        sof                : in  std_logic;
 
        -- HOST DATA
        iram_wren          : in  std_logic;
        iram_wdata         : in  std_logic_vector(C_PIXEL_BITS-1 downto 0);
        fifo_almost_full   : out std_logic;
 
        -- FDCT
        fdct_fifo_rd       : in  std_logic;
        fdct_fifo_q        : out std_logic_vector(23 downto 0);
        fdct_fifo_hf_full  : out std_logic
    );
end entity BUF_FIFO;
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of BUF_FIFO is
 
 
  constant C_NUM_LINES    : integer := 8 + C_EXTRA_LINES;
 
  signal pixel_cnt        : unsigned(15 downto 0);
  signal line_cnt         : unsigned(15 downto 0);
 
  signal ramq             : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
  signal ramd             : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
  signal ramwaddr         : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
  signal ramenw           : STD_LOGIC;
  signal ramraddr         : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
 
  signal pix_inblk_cnt    : unsigned(2 downto 0);
  signal pix_inblk_cnt_d1 : unsigned(2 downto 0);
  signal line_inblk_cnt   : unsigned(2 downto 0);
 
  signal read_block_cnt   : unsigned(12 downto 0);
  signal read_block_cnt_d1 : unsigned(12 downto 0);
  signal write_block_cnt  : unsigned(12 downto 0);
 
  signal ramraddr_int     : unsigned(16+log2(C_NUM_LINES)-1 downto 0);
  signal raddr_base_line  : unsigned(16+log2(C_NUM_LINES)-1 downto 0);
  signal raddr_tmp        : unsigned(15 downto 0);
  signal ramwaddr_d1      : unsigned(ramwaddr'range);
 
  signal line_lock        : unsigned(log2(C_NUM_LINES)-1 downto 0);
 
  signal memwr_line_cnt   : unsigned(log2(C_NUM_LINES)-1 downto 0);
 
  signal memrd_offs_cnt   : unsigned(log2(C_NUM_LINES)-1+1 downto 0);
  signal memrd_line       : unsigned(log2(C_NUM_LINES)-1 downto 0);
 
  signal wr_line_idx      : unsigned(15 downto 0);
  signal rd_line_idx      : unsigned(15 downto 0);
 
  signal image_write_end  : std_logic;
 
 
 
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
  -------------------------------------------------------------------
  -- RAM for SUB_FIFOs
  -------------------------------------------------------------------
  U_SUB_RAMZ : entity work.SUB_RAMZ
  generic map
  (
           RAMADDR_W => log2( C_MAX_LINE_WIDTH*C_NUM_LINES ),
           RAMDATA_W => C_PIXEL_BITS
  )
  port map
  (
        d            => ramd,
        waddr        => std_logic_vector(ramwaddr_d1),
        raddr        => std_logic_vector(ramraddr),
        we           => ramenw,
        clk          => clk,
 
        q            => ramq
  );
 
  -------------------------------------------------------------------
  -- register RAM data input
  -------------------------------------------------------------------
  p_mux1 : process(CLK, RST)
  begin
    if RST = '1' then
      ramenw           <= '0';
      ramd             <= (others => '0');
    elsif CLK'event and CLK = '1' then
      ramd      <= iram_wdata;
      ramenw    <= iram_wren;
    end if;
  end process;
 
  -------------------------------------------------------------------
  -- resolve RAM write address
  -------------------------------------------------------------------
  p_pixel_cnt : process(CLK, RST)
  begin
    if RST = '1' then
      pixel_cnt      <= (others => '0');
      memwr_line_cnt <= (others => '0');
      wr_line_idx    <= (others => '0');
      ramwaddr       <= (others => '0');
      ramwaddr_d1    <= (others => '0');
      image_write_end <= '0';
    elsif CLK'event and CLK = '1' then
      ramwaddr_d1 <= ramwaddr;
 
      if iram_wren = '1' then
        -- end of line
        if pixel_cnt = unsigned(img_size_x)-1 then
          pixel_cnt <= (others => '0');
          -- absolute write line index
          wr_line_idx <= wr_line_idx + 1;
 
          if wr_line_idx = unsigned(img_size_y)-1 then
            image_write_end <= '1';
          end if;
 
          -- memory line index
          if memwr_line_cnt = C_NUM_LINES-1 then
            memwr_line_cnt <= (others => '0');
            ramwaddr       <= (others => '0');
          else
            memwr_line_cnt <= memwr_line_cnt + 1;
            ramwaddr       <= ramwaddr + 1;
          end if;
        else
          pixel_cnt <= pixel_cnt + 1;
          ramwaddr  <= ramwaddr + 1;
        end if;
      end if;
 
      if sof = '1' then
        pixel_cnt      <= (others => '0');
        ramwaddr       <= (others => '0');
        memwr_line_cnt <= (others => '0');
        wr_line_idx    <= (others => '0');
        image_write_end <= '0';
      end if;
    end if;
  end process;
 
  -------------------------------------------------------------------
  -- FIFO half full / almost full flag generation
  -------------------------------------------------------------------
  p_mux3 : process(CLK, RST)
  begin
    if RST = '1' then
      fdct_fifo_hf_full   <= '0';
      fifo_almost_full    <= '0';
    elsif CLK'event and CLK = '1' then
 
      if rd_line_idx + 8 <= wr_line_idx then
        fdct_fifo_hf_full <= '1';
      else
        fdct_fifo_hf_full <= '0';
      end if;
 
      fifo_almost_full <= '0';
      if C_EXTRA_LINES = 0 then
        if wr_line_idx = rd_line_idx + C_NUM_LINES-1 then
          if pixel_cnt >= unsigned(img_size_x)-1-1 then
            fifo_almost_full <= '1';
          end if;
        elsif wr_line_idx > rd_line_idx + C_NUM_LINES-1 then
          fifo_almost_full <= '1';
        end if;
      else
        if wr_line_idx > rd_line_idx + C_NUM_LINES-1 then
          fifo_almost_full <= '1';
        end if;
      end if;
 
    end if;
  end process;
 
  -------------------------------------------------------------------
  -- read side
  -------------------------------------------------------------------
  p_mux5 : process(CLK, RST)
  begin
    if RST = '1' then
      memrd_offs_cnt <= (others => '0');
      read_block_cnt <= (others => '0');
      pix_inblk_cnt  <= (others => '0');
      line_inblk_cnt <= (others => '0');
      rd_line_idx    <= (others => '0');
      pix_inblk_cnt_d1  <= (others => '0');
      read_block_cnt_d1 <= (others => '0');
    elsif CLK'event and CLK = '1' then
      pix_inblk_cnt_d1 <= pix_inblk_cnt;
      read_block_cnt_d1 <= read_block_cnt;
 
      -- BUF FIFO read
      if fdct_fifo_rd = '1' then
        -- last pixel in block
        if pix_inblk_cnt = 8-1 then
          pix_inblk_cnt <= (others => '0');
 
          -- last line in 8
          if line_inblk_cnt = 8-1 then
            line_inblk_cnt <= (others => '0');
 
            -- last block in last line
            if read_block_cnt = unsigned(img_size_x(15 downto 3))-1 then
              read_block_cnt <= (others => '0');
              rd_line_idx <= rd_line_idx + 8;
              if memrd_offs_cnt + 8 > C_NUM_LINES-1 then
                memrd_offs_cnt <= memrd_offs_cnt + 8 - C_NUM_LINES;
              else
                memrd_offs_cnt <= memrd_offs_cnt + 8;
              end if;
            else
              read_block_cnt <= read_block_cnt + 1;
            end if;
          else
            line_inblk_cnt <= line_inblk_cnt + 1;
          end if;
 
        else
          pix_inblk_cnt <= pix_inblk_cnt + 1;
        end if;
      end if;
 
      if memrd_offs_cnt + (line_inblk_cnt) > C_NUM_LINES-1 then
        memrd_line <= memrd_offs_cnt(memrd_line'range) + (line_inblk_cnt) - (C_NUM_LINES);
      else
        memrd_line <= memrd_offs_cnt(memrd_line'range) + (line_inblk_cnt);
      end if;
 
      if sof = '1' then
        memrd_line     <= (others => '0');
        memrd_offs_cnt <= (others => '0');
        read_block_cnt <= (others => '0');
        pix_inblk_cnt  <= (others => '0');
        line_inblk_cnt <= (others => '0');
        rd_line_idx    <= (others => '0');
      end if;
 
    end if;
  end process;
 
  -- generate RAM data output based on 16 or 24 bit mode selection
  fdct_fifo_q <= (ramq(15 downto 11) & "000" &
                 ramq(10 downto 5) & "00" &
                 ramq(4 downto 0) & "000") when C_PIXEL_BITS = 16 else
                 std_logic_vector(resize(unsigned(ramq), 24));
 
 
  ramraddr <= ramraddr_int(ramraddr'range);
 
  -------------------------------------------------------------------
  -- resolve RAM read address
  -------------------------------------------------------------------
  p_mux4 : process(CLK, RST)
  begin
    if RST = '1' then
      ramraddr_int          <= (others => '0');
    elsif CLK'event and CLK = '1' then
      raddr_base_line <= (memrd_line) * unsigned(img_size_x);
      raddr_tmp       <= (read_block_cnt_d1 & "000") + pix_inblk_cnt_d1;
 
      ramraddr_int <= raddr_tmp + raddr_base_line;
    end if;
  end process;
 
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------

Line No.	Rev	Author	Line
1	25	mikel262	`-------------------------------------------------------------------------------`
2			`-- File Name : BUF_FIFO.vhd`
3			`--`
4			`-- Project : JPEG_ENC`
5			`--`
6			`-- Module : BUF_FIFO`
7			`--`
8			`-- Content : Input FIFO Buffer`
9			`--`
10			`-- Description :`
11			`--`
12			`-- Spec. :`
13			`--`
14			`-- Author : Michal Krepa`
15			`--`
16			`-------------------------------------------------------------------------------`
17			`-- History :`
18			`-- 20090311: (MK): Initial Creation.`
19			`-------------------------------------------------------------------------------`
20
21			`-------------------------------------------------------------------------------`
22			`-------------------------------------------------------------------------------`
23			`----------------------------------- LIBRARY/PACKAGE ---------------------------`
24			`-------------------------------------------------------------------------------`
25			`-------------------------------------------------------------------------------`
26
27			`-------------------------------------------------------------------------------`
28			`-- generic packages/libraries:`
29			`-------------------------------------------------------------------------------`
30			`library ieee;`
31			`use ieee.std_logic_1164.all;`
32			`use ieee.numeric_std.all;`
33
34			`-------------------------------------------------------------------------------`
35			`-- user packages/libraries:`
36			`-------------------------------------------------------------------------------`
37			`library work;`
38			`use work.JPEG_PKG.all;`
39			`-------------------------------------------------------------------------------`
40			`-------------------------------------------------------------------------------`
41			`----------------------------------- ENTITY ------------------------------------`
42			`-------------------------------------------------------------------------------`
43			`-------------------------------------------------------------------------------`
44			`entity BUF_FIFO is`
45			`port`
46			`(`
47			`CLK : in std_logic;`
48			`RST : in std_logic;`
49			`-- HOST PROG`
50			`img_size_x : in std_logic_vector(15 downto 0);`
51			`img_size_y : in std_logic_vector(15 downto 0);`
52			`sof : in std_logic;`
53
54			`-- HOST DATA`
55			`iram_wren : in std_logic;`
56	49	mikel262	`iram_wdata : in std_logic_vector(C_PIXEL_BITS-1 downto 0);`
57	25	mikel262	`fifo_almost_full : out std_logic;`
58
59			`-- FDCT`
60			`fdct_fifo_rd : in std_logic;`
61			`fdct_fifo_q : out std_logic_vector(23 downto 0);`
62			`fdct_fifo_hf_full : out std_logic`
63			`);`
64			`end entity BUF_FIFO;`
65
66			`-------------------------------------------------------------------------------`
67			`-------------------------------------------------------------------------------`
68			`----------------------------------- ARCHITECTURE ------------------------------`
69			`-------------------------------------------------------------------------------`
70			`-------------------------------------------------------------------------------`
71			`architecture RTL of BUF_FIFO is`
72
73	56	mikel262
74			`constant C_NUM_LINES : integer := 8 + C_EXTRA_LINES;`
75
76	52	mikel262	`signal pixel_cnt : unsigned(15 downto 0);`
77			`signal line_cnt : unsigned(15 downto 0);`
78
79			`signal ramq : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);`
80			`signal ramd : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);`
81	56	mikel262	`signal ramwaddr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);`
82	52	mikel262	`signal ramenw : STD_LOGIC;`
83	56	mikel262	`signal ramraddr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);`
84	49	mikel262
85	56	mikel262	`signal pix_inblk_cnt : unsigned(2 downto 0);`
86			`signal pix_inblk_cnt_d1 : unsigned(2 downto 0);`
87			`signal line_inblk_cnt : unsigned(2 downto 0);`
88	25	mikel262
89	52	mikel262	`signal read_block_cnt : unsigned(12 downto 0);`
90	56	mikel262	`signal read_block_cnt_d1 : unsigned(12 downto 0);`
91	52	mikel262	`signal write_block_cnt : unsigned(12 downto 0);`
92	25	mikel262
93	56	mikel262	`signal ramraddr_int : unsigned(16+log2(C_NUM_LINES)-1 downto 0);`
94			`signal raddr_base_line : unsigned(16+log2(C_NUM_LINES)-1 downto 0);`
95	52	mikel262	`signal raddr_tmp : unsigned(15 downto 0);`
96	56	mikel262	`signal ramwaddr_d1 : unsigned(ramwaddr'range);`
97	25	mikel262
98	56	mikel262	`signal line_lock : unsigned(log2(C_NUM_LINES)-1 downto 0);`
99	28	mikel262
100	56	mikel262	`signal memwr_line_cnt : unsigned(log2(C_NUM_LINES)-1 downto 0);`
101
102			`signal memrd_offs_cnt : unsigned(log2(C_NUM_LINES)-1+1 downto 0);`
103			`signal memrd_line : unsigned(log2(C_NUM_LINES)-1 downto 0);`
104
105			`signal wr_line_idx : unsigned(15 downto 0);`
106			`signal rd_line_idx : unsigned(15 downto 0);`
107
108			`signal image_write_end : std_logic;`
109
110
111
112	25	mikel262	`-------------------------------------------------------------------------------`
113			`-- Architecture: begin`
114			`-------------------------------------------------------------------------------`
115	52	mikel262	`begin`
116	25	mikel262	`-------------------------------------------------------------------`
117	28	mikel262	`-- RAM for SUB_FIFOs`
118			`-------------------------------------------------------------------`
119			`U_SUB_RAMZ : entity work.SUB_RAMZ`
120			`generic map`
121			`(`
122	56	mikel262	`RAMADDR_W => log2( C_MAX_LINE_WIDTH*C_NUM_LINES ),`
123	28	mikel262	`RAMDATA_W => C_PIXEL_BITS`
124			`)`
125			`port map`
126			`(`
127			`d => ramd,`
128	52	mikel262	`waddr => std_logic_vector(ramwaddr_d1),`
129			`raddr => std_logic_vector(ramraddr),`
130	28	mikel262	`we => ramenw,`
131			`clk => clk,`
132
133			`q => ramq`
134			`);`
135
136			`-------------------------------------------------------------------`
137	52	mikel262	`-- register RAM data input`
138	25	mikel262	`-------------------------------------------------------------------`
139	52	mikel262	`p_mux1 : process(CLK, RST)`
140	25	mikel262	`begin`
141			`if RST = '1' then`
142	52	mikel262	`ramenw <= '0';`
143			`ramd <= (others => '0');`
144	25	mikel262	`elsif CLK'event and CLK = '1' then`
145	52	mikel262	`ramd <= iram_wdata;`
146			`ramenw <= iram_wren;`
147	25	mikel262	`end if;`
148			`end process;`
149
150			`-------------------------------------------------------------------`
151	52	mikel262	`-- resolve RAM write address`
152	25	mikel262	`-------------------------------------------------------------------`
153			`p_pixel_cnt : process(CLK, RST)`
154			`begin`
155			`if RST = '1' then`
156	56	mikel262	`pixel_cnt <= (others => '0');`
157			`memwr_line_cnt <= (others => '0');`
158			`wr_line_idx <= (others => '0');`
159			`ramwaddr <= (others => '0');`
160			`ramwaddr_d1 <= (others => '0');`
161			`image_write_end <= '0';`
162	25	mikel262	`elsif CLK'event and CLK = '1' then`
163	52	mikel262	`ramwaddr_d1 <= ramwaddr;`
164
165	25	mikel262	`if iram_wren = '1' then`
166	56	mikel262	`-- end of line`
167	25	mikel262	`if pixel_cnt = unsigned(img_size_x)-1 then`
168			`pixel_cnt <= (others => '0');`
169	56	mikel262	`-- absolute write line index`
170			`wr_line_idx <= wr_line_idx + 1;`
171
172			`if wr_line_idx = unsigned(img_size_y)-1 then`
173			`image_write_end <= '1';`
174	52	mikel262	`end if;`
175	56	mikel262
176			`-- memory line index`
177			`if memwr_line_cnt = C_NUM_LINES-1 then`
178			`memwr_line_cnt <= (others => '0');`
179			`ramwaddr <= (others => '0');`
180			`else`
181			`memwr_line_cnt <= memwr_line_cnt + 1;`
182			`ramwaddr <= ramwaddr + 1;`
183			`end if;`
184	25	mikel262	`else`
185			`pixel_cnt <= pixel_cnt + 1;`
186	52	mikel262	`ramwaddr <= ramwaddr + 1;`
187	25	mikel262	`end if;`
188			`end if;`
189
190			`if sof = '1' then`
191	56	mikel262	`pixel_cnt <= (others => '0');`
192			`ramwaddr <= (others => '0');`
193			`memwr_line_cnt <= (others => '0');`
194			`wr_line_idx <= (others => '0');`
195			`image_write_end <= '0';`
196	25	mikel262	`end if;`
197			`end if;`
198			`end process;`
199	52	mikel262
200	25	mikel262	`-------------------------------------------------------------------`
201	52	mikel262	`-- FIFO half full / almost full flag generation`
202	25	mikel262	`-------------------------------------------------------------------`
203	52	mikel262	`p_mux3 : process(CLK, RST)`
204	25	mikel262	`begin`
205			`if RST = '1' then`
206	52	mikel262	`fdct_fifo_hf_full <= '0';`
207			`fifo_almost_full <= '0';`
208	25	mikel262	`elsif CLK'event and CLK = '1' then`
209	52	mikel262
210	56	mikel262	`if rd_line_idx + 8 <= wr_line_idx then`
211	52	mikel262	`fdct_fifo_hf_full <= '1';`
212			`else`
213			`fdct_fifo_hf_full <= '0';`
214			`end if;`
215
216	58	mikel262	`fifo_almost_full <= '0';`
217			`if C_EXTRA_LINES = 0 then`
218			`if wr_line_idx = rd_line_idx + C_NUM_LINES-1 then`
219			`if pixel_cnt >= unsigned(img_size_x)-1-1 then`
220			`fifo_almost_full <= '1';`
221			`end if;`
222			`elsif wr_line_idx > rd_line_idx + C_NUM_LINES-1 then`
223			`fifo_almost_full <= '1';`
224			`end if;`
225	52	mikel262	`else`
226	58	mikel262	`if wr_line_idx > rd_line_idx + C_NUM_LINES-1 then`
227			`fifo_almost_full <= '1';`
228			`end if;`
229	52	mikel262	`end if;`
230
231	25	mikel262	`end if;`
232			`end process;`
233
234			`-------------------------------------------------------------------`
235	52	mikel262	`-- read side`
236	25	mikel262	`-------------------------------------------------------------------`
237	52	mikel262	`p_mux5 : process(CLK, RST)`
238	25	mikel262	`begin`
239			`if RST = '1' then`
240	56	mikel262	`memrd_offs_cnt <= (others => '0');`
241	52	mikel262	`read_block_cnt <= (others => '0');`
242			`pix_inblk_cnt <= (others => '0');`
243			`line_inblk_cnt <= (others => '0');`
244	56	mikel262	`rd_line_idx <= (others => '0');`
245			`pix_inblk_cnt_d1 <= (others => '0');`
246			`read_block_cnt_d1 <= (others => '0');`
247	25	mikel262	`elsif CLK'event and CLK = '1' then`
248	56	mikel262	`pix_inblk_cnt_d1 <= pix_inblk_cnt;`
249			`read_block_cnt_d1 <= read_block_cnt;`
250
251			`-- BUF FIFO read`
252	52	mikel262	`if fdct_fifo_rd = '1' then`
253	56	mikel262	`-- last pixel in block`
254	52	mikel262	`if pix_inblk_cnt = 8-1 then`
255			`pix_inblk_cnt <= (others => '0');`
256	56	mikel262
257			`-- last line in 8`
258	52	mikel262	`if line_inblk_cnt = 8-1 then`
259			`line_inblk_cnt <= (others => '0');`
260	56	mikel262
261			`-- last block in last line`
262	52	mikel262	`if read_block_cnt = unsigned(img_size_x(15 downto 3))-1 then`
263			`read_block_cnt <= (others => '0');`
264	56	mikel262	`rd_line_idx <= rd_line_idx + 8;`
265			`if memrd_offs_cnt + 8 > C_NUM_LINES-1 then`
266			`memrd_offs_cnt <= memrd_offs_cnt + 8 - C_NUM_LINES;`
267			`else`
268			`memrd_offs_cnt <= memrd_offs_cnt + 8;`
269			`end if;`
270	52	mikel262	`else`
271			`read_block_cnt <= read_block_cnt + 1;`
272			`end if;`
273			`else`
274			`line_inblk_cnt <= line_inblk_cnt + 1;`
275			`end if;`
276	56	mikel262
277	25	mikel262	`else`
278	52	mikel262	`pix_inblk_cnt <= pix_inblk_cnt + 1;`
279	25	mikel262	`end if;`
280	52	mikel262	`end if;`
281
282	56	mikel262	`if memrd_offs_cnt + (line_inblk_cnt) > C_NUM_LINES-1 then`
283			`memrd_line <= memrd_offs_cnt(memrd_line'range) + (line_inblk_cnt) - (C_NUM_LINES);`
284			`else`
285			`memrd_line <= memrd_offs_cnt(memrd_line'range) + (line_inblk_cnt);`
286			`end if;`
287
288	52	mikel262	`if sof = '1' then`
289	56	mikel262	`memrd_line <= (others => '0');`
290			`memrd_offs_cnt <= (others => '0');`
291	52	mikel262	`read_block_cnt <= (others => '0');`
292			`pix_inblk_cnt <= (others => '0');`
293			`line_inblk_cnt <= (others => '0');`
294	56	mikel262	`rd_line_idx <= (others => '0');`
295	52	mikel262	`end if;`
296
297	25	mikel262	`end if;`
298			`end process;`
299
300	52	mikel262	`-- generate RAM data output based on 16 or 24 bit mode selection`
301	51	mikel262	`fdct_fifo_q <= (ramq(15 downto 11) & "000" &`
302			`ramq(10 downto 5) & "00" &`
303			`ramq(4 downto 0) & "000") when C_PIXEL_BITS = 16 else`
304			`std_logic_vector(resize(unsigned(ramq), 24));`
305	25	mikel262
306	28	mikel262
307	52	mikel262	`ramraddr <= ramraddr_int(ramraddr'range);`
308
309	28	mikel262	`-------------------------------------------------------------------`
310	52	mikel262	`-- resolve RAM read address`
311	28	mikel262	`-------------------------------------------------------------------`
312			`p_mux4 : process(CLK, RST)`
313			`begin`
314			`if RST = '1' then`
315	52	mikel262	`ramraddr_int <= (others => '0');`
316	28	mikel262	`elsif CLK'event and CLK = '1' then`
317	56	mikel262	`raddr_base_line <= (memrd_line) * unsigned(img_size_x);`
318			`raddr_tmp <= (read_block_cnt_d1 & "000") + pix_inblk_cnt_d1;`
319	52	mikel262
320			`ramraddr_int <= raddr_tmp + raddr_base_line;`
321	28	mikel262	`end if;`
322			`end process;`
323	25	mikel262
324			`end architecture RTL;`
325			`-------------------------------------------------------------------------------`
326			`-- Architecture: end`
327			`-------------------------------------------------------------------------------`

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