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[/] [mkjpeg/] [trunk/] [design/] [BufFifo/] [BUF_FIFO.vhd] - Blame information for rev 67

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-------------------------------------------------------------------------------
-- File Name : BUF_FIFO.vhd
--
-- Project   : JPEG_ENC
--
-- Module    : BUF_FIFO
--
-- Content   : Input FIFO Buffer
--
-- Description : 
--
-- Spec.     : 
--
-- Author    : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090311: (MK): Initial Creation.
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
        use IEEE.STD_LOGIC_1164.all;
  use ieee.numeric_std.all;
 
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
  use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity BUF_FIFO is
  port
  (
        CLK                : in  std_logic;
        RST                : in  std_logic;
        -- HOST PROG
        img_size_x         : in  std_logic_vector(15 downto 0);
        img_size_y         : in  std_logic_vector(15 downto 0);
        sof                : in  std_logic;
 
        -- HOST DATA
        iram_wren          : in  std_logic;
        iram_wdata         : in  std_logic_vector(C_PIXEL_BITS-1 downto 0);
        fifo_almost_full   : out std_logic;
 
        -- FDCT
        fdct_fifo_rd       : in  std_logic;
        fdct_fifo_q        : out std_logic_vector(23 downto 0);
        fdct_fifo_hf_full  : out std_logic
    );
end entity BUF_FIFO;
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of BUF_FIFO is
 
 
  --constant C_NUM_LINES    : integer := 8 + C_EXTRA_LINES;
  -- No Exstra Lines
  constant C_NUM_LINES    : integer := 8;
 
  signal pixel_cnt        : unsigned(15 downto 0);
  signal line_cnt         : unsigned(15 downto 0);
 
  --signal ramq             : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
  signal q             : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
  --signal ramd             : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
  signal ram_data             : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
 
  signal wr_ptr        : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
  signal ram_write           : STD_LOGIC;
  signal rd_ptr         : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);
 
  signal wr_addr        : unsigned(log2(C_MAX_LINE_WIDTH)-1 downto 0);
  signal we           : STD_LOGIC;
  signal rd_addr         : unsigned(log2(C_MAX_LINE_WIDTH)-1 downto 0);
 
    signal data_out             : STD_LOGIC_VECTOR(15 downto 0);
  --signal ramd             : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
  signal data_in            : unsigned(15 downto 0);
 
 
  signal wr_addr2        : unsigned(log2(C_MAX_LINE_WIDTH)-1 downto 0);
  signal we2           : STD_LOGIC;
  signal rd_addr2         : unsigned(log2(C_MAX_LINE_WIDTH)-1 downto 0);
 
    signal data_out2             : STD_LOGIC_VECTOR(15 downto 0);
  --signal ramd             : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);
  signal data_in2            : unsigned(15 downto 0);
 
  signal pix_inblk_cnt    : unsigned(3 downto 0);
  signal pix_inblk_cnt_d1 : unsigned(3 downto 0);
  signal line_inblk_cnt   : unsigned(2 downto 0);
 
  signal read_block_cnt   : unsigned(12 downto 0);
  signal read_block_cnt_d1 : unsigned(12 downto 0);
  signal write_block_cnt  : unsigned(12 downto 0);
 
  signal ramraddr_int     : unsigned(16+log2(C_NUM_LINES)-1 downto 0);
  signal raddr_base_line  : unsigned(16+log2(C_NUM_LINES)-1 downto 0);
  signal raddr_tmp        : unsigned(15 downto 0);
  --signal ramwaddr_d1      : unsigned(ramwaddr'range);
 
  signal line_lock        : unsigned(log2(C_NUM_LINES)-1 downto 0);
 
  signal memwr_line_cnt   : unsigned(log2(C_NUM_LINES)-1 downto 0);
 
  signal memrd_offs_cnt   : unsigned(log2(C_NUM_LINES)-1+1 downto 0);
  signal memrd_line       : unsigned(log2(C_NUM_LINES)-1 downto 0);
 
  signal wr_line_idx      : unsigned(15 downto 0);
  signal rd_line_idx      : unsigned(15 downto 0);
 
  signal image_write_end  : std_logic;
 
  signal result                                 :std_logic_vector(31 downto 0);
  signal threshold                              :std_logic_vector(31 downto 0);
 
  signal wr_counter : unsigned(15 downto 0);
  signal rd_counter : unsigned(15 downto 0);
 
  signal wr_mod : unsigned(15 downto 0);
  signal rd_mod : unsigned(15 downto 0);
 
  signal wr_counter_total : unsigned(31 downto 0);
  signal rd_counter_total : unsigned(31 downto 0);
  signal counter : unsigned(31 downto 0);
  signal counter2 : unsigned(31 downto 0);
 
  signal init_table_wr : std_logic;
  signal init_table_rd : std_logic;
 
    signal do1 : unsigned(15 downto 0);
  signal do2 : unsigned(15 downto 0);
    signal data_temp : unsigned(15 downto 0);
  signal data_temp2 : unsigned(15 downto 0);
 
   signal temp                          :std_logic_vector(23 downto 0);
 
        signal fifo_almost_full_i  : std_logic;
 
 
 
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
  -------------------------------------------------------------------
  -- RAM for SUB_FIFOs
  -------------------------------------------------------------------
  fifo_almost_full <= fifo_almost_full_i;
 
  U_SUB_RAMZ : entity work.SUB_RAMZ
  generic map
  (
           RAMADDR_W => log2( C_MAX_LINE_WIDTH*C_NUM_LINES ),
           RAMDATA_W => C_PIXEL_BITS
  )
  port map
  (
        d            => ram_data,
        waddr        => std_logic_vector(wr_ptr),
        raddr        => std_logic_vector(rd_ptr),
        we           => ram_write,
        clk          => clk,
 
        q            => q
  );
 
  MULTIPLIER : entity work.multiplier
  PORT MAP(
                CLK => CLK,
                RST => RST,
                img_size_x => img_size_x,
                img_size_y => img_size_y,
                result => result,
                threshold => threshold
        );
 
        U_SUB_RAMZ_WR_ADRESS_LUT : entity work.SUB_RAMZ_LUT
  generic map
  (
           RAMADDR_W => log2( C_MAX_LINE_WIDTH ),
           RAMDATA_W => 16
  )
  port map
  (
        d            => std_logic_vector(data_in),
        waddr        => std_logic_vector(wr_addr),
        raddr        => std_logic_vector(rd_addr),
        we           => we,
        clk          => CLK,
 
        q            => data_out
  );
 
  U_SUB_RAMZ_RD_ADRESS_LUT : entity work.SUB_RAMZ_LUT
  generic map
  (
           RAMADDR_W => log2( C_MAX_LINE_WIDTH ),
           RAMDATA_W => 16
  )
  port map
  (
        d            => std_logic_vector(data_in2),
        waddr        => std_logic_vector(wr_addr2),
        raddr        => std_logic_vector(rd_addr2),
        we           => we2,
        clk          => CLK,
 
        q            => data_out2
  );
 
 
  process (CLK, RST)
  begin
        if (RST = '1') then
                wr_counter <= (others => '0');
                wr_counter_total <= (others => '0');
                wr_mod <= (others => '0');
                wr_ptr <= (others => '0');
 
                ram_write <= '0';
                init_table_wr <= '0';
                do1 <= (others => '0');
                data_temp <= (others => '0');
                wr_addr <= (others => '0');
                rd_addr <= (others => '0');
                we <= '0';
                counter <= (others => '0');
        elsif (CLK'event and CLK = '1') then
                if (init_table_wr = '0') then
                        if (iram_wren = '1') then
                                if (wr_mod /= 0 and wr_counter mod 8 = "000") then
                                          wr_ptr <= resize(do1(5 downto 3) * unsigned(img_size_x), log2(C_MAX_LINE_WIDTH*C_NUM_LINES)) + resize(do1(15 downto 6) * 8, log2(C_MAX_LINE_WIDTH*C_NUM_LINES));
                                                data_temp <=  resize(do1(5 downto 3) * unsigned(img_size_x), 16) + resize(do1(15 downto 6) * 8, 16);
 
                                        --wr_ptr <= do1 / 8 mod 8 *  unsigned(img_size_x) + do1 / 8 / 8 * 8;
                                        --data_temp <= do1 / 8 mod 8 *  unsigned(img_size_x) + do1 / 8 / 8 * 8;
                                else
                                        if (wr_counter = 0) then
                                                wr_ptr <= (others => '0');
                                        else
                                                wr_ptr <= wr_ptr + 1;
                                        end if;
                                end if;
 
                                if (wr_mod /= 0 and wr_counter mod 8 = "011") then
                                        if (wr_counter = unsigned(img_size_x) * 8 - 5) then
                                                rd_addr <= (others => '0');
                                        else
                                                rd_addr <= resize((wr_counter + 5) / 8, log2(C_MAX_LINE_WIDTH));
                                        end if;
                                end if;
 
                                if (wr_mod /= 0 and wr_counter mod 8 = "101") then
                                        do1 <= unsigned(data_out);
                                        we <= '1';
 
                                        if (wr_mod = unsigned(img_size_y) / 8 - 1) then
                                                wr_addr <= resize(counter, log2(C_MAX_LINE_WIDTH));
                                                data_in <= resize(counter * 8, 16);
                                                counter <= counter + 1;
                                        else
                                                data_in <= data_temp;
                                                if (wr_counter = unsigned(img_size_x) * 8 - 3) then
                                                        wr_addr <= (others => '0');
                                                else
                                                        wr_addr <= resize((wr_counter + 3) / 8 - 1, log2(C_MAX_LINE_WIDTH));
                                                end if;
                                        end if;
                                else
                                        we <= '0';
                                end if;
 
                                ram_write <= '1';
                                ram_data <= iram_wdata;
 
                                wr_counter_total <= wr_counter_total  + 1;
 
                                if (wr_counter_total = unsigned(result) - 1) then
 
                                        init_table_wr <= '1';
                                        counter <= (others => '0');
                                end if;
 
                                if (wr_counter = unsigned(img_size_x) * 8 - 1)  then
                                        wr_counter <= (others => '0');
                                        wr_mod <= wr_mod + 1;
                                else
                                        wr_counter <= wr_counter + 1;
                                end if;
                        else
                                ram_write <= '0';
                        end if;
 
      if sof = '1' then
        wr_counter <= (others => '0');
        wr_counter_total <= (others => '0');
        wr_mod <= (others => '0');
        wr_ptr <= (others => '0');
 
        ram_write <= '0';
        init_table_wr <= '0';
        do1 <= (others => '0');
        data_temp <= (others => '0');
        wr_addr <= (others => '0');
        rd_addr <= (others => '0');
        we <= '0';
        counter <= (others => '0');
      end if;
 
                end if;
 
 
 
 
        end if;
  end process;
 
        process (CLK, RST)
        begin
                if (RST = '1') then
                        fifo_almost_full_i <= '0';
                        fdct_fifo_hf_full <= '0';
                elsif (CLK'event and CLK = '1') then
                                if (fifo_almost_full_i = '0' and wr_counter_total  = rd_counter_total + unsigned(img_size_x)*8-2) then
 
                                        fifo_almost_full_i <= '1';
 
                                end if;
 
                                if (fifo_almost_full_i = '1' and wr_counter_total < rd_counter_total + unsigned(threshold) ) then
 
                                        fifo_almost_full_i <= '0';
 
                                end if;
 
                                if (wr_counter = unsigned(img_size_x) * 8 - 1) then
 
                                        fdct_fifo_hf_full <= '1';
                                end if;
 
                                if (rd_counter = unsigned(img_size_x) * 8 - 1) then
 
                                        fdct_fifo_hf_full <= '0';
                                        fifo_almost_full_i <= '0';
                                end if;
 
        if sof = '1' then
          fifo_almost_full_i <= '0';
                            fdct_fifo_hf_full <= '0';
        end if;
 
                end if;
        end process;
 
 
 
        process (CLK, RST)
        begin
                if (RST = '1') then
                        fdct_fifo_q <= (others => '0');
                        temp <= (others => '0');
                        rd_counter <= (others => '0');
                        rd_counter_total <= (others => '0');
                        rd_mod <= x"0001";
                        rd_ptr <= (others => '0');
                        init_table_rd <= '0';
                        do2 <= (others => '0');
                        data_temp2 <= (others => '0');
                        wr_addr2 <= (others => '0');
                        rd_addr2 <= (others => '0');
                        we2 <= '0';
                        counter2 <= (others => '0');
                elsif (CLK'event and CLK = '1') then
                        if (init_table_rd = '0') then
                                if (fdct_fifo_rd = '1') then
                                        if (rd_counter mod 8 = "000") then
                                                --rd_ptr <=  resize(do2(5 downto 3) *  unsigned(img_size_x) + do2(15 downto 7) * 8, log2(C_MAX_LINE_WIDTH*C_NUM_LINES));
                                                --data_temp2 <=  resize(do2(5 downto 3) *  unsigned(img_size_x) + do2(15 downto 7) * 8, 16);
                                                rd_ptr <= resize(do2(5 downto 3) * unsigned(img_size_x), log2(C_MAX_LINE_WIDTH*C_NUM_LINES)) + resize(do2(15 downto 6) * 8, log2(C_MAX_LINE_WIDTH*C_NUM_LINES));
                                                data_temp2 <=  resize(do2(5 downto 3) * unsigned(img_size_x), 16) + resize(do2(15 downto 6) * 8, 16);
                                        else
                                                rd_ptr <= rd_ptr + 1;
                                        end if;
 
                                        if (rd_counter mod 8 = "011") then
                                                if (rd_counter = unsigned(img_size_x) * 8 - 5) then
                                                        rd_addr2 <= (others => '0');
                                                else
                                                        rd_addr2 <= resize(unsigned(rd_counter + 5) / 8, log2(C_MAX_LINE_WIDTH));
                                                end if;
                                        end if;
 
                                        if (rd_counter mod 8 = "101") then
                                                do2 <= unsigned(data_out2);
                                                we2 <= '1';
                                                if (rd_mod = unsigned(img_size_y) / 8) then
                                                        data_in2 <= resize(counter2 * 8, 16);
                                                        wr_addr2 <= resize(counter2, log2(C_MAX_LINE_WIDTH));
                                                        counter2 <= counter2 + 1;
                                                else
                                                        data_in2 <= data_temp2;
                                                        if (rd_counter = unsigned(img_size_x) * 8 - 3) then
                                                                wr_addr2 <= (others => '0');
                                                        else
 
                                                                wr_addr2 <= resize(unsigned(rd_counter + 3) / 8 - 1, log2(C_MAX_LINE_WIDTH));
 
                                                        end if;
                                                end if;
                                        else
                                                we2 <= '0';
                                        end if;
 
                                        rd_counter_total <= rd_counter_total  + 1;
 
                                        if (rd_counter_total = unsigned(result) - 1) then
 
                                                init_table_rd <= '1';
                                                counter2 <= (others => '0');
                                        end if;
 
                                        if (rd_counter = unsigned(img_size_x) * 8 - 1) then
 
                                                rd_counter <= (others => '0');
                                                rd_mod <= rd_mod + 1;
 
                                        else
                                                rd_counter <= rd_counter + 1;
                                        end if;
 
 
 
 
                                end if;
 
                                if sof = '1' then
          fdct_fifo_q <= (others => '0');
          temp <= (others => '0');
          rd_counter <= (others => '0');
          rd_counter_total <= (others => '0');
          rd_mod <= x"0001";
          rd_ptr <= (others => '0');
          init_table_rd <= '0';
          do2 <= (others => '0');
          data_temp2 <= (others => '0');
          wr_addr2 <= (others => '0');
          rd_addr2 <= (others => '0');
          we2 <= '0';
          counter2 <= (others => '0');
        end if;
 
 
--                               fdct_fifo_q <= (temp(15 downto 11) & "000" & 
--                 temp(10 downto 5) & "00" & 
--                 temp(4 downto 0) & "000") when C_PIXEL_BITS = 16 else 
--                 std_logic_vector(resize(unsigned(temp), 24));
                        end if;
 
                        temp <= q;
                        if (C_PIXEL_BITS = 16) then
 
                                fdct_fifo_q <= (temp(15 downto 11) & "000" &
                                  temp(10 downto 5) & "00" &
                                  temp(4 downto 0) & "000");
                        else
                                fdct_fifo_q <= temp;
                        end if;
 
                end if;
        end process;
 
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------

Line No.	Rev	Author	Line
1	25	mikel262	`-------------------------------------------------------------------------------`
2			`-- File Name : BUF_FIFO.vhd`
3			`--`
4			`-- Project : JPEG_ENC`
5			`--`
6			`-- Module : BUF_FIFO`
7			`--`
8			`-- Content : Input FIFO Buffer`
9			`--`
10			`-- Description :`
11			`--`
12			`-- Spec. :`
13			`--`
14			`-- Author : Michal Krepa`
15			`--`
16			`-------------------------------------------------------------------------------`
17			`-- History :`
18			`-- 20090311: (MK): Initial Creation.`
19			`-------------------------------------------------------------------------------`
20
21			`-------------------------------------------------------------------------------`
22			`-------------------------------------------------------------------------------`
23			`----------------------------------- LIBRARY/PACKAGE ---------------------------`
24			`-------------------------------------------------------------------------------`
25			`-------------------------------------------------------------------------------`
26
27			`-------------------------------------------------------------------------------`
28			`-- generic packages/libraries:`
29			`-------------------------------------------------------------------------------`
30			`library ieee;`
31	67	mikel262	`use IEEE.STD_LOGIC_1164.all;`
32	25	mikel262	`use ieee.numeric_std.all;`
33
34			`-------------------------------------------------------------------------------`
35			`-- user packages/libraries:`
36			`-------------------------------------------------------------------------------`
37			`library work;`
38			`use work.JPEG_PKG.all;`
39			`-------------------------------------------------------------------------------`
40			`-------------------------------------------------------------------------------`
41			`----------------------------------- ENTITY ------------------------------------`
42			`-------------------------------------------------------------------------------`
43			`-------------------------------------------------------------------------------`
44			`entity BUF_FIFO is`
45			`port`
46			`(`
47			`CLK : in std_logic;`
48			`RST : in std_logic;`
49			`-- HOST PROG`
50			`img_size_x : in std_logic_vector(15 downto 0);`
51			`img_size_y : in std_logic_vector(15 downto 0);`
52			`sof : in std_logic;`
53
54			`-- HOST DATA`
55			`iram_wren : in std_logic;`
56	49	mikel262	`iram_wdata : in std_logic_vector(C_PIXEL_BITS-1 downto 0);`
57	25	mikel262	`fifo_almost_full : out std_logic;`
58
59			`-- FDCT`
60			`fdct_fifo_rd : in std_logic;`
61			`fdct_fifo_q : out std_logic_vector(23 downto 0);`
62			`fdct_fifo_hf_full : out std_logic`
63			`);`
64			`end entity BUF_FIFO;`
65
66			`-------------------------------------------------------------------------------`
67			`-------------------------------------------------------------------------------`
68			`----------------------------------- ARCHITECTURE ------------------------------`
69			`-------------------------------------------------------------------------------`
70			`-------------------------------------------------------------------------------`
71			`architecture RTL of BUF_FIFO is`
72
73	56	mikel262
74	67	mikel262	`--constant C_NUM_LINES : integer := 8 + C_EXTRA_LINES;`
75			`-- No Exstra Lines`
76			`constant C_NUM_LINES : integer := 8;`
77
78	52	mikel262	`signal pixel_cnt : unsigned(15 downto 0);`
79			`signal line_cnt : unsigned(15 downto 0);`
80
81	67	mikel262	`--signal ramq : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);`
82			`signal q : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);`
83			`--signal ramd : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);`
84			`signal ram_data : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);`
85	49	mikel262
86	67	mikel262	`signal wr_ptr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);`
87			`signal ram_write : STD_LOGIC;`
88			`signal rd_ptr : unsigned(log2(C_MAX_LINE_WIDTH*C_NUM_LINES)-1 downto 0);`
89
90			`signal wr_addr : unsigned(log2(C_MAX_LINE_WIDTH)-1 downto 0);`
91			`signal we : STD_LOGIC;`
92			`signal rd_addr : unsigned(log2(C_MAX_LINE_WIDTH)-1 downto 0);`
93
94			`signal data_out : STD_LOGIC_VECTOR(15 downto 0);`
95			`--signal ramd : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);`
96			`signal data_in : unsigned(15 downto 0);`
97
98
99			`signal wr_addr2 : unsigned(log2(C_MAX_LINE_WIDTH)-1 downto 0);`
100			`signal we2 : STD_LOGIC;`
101			`signal rd_addr2 : unsigned(log2(C_MAX_LINE_WIDTH)-1 downto 0);`
102
103			`signal data_out2 : STD_LOGIC_VECTOR(15 downto 0);`
104			`--signal ramd : STD_LOGIC_VECTOR(C_PIXEL_BITS-1 downto 0);`
105			`signal data_in2 : unsigned(15 downto 0);`
106
107	61	mikel262	`signal pix_inblk_cnt : unsigned(3 downto 0);`
108			`signal pix_inblk_cnt_d1 : unsigned(3 downto 0);`
109	56	mikel262	`signal line_inblk_cnt : unsigned(2 downto 0);`
110	25	mikel262
111	52	mikel262	`signal read_block_cnt : unsigned(12 downto 0);`
112	56	mikel262	`signal read_block_cnt_d1 : unsigned(12 downto 0);`
113	52	mikel262	`signal write_block_cnt : unsigned(12 downto 0);`
114	25	mikel262
115	56	mikel262	`signal ramraddr_int : unsigned(16+log2(C_NUM_LINES)-1 downto 0);`
116			`signal raddr_base_line : unsigned(16+log2(C_NUM_LINES)-1 downto 0);`
117	52	mikel262	`signal raddr_tmp : unsigned(15 downto 0);`
118	67	mikel262	`--signal ramwaddr_d1 : unsigned(ramwaddr'range);`
119	25	mikel262
120	56	mikel262	`signal line_lock : unsigned(log2(C_NUM_LINES)-1 downto 0);`
121	28	mikel262
122	56	mikel262	`signal memwr_line_cnt : unsigned(log2(C_NUM_LINES)-1 downto 0);`
123
124			`signal memrd_offs_cnt : unsigned(log2(C_NUM_LINES)-1+1 downto 0);`
125			`signal memrd_line : unsigned(log2(C_NUM_LINES)-1 downto 0);`
126
127			`signal wr_line_idx : unsigned(15 downto 0);`
128			`signal rd_line_idx : unsigned(15 downto 0);`
129
130			`signal image_write_end : std_logic;`
131
132	67	mikel262	`signal result :std_logic_vector(31 downto 0);`
133			`signal threshold :std_logic_vector(31 downto 0);`
134	56	mikel262
135	67	mikel262	`signal wr_counter : unsigned(15 downto 0);`
136			`signal rd_counter : unsigned(15 downto 0);`
137	56	mikel262
138	67	mikel262	`signal wr_mod : unsigned(15 downto 0);`
139			`signal rd_mod : unsigned(15 downto 0);`
140
141			`signal wr_counter_total : unsigned(31 downto 0);`
142			`signal rd_counter_total : unsigned(31 downto 0);`
143			`signal counter : unsigned(31 downto 0);`
144			`signal counter2 : unsigned(31 downto 0);`
145
146			`signal init_table_wr : std_logic;`
147			`signal init_table_rd : std_logic;`
148
149			`signal do1 : unsigned(15 downto 0);`
150			`signal do2 : unsigned(15 downto 0);`
151			`signal data_temp : unsigned(15 downto 0);`
152			`signal data_temp2 : unsigned(15 downto 0);`
153
154			`signal temp :std_logic_vector(23 downto 0);`
155
156			`signal fifo_almost_full_i : std_logic;`
157
158
159
160	25	mikel262	`-------------------------------------------------------------------------------`
161			`-- Architecture: begin`
162			`-------------------------------------------------------------------------------`
163	52	mikel262	`begin`
164	25	mikel262	`-------------------------------------------------------------------`
165	28	mikel262	`-- RAM for SUB_FIFOs`
166			`-------------------------------------------------------------------`
167	67	mikel262	`fifo_almost_full <= fifo_almost_full_i;`
168
169	28	mikel262	`U_SUB_RAMZ : entity work.SUB_RAMZ`
170			`generic map`
171			`(`
172	56	mikel262	`RAMADDR_W => log2( C_MAX_LINE_WIDTH*C_NUM_LINES ),`
173	28	mikel262	`RAMDATA_W => C_PIXEL_BITS`
174			`)`
175			`port map`
176			`(`
177	67	mikel262	`d => ram_data,`
178			`waddr => std_logic_vector(wr_ptr),`
179			`raddr => std_logic_vector(rd_ptr),`
180			`we => ram_write,`
181	28	mikel262	`clk => clk,`
182
183	67	mikel262	`q => q`
184	28	mikel262	`);`
185
186	67	mikel262	`MULTIPLIER : entity work.multiplier`
187			`PORT MAP(`
188			`CLK => CLK,`
189			`RST => RST,`
190			`img_size_x => img_size_x,`
191			`img_size_y => img_size_y,`
192			`result => result,`
193			`threshold => threshold`
194			`);`
195
196			`U_SUB_RAMZ_WR_ADRESS_LUT : entity work.SUB_RAMZ_LUT`
197			`generic map`
198			`(`
199			`RAMADDR_W => log2( C_MAX_LINE_WIDTH ),`
200			`RAMDATA_W => 16`
201			`)`
202			`port map`
203			`(`
204			`d => std_logic_vector(data_in),`
205			`waddr => std_logic_vector(wr_addr),`
206			`raddr => std_logic_vector(rd_addr),`
207			`we => we,`
208			`clk => CLK,`
209
210			`q => data_out`
211			`);`
212	25	mikel262
213	67	mikel262	`U_SUB_RAMZ_RD_ADRESS_LUT : entity work.SUB_RAMZ_LUT`
214			`generic map`
215			`(`
216			`RAMADDR_W => log2( C_MAX_LINE_WIDTH ),`
217			`RAMDATA_W => 16`
218			`)`
219			`port map`
220			`(`
221			`d => std_logic_vector(data_in2),`
222			`waddr => std_logic_vector(wr_addr2),`
223			`raddr => std_logic_vector(rd_addr2),`
224			`we => we2,`
225			`clk => CLK,`
226
227			`q => data_out2`
228			`);`
229
230
231			`process (CLK, RST)`
232	25	mikel262	`begin`
233	67	mikel262	`if (RST = '1') then`
234			`wr_counter <= (others => '0');`
235			`wr_counter_total <= (others => '0');`
236			`wr_mod <= (others => '0');`
237			`wr_ptr <= (others => '0');`
238
239			`ram_write <= '0';`
240			`init_table_wr <= '0';`
241			`do1 <= (others => '0');`
242			`data_temp <= (others => '0');`
243			`wr_addr <= (others => '0');`
244			`rd_addr <= (others => '0');`
245			`we <= '0';`
246			`counter <= (others => '0');`
247			`elsif (CLK'event and CLK = '1') then`
248			`if (init_table_wr = '0') then`
249			`if (iram_wren = '1') then`
250			`if (wr_mod /= 0 and wr_counter mod 8 = "000") then`
251			`wr_ptr <= resize(do1(5 downto 3) * unsigned(img_size_x), log2(C_MAX_LINE_WIDTHC_NUM_LINES)) + resize(do1(15 downto 6) 8, log2(C_MAX_LINE_WIDTH*C_NUM_LINES));`
252			`data_temp <= resize(do1(5 downto 3) * unsigned(img_size_x), 16) + resize(do1(15 downto 6) * 8, 16);`
253
254			`--wr_ptr <= do1 / 8 mod 8 * unsigned(img_size_x) + do1 / 8 / 8 * 8;`
255			`--data_temp <= do1 / 8 mod 8 * unsigned(img_size_x) + do1 / 8 / 8 * 8;`
256			`else`
257			`if (wr_counter = 0) then`
258			`wr_ptr <= (others => '0');`
259			`else`
260			`wr_ptr <= wr_ptr + 1;`
261			`end if;`
262			`end if;`
263
264			`if (wr_mod /= 0 and wr_counter mod 8 = "011") then`
265			`if (wr_counter = unsigned(img_size_x) * 8 - 5) then`
266			`rd_addr <= (others => '0');`
267			`else`
268			`rd_addr <= resize((wr_counter + 5) / 8, log2(C_MAX_LINE_WIDTH));`
269			`end if;`
270			`end if;`
271
272			`if (wr_mod /= 0 and wr_counter mod 8 = "101") then`
273			`do1 <= unsigned(data_out);`
274			`we <= '1';`
275
276			`if (wr_mod = unsigned(img_size_y) / 8 - 1) then`
277			`wr_addr <= resize(counter, log2(C_MAX_LINE_WIDTH));`
278			`data_in <= resize(counter * 8, 16);`
279			`counter <= counter + 1;`
280			`else`
281			`data_in <= data_temp;`
282			`if (wr_counter = unsigned(img_size_x) * 8 - 3) then`
283			`wr_addr <= (others => '0');`
284			`else`
285			`wr_addr <= resize((wr_counter + 3) / 8 - 1, log2(C_MAX_LINE_WIDTH));`
286			`end if;`
287			`end if;`
288			`else`
289			`we <= '0';`
290			`end if;`
291
292			`ram_write <= '1';`
293			`ram_data <= iram_wdata;`
294
295			`wr_counter_total <= wr_counter_total + 1;`
296
297			`if (wr_counter_total = unsigned(result) - 1) then`
298
299			`init_table_wr <= '1';`
300			`counter <= (others => '0');`
301			`end if;`
302
303			`if (wr_counter = unsigned(img_size_x) * 8 - 1) then`
304			`wr_counter <= (others => '0');`
305			`wr_mod <= wr_mod + 1;`
306			`else`
307			`wr_counter <= wr_counter + 1;`
308			`end if;`
309			`else`
310			`ram_write <= '0';`
311			`end if;`
312
313	25	mikel262	`if sof = '1' then`
314	67	mikel262	`wr_counter <= (others => '0');`
315			`wr_counter_total <= (others => '0');`
316			`wr_mod <= (others => '0');`
317			`wr_ptr <= (others => '0');`
318
319			`ram_write <= '0';`
320			`init_table_wr <= '0';`
321			`do1 <= (others => '0');`
322			`data_temp <= (others => '0');`
323			`wr_addr <= (others => '0');`
324			`rd_addr <= (others => '0');`
325			`we <= '0';`
326			`counter <= (others => '0');`
327	25	mikel262	`end if;`
328	67	mikel262
329			`end if;`
330
331
332
333
334			`end if;`
335	25	mikel262	`end process;`
336	52	mikel262
337	67	mikel262	`process (CLK, RST)`
338			`begin`
339			`if (RST = '1') then`
340			`fifo_almost_full_i <= '0';`
341			`fdct_fifo_hf_full <= '0';`
342			`elsif (CLK'event and CLK = '1') then`
343			`if (fifo_almost_full_i = '0' and wr_counter_total = rd_counter_total + unsigned(img_size_x)*8-2) then`
344
345			`fifo_almost_full_i <= '1';`
346
347			`end if;`
348
349			`if (fifo_almost_full_i = '1' and wr_counter_total < rd_counter_total + unsigned(threshold) ) then`
350
351			`fifo_almost_full_i <= '0';`
352
353			`end if;`
354
355			`if (wr_counter = unsigned(img_size_x) * 8 - 1) then`
356
357			`fdct_fifo_hf_full <= '1';`
358			`end if;`
359
360			`if (rd_counter = unsigned(img_size_x) * 8 - 1) then`
361
362			`fdct_fifo_hf_full <= '0';`
363			`fifo_almost_full_i <= '0';`
364			`end if;`
365	52	mikel262
366	67	mikel262	`if sof = '1' then`
367			`fifo_almost_full_i <= '0';`
368			`fdct_fifo_hf_full <= '0';`
369	58	mikel262	`end if;`
370	67	mikel262
371			`end if;`
372			`end process;`
373
374
375
376			`process (CLK, RST)`
377			`begin`
378			`if (RST = '1') then`
379			`fdct_fifo_q <= (others => '0');`
380			`temp <= (others => '0');`
381			`rd_counter <= (others => '0');`
382			`rd_counter_total <= (others => '0');`
383			`rd_mod <= x"0001";`
384			`rd_ptr <= (others => '0');`
385			`init_table_rd <= '0';`
386			`do2 <= (others => '0');`
387			`data_temp2 <= (others => '0');`
388			`wr_addr2 <= (others => '0');`
389			`rd_addr2 <= (others => '0');`
390			`we2 <= '0';`
391			`counter2 <= (others => '0');`
392			`elsif (CLK'event and CLK = '1') then`
393			`if (init_table_rd = '0') then`
394			`if (fdct_fifo_rd = '1') then`
395			`if (rd_counter mod 8 = "000") then`
396			`--rd_ptr <= resize(do2(5 downto 3) * unsigned(img_size_x) + do2(15 downto 7) * 8, log2(C_MAX_LINE_WIDTH*C_NUM_LINES));`
397			`--data_temp2 <= resize(do2(5 downto 3) * unsigned(img_size_x) + do2(15 downto 7) * 8, 16);`
398			`rd_ptr <= resize(do2(5 downto 3) * unsigned(img_size_x), log2(C_MAX_LINE_WIDTHC_NUM_LINES)) + resize(do2(15 downto 6) 8, log2(C_MAX_LINE_WIDTH*C_NUM_LINES));`
399			`data_temp2 <= resize(do2(5 downto 3) * unsigned(img_size_x), 16) + resize(do2(15 downto 6) * 8, 16);`
400			`else`
401			`rd_ptr <= rd_ptr + 1;`
402			`end if;`
403
404			`if (rd_counter mod 8 = "011") then`
405			`if (rd_counter = unsigned(img_size_x) * 8 - 5) then`
406			`rd_addr2 <= (others => '0');`
407			`else`
408			`rd_addr2 <= resize(unsigned(rd_counter + 5) / 8, log2(C_MAX_LINE_WIDTH));`
409			`end if;`
410			`end if;`
411
412			`if (rd_counter mod 8 = "101") then`
413			`do2 <= unsigned(data_out2);`
414			`we2 <= '1';`
415			`if (rd_mod = unsigned(img_size_y) / 8) then`
416			`data_in2 <= resize(counter2 * 8, 16);`
417			`wr_addr2 <= resize(counter2, log2(C_MAX_LINE_WIDTH));`
418			`counter2 <= counter2 + 1;`
419			`else`
420			`data_in2 <= data_temp2;`
421			`if (rd_counter = unsigned(img_size_x) * 8 - 3) then`
422			`wr_addr2 <= (others => '0');`
423			`else`
424
425			`wr_addr2 <= resize(unsigned(rd_counter + 3) / 8 - 1, log2(C_MAX_LINE_WIDTH));`
426
427			`end if;`
428			`end if;`
429			`else`
430			`we2 <= '0';`
431			`end if;`
432
433			`rd_counter_total <= rd_counter_total + 1;`
434
435			`if (rd_counter_total = unsigned(result) - 1) then`
436
437			`init_table_rd <= '1';`
438			`counter2 <= (others => '0');`
439			`end if;`
440
441			`if (rd_counter = unsigned(img_size_x) * 8 - 1) then`
442
443			`rd_counter <= (others => '0');`
444			`rd_mod <= rd_mod + 1;`
445
446			`else`
447			`rd_counter <= rd_counter + 1;`
448			`end if;`
449
450
451
452
453			`end if;`
454
455			`if sof = '1' then`
456			`fdct_fifo_q <= (others => '0');`
457			`temp <= (others => '0');`
458			`rd_counter <= (others => '0');`
459			`rd_counter_total <= (others => '0');`
460			`rd_mod <= x"0001";`
461			`rd_ptr <= (others => '0');`
462			`init_table_rd <= '0';`
463			`do2 <= (others => '0');`
464			`data_temp2 <= (others => '0');`
465			`wr_addr2 <= (others => '0');`
466			`rd_addr2 <= (others => '0');`
467			`we2 <= '0';`
468			`counter2 <= (others => '0');`
469			`end if;`
470
471
472			`-- fdct_fifo_q <= (temp(15 downto 11) & "000" &`
473			`-- temp(10 downto 5) & "00" &`
474			`-- temp(4 downto 0) & "000") when C_PIXEL_BITS = 16 else`
475			`-- std_logic_vector(resize(unsigned(temp), 24));`
476			`end if;`
477
478			`temp <= q;`
479			`if (C_PIXEL_BITS = 16) then`
480
481			`fdct_fifo_q <= (temp(15 downto 11) & "000" &`
482			`temp(10 downto 5) & "00" &`
483			`temp(4 downto 0) & "000");`
484			`else`
485			`fdct_fifo_q <= temp;`
486			`end if;`
487	61	mikel262
488	67	mikel262	`end if;`
489			`end process;`
490	25	mikel262
491			`end architecture RTL;`
492			`-------------------------------------------------------------------------------`
493			`-- Architecture: end`
494			`-------------------------------------------------------------------------------`

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