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[/] [mkjpeg/] [trunk/] [design/] [BufFifo/] [SUB_FIFO.vhd] - Blame information for rev 30

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1 30 mikel262
 
2
library IEEE;
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  use IEEE.STD_LOGIC_1164.all;
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  use IEEE.STD_LOGIC_UNSIGNED.all;
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library WORK;
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entity SUB_FIFO is
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  generic (
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        DATA_WIDTH         : INTEGER   := 12;
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        ADDR_WIDTH         : INTEGER   := 2
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       );
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  port (
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        rst               : in  STD_LOGIC;
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        clk               : in  STD_LOGIC;
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        rinc              : in  STD_LOGIC;
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        winc              : in  STD_LOGIC;
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        fullo             : out STD_LOGIC;
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        emptyo            : out STD_LOGIC;
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        count             : out STD_LOGIC_VECTOR (ADDR_WIDTH downto 0);
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        ramwaddr          : out STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
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        ramenw            : out STD_LOGIC;
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        ramraddr          : out STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
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        ramenr            : out STD_LOGIC
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        );
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end SUB_FIFO;
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architecture RTL of SUB_FIFO is
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  signal raddr_reg        : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
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  signal waddr_reg        : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
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  signal count_reg        : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0);
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  signal rd_en_reg        : STD_LOGIC;
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  signal wr_en_reg        : STD_LOGIC;
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  signal empty_reg        : STD_LOGIC;
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  signal full_reg         : STD_LOGIC;
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  constant ZEROS_C        : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '0');
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  constant ONES_C         : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
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begin
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  ramwaddr                <= waddr_reg;
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  ramenw                  <= wr_en_reg;
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  ramraddr                <= raddr_reg;
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  ramenr                  <= '1';
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  emptyo                  <= empty_reg;
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  fullo                   <= full_reg;
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  rd_en_reg               <= (rinc and not empty_reg);
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  wr_en_reg               <= (winc and not full_reg);
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  count <= count_reg;
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  process(clk)
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  begin
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    if clk = '1' and clk'event then
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      if rst = '1' then
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        empty_reg         <= '1';
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      else
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        if count_reg = ZEROS_C or
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          (count_reg = 1 and rd_en_reg = '1' and wr_en_reg = '0') then
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          empty_reg       <= '1';
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        else
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          empty_reg       <= '0';
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        end if;
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      end if;
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    end if;
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  end process;
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  process(clk)
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  begin
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    if clk = '1' and clk'event then
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      if rst = '1' then
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        full_reg          <= '0';
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      else
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        if count_reg = 2**ADDR_WIDTH or
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          (count_reg = 2**ADDR_WIDTH-1 and wr_en_reg = '1' and rd_en_reg = '0') then
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          full_reg        <= '1';
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        else
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          full_reg        <= '0';
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        end if;
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      end if;
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    end if;
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  end process;
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  process(clk)
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  begin
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    if clk = '1' and clk'event then
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      if rst = '1' then
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        raddr_reg         <= (others => '0');
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      else
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        if rd_en_reg = '1' then
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          raddr_reg       <= raddr_reg + '1';
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        end if;
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      end if;
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    end if;
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  end process;
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  process(clk)
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  begin
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    if clk = '1' and clk'event then
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      if rst = '1' then
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        waddr_reg         <= (others => '0');
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      else
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        if wr_en_reg = '1' then
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          waddr_reg       <= waddr_reg + '1';
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        end if;
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      end if;
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    end if;
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  end process;
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  process(clk)
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  begin
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    if clk = '1' and clk'event then
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      if rst = '1' then
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        count_reg         <= (others => '0');
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      else
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        if (rd_en_reg = '1' and wr_en_reg = '0') or (rd_en_reg = '0' and wr_en_reg = '1') then
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          if rd_en_reg = '1' then
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            count_reg     <= count_reg - '1';
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          else
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            count_reg     <= count_reg + '1';
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          end if;
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        end if;
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      end if;
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    end if;
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  end process;
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end RTL;

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