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[/] [mkjpeg/] [trunk/] [design/] [BufFifo/] [SUB_FIFO.vhd] - Blame information for rev 40

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library IEEE;
  use IEEE.STD_LOGIC_1164.all;
  use IEEE.STD_LOGIC_UNSIGNED.all;
library WORK;
 
entity SUB_FIFO is
  generic (
        DATA_WIDTH         : INTEGER   := 12;
        ADDR_WIDTH         : INTEGER   := 2
       );
  port (
        rst               : in  STD_LOGIC;
        clk               : in  STD_LOGIC;
        rinc              : in  STD_LOGIC;
        winc              : in  STD_LOGIC;
 
        fullo             : out STD_LOGIC;
        emptyo            : out STD_LOGIC;
        count             : out STD_LOGIC_VECTOR (ADDR_WIDTH downto 0);
 
        ramwaddr          : out STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
        ramenw            : out STD_LOGIC;
        ramraddr          : out STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
        ramenr            : out STD_LOGIC
        );
end SUB_FIFO;
 
architecture RTL of SUB_FIFO is
 
  signal raddr_reg        : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
  signal waddr_reg        : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
  signal count_reg        : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0);
  signal rd_en_reg        : STD_LOGIC;
  signal wr_en_reg        : STD_LOGIC;
  signal empty_reg        : STD_LOGIC;
  signal full_reg         : STD_LOGIC;
 
  constant ZEROS_C        : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '0');
  constant ONES_C         : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
 
begin
 
  ramwaddr                <= waddr_reg;
  ramenw                  <= wr_en_reg;
  ramraddr                <= raddr_reg;
  ramenr                  <= '1';
 
  emptyo                  <= empty_reg;
  fullo                   <= full_reg;
  rd_en_reg               <= (rinc and not empty_reg);
  wr_en_reg               <= (winc and not full_reg);
 
  count <= count_reg;
 
  process(clk)
  begin
    if clk = '1' and clk'event then
      if rst = '1' then
        empty_reg         <= '1';
      else
        if count_reg = ZEROS_C or
          (count_reg = 1 and rd_en_reg = '1' and wr_en_reg = '0') then
          empty_reg       <= '1';
        else
          empty_reg       <= '0';
        end if;
      end if;
    end if;
  end process;
 
  process(clk)
  begin
    if clk = '1' and clk'event then
      if rst = '1' then
        full_reg          <= '0';
      else
        if count_reg = 2**ADDR_WIDTH or
          (count_reg = 2**ADDR_WIDTH-1 and wr_en_reg = '1' and rd_en_reg = '0') then
          full_reg        <= '1';
        else
          full_reg        <= '0';
        end if;
      end if;
    end if;
  end process;
 
  process(clk)
  begin
    if clk = '1' and clk'event then
      if rst = '1' then
        raddr_reg         <= (others => '0');
      else
        if rd_en_reg = '1' then
          raddr_reg       <= raddr_reg + '1';
        end if;
      end if;
    end if;
  end process;
 
  process(clk)
  begin
    if clk = '1' and clk'event then
      if rst = '1' then
        waddr_reg         <= (others => '0');
      else
        if wr_en_reg = '1' then
          waddr_reg       <= waddr_reg + '1';
        end if;
      end if;
    end if;
  end process;
 
  process(clk)
  begin
    if clk = '1' and clk'event then
      if rst = '1' then
        count_reg         <= (others => '0');
      else
        if (rd_en_reg = '1' and wr_en_reg = '0') or (rd_en_reg = '0' and wr_en_reg = '1') then
          if rd_en_reg = '1' then
            count_reg     <= count_reg - '1';
          else
            count_reg     <= count_reg + '1';
          end if;
        end if;
      end if;
    end if;
  end process;
 
end RTL;

Line No.	Rev	Author	Line
1	30	mikel262
2			`library IEEE;`
3			`use IEEE.STD_LOGIC_1164.all;`
4			`use IEEE.STD_LOGIC_UNSIGNED.all;`
5			`library WORK;`
6
7			`entity SUB_FIFO is`
8			`generic (`
9			`DATA_WIDTH : INTEGER := 12;`
10			`ADDR_WIDTH : INTEGER := 2`
11			`);`
12			`port (`
13			`rst : in STD_LOGIC;`
14			`clk : in STD_LOGIC;`
15			`rinc : in STD_LOGIC;`
16			`winc : in STD_LOGIC;`
17
18			`fullo : out STD_LOGIC;`
19			`emptyo : out STD_LOGIC;`
20			`count : out STD_LOGIC_VECTOR (ADDR_WIDTH downto 0);`
21
22			`ramwaddr : out STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);`
23			`ramenw : out STD_LOGIC;`
24			`ramraddr : out STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);`
25			`ramenr : out STD_LOGIC`
26			`);`
27			`end SUB_FIFO;`
28
29			`architecture RTL of SUB_FIFO is`
30
31			`signal raddr_reg : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);`
32			`signal waddr_reg : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);`
33			`signal count_reg : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0);`
34			`signal rd_en_reg : STD_LOGIC;`
35			`signal wr_en_reg : STD_LOGIC;`
36			`signal empty_reg : STD_LOGIC;`
37			`signal full_reg : STD_LOGIC;`
38
39			`constant ZEROS_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '0');`
40			`constant ONES_C : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');`
41
42			`begin`
43
44			`ramwaddr <= waddr_reg;`
45			`ramenw <= wr_en_reg;`
46			`ramraddr <= raddr_reg;`
47			`ramenr <= '1';`
48
49			`emptyo <= empty_reg;`
50			`fullo <= full_reg;`
51			`rd_en_reg <= (rinc and not empty_reg);`
52			`wr_en_reg <= (winc and not full_reg);`
53
54			`count <= count_reg;`
55
56			`process(clk)`
57			`begin`
58			`if clk = '1' and clk'event then`
59			`if rst = '1' then`
60			`empty_reg <= '1';`
61			`else`
62			`if count_reg = ZEROS_C or`
63			`(count_reg = 1 and rd_en_reg = '1' and wr_en_reg = '0') then`
64			`empty_reg <= '1';`
65			`else`
66			`empty_reg <= '0';`
67			`end if;`
68			`end if;`
69			`end if;`
70			`end process;`
71
72			`process(clk)`
73			`begin`
74			`if clk = '1' and clk'event then`
75			`if rst = '1' then`
76			`full_reg <= '0';`
77			`else`
78			`if count_reg = 2**ADDR_WIDTH or`
79			`(count_reg = 2**ADDR_WIDTH-1 and wr_en_reg = '1' and rd_en_reg = '0') then`
80			`full_reg <= '1';`
81			`else`
82			`full_reg <= '0';`
83			`end if;`
84			`end if;`
85			`end if;`
86			`end process;`
87
88			`process(clk)`
89			`begin`
90			`if clk = '1' and clk'event then`
91			`if rst = '1' then`
92			`raddr_reg <= (others => '0');`
93			`else`
94			`if rd_en_reg = '1' then`
95			`raddr_reg <= raddr_reg + '1';`
96			`end if;`
97			`end if;`
98			`end if;`
99			`end process;`
100
101			`process(clk)`
102			`begin`
103			`if clk = '1' and clk'event then`
104			`if rst = '1' then`
105			`waddr_reg <= (others => '0');`
106			`else`
107			`if wr_en_reg = '1' then`
108			`waddr_reg <= waddr_reg + '1';`
109			`end if;`
110			`end if;`
111			`end if;`
112			`end process;`
113
114			`process(clk)`
115			`begin`
116			`if clk = '1' and clk'event then`
117			`if rst = '1' then`
118			`count_reg <= (others => '0');`
119			`else`
120			`if (rd_en_reg = '1' and wr_en_reg = '0') or (rd_en_reg = '0' and wr_en_reg = '1') then`
121			`if rd_en_reg = '1' then`
122			`count_reg <= count_reg - '1';`
123			`else`
124			`count_reg <= count_reg + '1';`
125			`end if;`
126			`end if;`
127			`end if;`
128			`end if;`
129			`end process;`
130
131			`end RTL;`

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[/] [mkjpeg/] [trunk/] [design/] [BufFifo/] [SUB_FIFO.vhd] - Blame information for rev 40