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[/] [mkjpeg/] [trunk/] [design/] [common/] [FIFO.vhd] - Blame information for rev 66

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1 25 mikel262 
library IEEE;
2 
  use IEEE.STD_LOGIC_1164.all;
3 
  use IEEE.NUMERIC_STD.all;
4 
 
5 
entity RAMF is
6 
  generic (
7 
        RAMD_W : INTEGER := 12;
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        RAMA_W : INTEGER := 6
9 
  );
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  port (
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        d                 : in  STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
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        waddr             : in  STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
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        raddr             : in  STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
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        we                : in  STD_LOGIC;
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        clk               : in  STD_LOGIC;
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        q                 : out STD_LOGIC_VECTOR(RAMD_W-1 downto 0)
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  );
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end RAMF;
20 
 
21 
architecture RTL of RAMF is
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  type mem_type is array ((2**RAMA_W)-1 downto 0) of
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                              STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
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  signal mem                    : mem_type;
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  signal read_addr              : STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
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begin
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  -------------------------------------------------------------------------------
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  q_sg:
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  -------------------------------------------------------------------------------
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  q <= mem(TO_INTEGER(UNSIGNED(read_addr)));
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  -------------------------------------------------------------------------------
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  read_proc: -- register read address
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  -------------------------------------------------------------------------------
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  process (clk)
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  begin
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    if clk = '1' and clk'event then
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      read_addr <= raddr;
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    end if;
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  end process;
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  -------------------------------------------------------------------------------
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  write_proc: --write access
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  -------------------------------------------------------------------------------
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  process (clk) begin
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    if clk = '1' and clk'event then
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      if we = '1'  then
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        mem(TO_INTEGER(UNSIGNED(waddr))) <= d;
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      end if;
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    end if;
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  end process;
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end RTL;
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----------------------------------------------------------------------------------
57 
 
58 
library IEEE;
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  use IEEE.STD_LOGIC_1164.all;
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  use IEEE.STD_LOGIC_UNSIGNED.all;
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library WORK;
62 
 
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entity FIFO is
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  generic (
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        DATA_WIDTH         : INTEGER   := 12;
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        ADDR_WIDTH         : INTEGER   := 2
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       );
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  port (
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        rst               : in  STD_LOGIC;
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        clk               : in  STD_LOGIC;
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        rinc              : in  STD_LOGIC;
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        winc              : in  STD_LOGIC;
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        datai             : in  STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
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        datao             : out STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
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        fullo             : out STD_LOGIC;
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        emptyo            : out STD_LOGIC;
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        count             : out STD_LOGIC_VECTOR (ADDR_WIDTH downto 0)
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        );
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end FIFO;
81 
 
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architecture RTL of FIFO is
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  signal raddr_reg        : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
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  signal waddr_reg        : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
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  signal count_reg        : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0);
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  signal rd_en_reg        : STD_LOGIC;
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  signal wr_en_reg        : STD_LOGIC;
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  signal empty_reg        : STD_LOGIC;
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  signal full_reg         : STD_LOGIC;
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  signal ramq             : STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
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  signal ramd             : STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
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  signal ramwaddr         : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
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  signal ramenw           : STD_LOGIC;
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  signal ramraddr         : STD_LOGIC_VECTOR (ADDR_WIDTH-1 downto 0);
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  signal ramenr           : STD_LOGIC;
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  constant ZEROS_C        : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '0');
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  constant ONES_C         : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
100 
 
101 
  component RAMF
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  generic (
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           RAMD_W : INTEGER := 12;
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           RAMA_W : INTEGER := 6
105 
  );
106 
  port (
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        d                 : in  STD_LOGIC_VECTOR(RAMD_W-1 downto 0);
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        waddr             : in  STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
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        raddr             : in  STD_LOGIC_VECTOR(RAMA_W-1 downto 0);
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        we                : in  STD_LOGIC;
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        clk               : in  STD_LOGIC;
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        q                 : out STD_LOGIC_VECTOR(RAMD_W-1 downto 0)
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  );
115 
  end component;
116 
begin
117 
 
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  U_RAMF : RAMF
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  generic map (
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           RAMD_W => DATA_WIDTH,
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           RAMA_W => ADDR_WIDTH
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  )
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  port map (
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        d            => ramd,
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        waddr        => ramwaddr,
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        raddr        => ramraddr,
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        we           => ramenw,
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        clk          => clk,
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130 
        q            => ramq
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  );
132 
 
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  ramd                    <= datai;
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  ramwaddr                <= waddr_reg;
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  ramenw                  <= wr_en_reg;
138 
 
139 
  ramraddr                <= raddr_reg;
140 
 
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  ramenr                  <= '1';
142 
 
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  datao                   <= ramq;
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  emptyo                  <= empty_reg;
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  fullo                   <= full_reg;
148 
 
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  rd_en_reg               <= (rinc and not empty_reg);
150 
 
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  wr_en_reg               <= (winc and not full_reg);
152 
 
153 
  count <= count_reg;
154 
 
155 
  process(clk)
156 
  begin
157 
    if clk = '1' and clk'event then
158 
      if rst = '1' then
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        empty_reg         <= '1';
160 
      else
161 
        if count_reg = ZEROS_C or
162 
          (count_reg = 1 and rd_en_reg = '1' and wr_en_reg = '0') then
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          empty_reg       <= '1';
164 
        else
165 
          empty_reg       <= '0';
166 
        end if;
167 
      end if;
168 
    end if;
169 
  end process;
170 
 
171 
  process(clk)
172 
  begin
173 
    if clk = '1' and clk'event then
174 
      if rst = '1' then
175 
        full_reg          <= '0';
176 
      else
177 
        if count_reg = 2**ADDR_WIDTH or
178 
          (count_reg = 2**ADDR_WIDTH-1 and wr_en_reg = '1' and rd_en_reg = '0') then
179 
          full_reg        <= '1';
180 
        else
181 
          full_reg        <= '0';
182 
        end if;
183 
      end if;
184 
    end if;
185 
  end process;
186 
 
187 
  process(clk)
188 
  begin
189 
    if clk = '1' and clk'event then
190 
      if rst = '1' then
191 
        raddr_reg         <= (others => '0');
192 
      else
193 
        if rd_en_reg = '1' then
194 
          raddr_reg       <= raddr_reg + '1';
195 
        end if;
196 
      end if;
197 
    end if;
198 
  end process;
199 
 
200 
  process(clk)
201 
  begin
202 
    if clk = '1' and clk'event then
203 
      if rst = '1' then
204 
        waddr_reg         <= (others => '0');
205 
      else
206 
        if wr_en_reg = '1' then
207 
          waddr_reg       <= waddr_reg + '1';
208 
        end if;
209 
      end if;
210 
    end if;
211 
  end process;
212 
 
213 
  process(clk)
214 
  begin
215 
    if clk = '1' and clk'event then
216 
      if rst = '1' then
217 
        count_reg         <= (others => '0');
218 
      else
219 
        if (rd_en_reg = '1' and wr_en_reg = '0') or (rd_en_reg = '0' and wr_en_reg = '1') then
220 
          if rd_en_reg = '1' then
221 
            count_reg     <= count_reg - '1';
222 
          else
223 
            count_reg     <= count_reg + '1';
224 
          end if;
225 
        end if;
226 
      end if;
227 
    end if;
228 
  end process;
229 
 
230 
end RTL;

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