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[/] [mkjpeg/] [trunk/] [design/] [hostif/] [HostIF.vhd] - Blame information for rev 31

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1 25 mikel262
-------------------------------------------------------------------------------
2
-- File Name : HostIF.vhd
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--
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-- Project   : JPEG_ENC
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--
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-- Module    : HostIF
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--
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-- Content   : Host Interface (Xilinx OPB v2.1)
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--
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-- Description : 
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--
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-- Spec.     : 
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--
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-- Author    : Michal Krepa
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--
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-------------------------------------------------------------------------------
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-- History :
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-- 20090301: (MK): Initial Creation.
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-------------------------------------------------------------------------------
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.numeric_std.all;
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entity HostIF is
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  port
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  (
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        CLK                : in  std_logic;
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        RST                : in  std_logic;
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        -- OPB
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        OPB_ABus           : in  std_logic_vector(31 downto 0);
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        OPB_BE             : in  std_logic_vector(3 downto 0);
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        OPB_DBus_in        : in  std_logic_vector(31 downto 0);
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        OPB_RNW            : in  std_logic;
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        OPB_select         : in  std_logic;
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        OPB_DBus_out       : out std_logic_vector(31 downto 0);
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        OPB_XferAck        : out std_logic;
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        OPB_retry          : out std_logic;
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        OPB_toutSup        : out std_logic;
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        OPB_errAck         : out std_logic;
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        -- Quantizer RAM
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        qdata              : out std_logic_vector(7 downto 0);
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        qaddr              : out std_logic_vector(5 downto 0);
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        qwren              : out std_logic;
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        -- CTRL
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        jpeg_ready         : in  std_logic;
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        jpeg_busy          : in  std_logic;
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        -- ByteStuffer
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        outram_base_addr   : out std_logic_vector(9 downto 0);
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        num_enc_bytes      : in  std_logic_vector(23 downto 0);
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        -- others
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        img_size_x         : out std_logic_vector(15 downto 0);
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        img_size_y         : out std_logic_vector(15 downto 0);
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        img_size_wr        : out std_logic;
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        sof                : out std_logic;
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        cmp_max            : out std_logic_vector(1 downto 0)
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    );
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end entity HostIF;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ARCHITECTURE ------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture RTL of HostIF is
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  constant C_ENC_START_REG        : std_logic_vector(31 downto 0) := X"0000_0000";
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  constant C_IMAGE_SIZE_REG       : std_logic_vector(31 downto 0) := X"0000_0004";
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  constant C_IMAGE_RAM_ACCESS_REG : std_logic_vector(31 downto 0) := X"0000_0008";
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  constant C_ENC_STS_REG          : std_logic_vector(31 downto 0) := X"0000_000C";
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  constant C_COD_DATA_ADDR_REG    : std_logic_vector(31 downto 0) := X"0000_0010";
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  constant C_ENC_LENGTH_REG       : std_logic_vector(31 downto 0) := X"0000_0014";
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  constant C_QUANTIZER_RAM        : std_logic_vector(31 downto 0) :=
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                                      X"0000_01" & "------00";
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  constant C_IMAGE_RAM            : std_logic_vector(31 downto 0) :=
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                                      X"001" & "------------------00";
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  constant C_IMAGE_RAM_BASE : unsigned(31 downto 0) := X"0010_0000";
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  signal enc_start_reg            : std_logic_vector(31 downto 0);
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  signal image_size_reg           : std_logic_vector(31 downto 0);
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  signal image_ram_access_reg     : std_logic_vector(31 downto 0);
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  signal enc_sts_reg              : std_logic_vector(31 downto 0);
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  signal cod_data_addr_reg        : std_logic_vector(31 downto 0);
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  signal enc_length_reg           : std_logic_vector(31 downto 0);
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  signal rd_dval                  : std_logic;
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  signal data_read                : std_logic_vector(31 downto 0);
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  signal quantizer_ram_q          : std_logic_vector(31 downto 0);
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  signal image_ram_q              : std_logic_vector(31 downto 0);
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  signal write_done               : std_logic;
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  signal OPB_select_d             : std_logic;
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-------------------------------------------------------------------------------
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-- Architecture: begin
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-------------------------------------------------------------------------------
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begin
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  OPB_retry    <= '0';
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  OPB_toutSup  <= '0';
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  OPB_errAck   <= '0';
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  -- temporary!!
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  quantizer_ram_q <= (others => '0');
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  image_ram_q     <= (others => '0');
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  img_size_x <= image_size_reg(31 downto 16);
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  img_size_y <= image_size_reg(15 downto 0);
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  outram_base_addr <= cod_data_addr_reg(outram_base_addr'range);
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  cmp_max <= enc_start_reg(2 downto 1);
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  -------------------------------------------------------------------
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  -- OPB read
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  -------------------------------------------------------------------
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  p_read : process(CLK, RST)
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  begin
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    if RST = '1' then
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      OPB_DBus_out <= (others => '0');
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      rd_dval      <= '0';
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      data_read    <= (others => '0');
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    elsif CLK'event and CLK = '1' then
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      rd_dval <= '0';
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      OPB_DBus_out <= data_read;
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      if OPB_select = '1' and OPB_select_d = '0' then
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        -- only double word transactions are be supported
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        if OPB_RNW = '1' and OPB_BE = X"F" then
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          case OPB_ABus is
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            when C_ENC_START_REG =>
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              data_read <= enc_start_reg;
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              rd_dval <= '1';
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            when C_IMAGE_SIZE_REG =>
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              data_read <= image_size_reg;
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              rd_dval <= '1';
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            when C_IMAGE_RAM_ACCESS_REG =>
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              data_read <= image_ram_access_reg;
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              rd_dval <= '1';
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            when C_ENC_STS_REG =>
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              data_read <= enc_sts_reg;
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              rd_dval <= '1';
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            when C_COD_DATA_ADDR_REG =>
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              data_read <= cod_data_addr_reg;
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              rd_dval <= '1';
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            when C_ENC_LENGTH_REG =>
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              data_read <= enc_length_reg;
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              rd_dval <= '1';
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            when others =>
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              data_read <= (others => '0');
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          end case;
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        end if;
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      end if;
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    end if;
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  end process;
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  -------------------------------------------------------------------
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  -- OPB write
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  -------------------------------------------------------------------
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  p_write : process(CLK, RST)
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  begin
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    if RST = '1' then
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      qwren                <= '0';
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      write_done           <= '0';
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      enc_start_reg        <= (others => '0');
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      image_size_reg       <= (others => '0');
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      image_ram_access_reg <= (others => '0');
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      enc_sts_reg          <= (others => '0');
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      cod_data_addr_reg    <= (others => '0');
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      enc_length_reg       <= (others => '0');
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      qdata                <= (others => '0');
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      qaddr                <= (others => '0');
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      OPB_select_d         <= '0';
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      sof                  <= '0';
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      img_size_wr          <= '0';
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    elsif CLK'event and CLK = '1' then
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      qwren        <= '0';
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      write_done   <= '0';
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      sof          <= '0';
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      img_size_wr  <= '0';
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      OPB_select_d <= OPB_select;
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      if OPB_select = '1' and OPB_select_d = '0' then
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        -- only double word transactions are be supported
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        if OPB_RNW = '0' and OPB_BE = X"F" then
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          case OPB_ABus is
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            when C_ENC_START_REG =>
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              enc_start_reg <= OPB_DBus_in;
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              write_done <= '1';
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              if OPB_DBus_in(0) = '1' then
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                sof <= '1';
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              end if;
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            when C_IMAGE_SIZE_REG =>
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              image_size_reg <= OPB_DBus_in;
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              img_size_wr <= '1';
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              write_done <= '1';
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            when C_IMAGE_RAM_ACCESS_REG =>
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              image_ram_access_reg <= OPB_DBus_in;
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              write_done <= '1';
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            when C_ENC_STS_REG =>
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              enc_sts_reg <= (others => '0');
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              write_done <= '1';
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            when C_COD_DATA_ADDR_REG =>
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              cod_data_addr_reg <= OPB_DBus_in;
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              write_done <= '1';
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            when C_ENC_LENGTH_REG =>
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              --enc_length_reg <= OPB_DBus_in;
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              write_done <= '1';
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            when others =>
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              null;
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          end case;
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          if std_match(OPB_ABus, C_QUANTIZER_RAM) then
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            qdata      <= OPB_DBus_in(qdata'range);
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            qaddr      <= OPB_ABus(qaddr'high+2 downto 2);
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            qwren      <= '1';
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            write_done <= '1';
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          end if;
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        end if;
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      end if;
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      -- special handling of status reg
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      if jpeg_ready = '1' then
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        -- set jpeg done flag
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        enc_sts_reg(1) <= '1';
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      end if;
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      enc_sts_reg(0) <= jpeg_busy;
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248
      enc_length_reg <= (others => '0');
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      enc_length_reg(num_enc_bytes'range) <= num_enc_bytes;
250
 
251
    end if;
252
  end process;
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  -------------------------------------------------------------------
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  -- transfer ACK
256
  -------------------------------------------------------------------
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  p_ack : process(CLK, RST)
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  begin
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    if RST = '1' then
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      OPB_XferAck <= '0';
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    elsif CLK'event and CLK = '1' then
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      OPB_XferAck <= rd_dval or write_done;
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    end if;
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  end process;
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end architecture RTL;
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-------------------------------------------------------------------------------
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-- Architecture: end
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-------------------------------------------------------------------------------

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