OpenCores
URL https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk

Subversion Repositories mkjpeg

[/] [mkjpeg/] [trunk/] [design/] [mdct/] [DCT2D.VHD] - Blame information for rev 52

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 25 mikel262
--------------------------------------------------------------------------------
2
--                                                                            --
3
--                          V H D L    F I L E                                --
4
--                          COPYRIGHT (C) 2006                                --
5
--                                                                            --
6
--------------------------------------------------------------------------------
7
--
8
-- Title       : DCT2D
9
-- Design      : MDCT Core
10
-- Author      : Michal Krepa
11
--
12
--------------------------------------------------------------------------------
13
--
14
-- File        : DCT2D.VHD
15
-- Created     : Sat Mar 28 22:32 2006
16
--
17
--------------------------------------------------------------------------------
18
--
19
--  Description : 1D Discrete Cosine Transform (second stage)
20
--
21
--------------------------------------------------------------------------------
22
 
23
 
24
library IEEE;
25
  use IEEE.STD_LOGIC_1164.all;
26
  use ieee.numeric_std.all;
27
 
28
library WORK;
29
  use WORK.MDCT_PKG.all;
30
 
31
entity DCT2D is
32
        port(
33
      clk          : in STD_LOGIC;
34
      rst          : in std_logic;
35
      romedatao    : in T_ROM2DATAO;
36
      romodatao    : in T_ROM2DATAO;
37
      ramdatao     : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
38
      dataready    : in STD_LOGIC;
39
 
40
      odv          : out STD_LOGIC;
41
      dcto         : out std_logic_vector(OP_W-1 downto 0);
42
      romeaddro    : out T_ROM2ADDRO;
43
      romoaddro    : out T_ROM2ADDRO;
44
      ramraddro    : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
45
      rmemsel      : out STD_LOGIC;
46
      datareadyack : out STD_LOGIC
47
 
48
                );
49
end DCT2D;
50
 
51
architecture RTL of DCT2D is
52
 
53
  type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
54
 
55
  signal databuf_reg     : input_data2;
56
  signal latchbuf_reg    : input_data2;
57
  signal col_reg         : UNSIGNED(RAMADRR_W/2-1 downto 0);
58
  signal row_reg         : UNSIGNED(RAMADRR_W/2-1 downto 0);
59
  signal colram_reg      : UNSIGNED(RAMADRR_W/2-1 downto 0);
60
  signal rowram_reg      : UNSIGNED(RAMADRR_W/2-1 downto 0);
61
  signal colr_reg        : UNSIGNED(RAMADRR_W/2-1 downto 0);
62
  signal rowr_reg        : UNSIGNED(RAMADRR_W/2-1 downto 0);
63
  signal rmemsel_reg     : STD_LOGIC;
64
  signal stage1_reg      : STD_LOGIC;
65
  signal stage2_reg      : STD_LOGIC;
66
  signal stage2_cnt_reg  : UNSIGNED(RAMADRR_W-1 downto 0);
67
  signal dataready_2_reg : STD_LOGIC;
68
  signal even_not_odd    : std_logic;
69
  signal even_not_odd_d1 : std_logic;
70
  signal even_not_odd_d2 : std_logic;
71
  signal even_not_odd_d3 : std_logic;
72
  signal even_not_odd_d4 : std_logic;
73
  signal odv_d0          : std_logic;
74
  signal odv_d1          : std_logic;
75
  signal odv_d2          : std_logic;
76
  signal odv_d3          : std_logic;
77
  signal odv_d4          : std_logic;
78
  signal odv_d5          : std_logic;
79
  signal dcto_1          : std_logic_vector(DA2_W-1 downto 0);
80
  signal dcto_2          : std_logic_vector(DA2_W-1 downto 0);
81
  signal dcto_3          : std_logic_vector(DA2_W-1 downto 0);
82
  signal dcto_4          : std_logic_vector(DA2_W-1 downto 0);
83
  signal dcto_5          : std_logic_vector(DA2_W-1 downto 0);
84
  signal romedatao_d1    : T_ROM2DATAO;
85
  signal romodatao_d1    : T_ROM2DATAO;
86
  signal romedatao_d2    : T_ROM2DATAO;
87
  signal romodatao_d2    : T_ROM2DATAO;
88
  signal romedatao_d3    : T_ROM2DATAO;
89
  signal romodatao_d3    : T_ROM2DATAO;
90
  signal romedatao_d4    : T_ROM2DATAO;
91
  signal romodatao_d4    : T_ROM2DATAO;
92
begin
93
 
94
  ramraddro_sg:
95
  ramraddro  <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
96
 
97
  rmemsel_sg:
98
  rmemsel    <= rmemsel_reg;
99
 
100
  process(clk,rst)
101
  begin
102
    if rst = '1' then
103
      stage2_cnt_reg       <= (others => '1');
104
      rmemsel_reg          <= '0';
105
      stage1_reg           <= '0';
106
      stage2_reg           <= '0';
107
      colram_reg           <= (others => '0');
108
      rowram_reg           <= (others => '0');
109
      col_reg              <= (others => '0');
110
      row_reg              <= (others => '0');
111
      latchbuf_reg         <= (others => (others => '0'));
112
      databuf_reg          <= (others => (others => '0'));
113
      odv_d0               <= '0';
114
      colr_reg             <= (others => '0');
115
      rowr_reg             <= (others => '0');
116
      dataready_2_reg      <= '0';
117
    elsif clk='1' and clk'event then
118
      stage2_reg    <= '0';
119
      odv_d0        <= '0';
120
      datareadyack  <= '0';
121
      dataready_2_reg <= dataready;
122
 
123
      ----------------------------------
124
      -- read DCT 1D to barrel shifer
125
      ----------------------------------
126
      if stage1_reg = '1' then
127
 
128
        -- right shift input data
129
        latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
130
        latchbuf_reg(N-1)          <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
131
 
132
        colram_reg  <= colram_reg + 1;
133
        colr_reg    <= colr_reg + 1;
134
 
135
        if colram_reg = N-2 then
136
          rowr_reg <= rowr_reg + 1;
137
        end if;
138
 
139
        if colram_reg = N-1 then
140
          rowram_reg <= rowram_reg + 1;
141
          if rowram_reg = N-1 then
142
            stage1_reg    <= '0';
143
            colr_reg      <= (others => '0');
144
            -- release memory
145
            rmemsel_reg    <= not rmemsel_reg;
146
          end if;
147
 
148
          -- after this sum databuf_reg is in range of -256 to 254 (min to max)
149
          databuf_reg(0)  <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
150
          databuf_reg(1)  <= latchbuf_reg(2)+latchbuf_reg(7);
151
          databuf_reg(2)  <= latchbuf_reg(3)+latchbuf_reg(6);
152
          databuf_reg(3)  <= latchbuf_reg(4)+latchbuf_reg(5);
153
          databuf_reg(4)  <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
154
          databuf_reg(5)  <= latchbuf_reg(2)-latchbuf_reg(7);
155
          databuf_reg(6)  <= latchbuf_reg(3)-latchbuf_reg(6);
156
          databuf_reg(7)  <= latchbuf_reg(4)-latchbuf_reg(5);
157
 
158
          -- 8 point input latched
159
          stage2_reg      <= '1';
160
        end if;
161
      end if;
162
 
163
      --------------------------------
164
      -- 2nd stage
165
      --------------------------------
166
      if stage2_cnt_reg < N then
167
        stage2_cnt_reg <= stage2_cnt_reg + 1;
168
 
169
        -- output data valid
170
        odv_d0    <= '1';
171
 
172
        -- increment column counter
173
        col_reg   <= col_reg + 1;
174
 
175
        -- finished processing one input row
176
        if col_reg = N - 1 then
177
          row_reg         <= row_reg + 1;
178
        end if;
179
      end if;
180
 
181
      if stage2_reg = '1' then
182
        stage2_cnt_reg <= (others => '0');
183
        col_reg        <= (0=>'1',others => '0');
184
      end if;
185
      --------------------------------
186
 
187
      ----------------------------------
188
      -- wait for new data
189
      ----------------------------------
190
      -- one of ram buffers has new data, process it
191
      if dataready = '1' and dataready_2_reg = '0'  then
192
        stage1_reg    <= '1';
193
        -- to account for 1T RAM delay, increment RAM address counter
194
        colram_reg    <= (others => '0');
195
        colr_reg      <= (0=>'1',others => '0');
196
        datareadyack  <= '1';
197
      end if;
198
      ----------------------------------
199
 
200
 
201
    end if;
202
  end process;
203
 
204
  p_data_pipe : process(CLK, RST)
205
  begin
206
    if RST = '1' then
207
      even_not_odd         <= '0';
208
      even_not_odd_d1      <= '0';
209
      even_not_odd_d2      <= '0';
210
      even_not_odd_d3      <= '0';
211
      even_not_odd_d4      <= '0';
212
      odv_d1               <= '0';
213
      odv_d2               <= '0';
214
      odv_d3               <= '0';
215
      odv_d4               <= '0';
216
      odv_d5               <= '0';
217
      dcto_1               <= (others => '0');
218
      dcto_2               <= (others => '0');
219
      dcto_3               <= (others => '0');
220
      dcto_4               <= (others => '0');
221
      dcto_5               <= (others => '0');
222
    elsif CLK'event and CLK = '1' then
223
      even_not_odd    <= stage2_cnt_reg(0);
224
      even_not_odd_d1 <= even_not_odd;
225
      even_not_odd_d2 <= even_not_odd_d1;
226
      even_not_odd_d3 <= even_not_odd_d2;
227
      even_not_odd_d4 <= even_not_odd_d3;
228
      odv_d1          <= odv_d0;
229
      odv_d2          <= odv_d1;
230
      odv_d3          <= odv_d2;
231
      odv_d4          <= odv_d3;
232
      odv_d5          <= odv_d4;
233
 
234
      if even_not_odd = '0' then
235
        dcto_1 <= STD_LOGIC_VECTOR(RESIZE
236
          (RESIZE(SIGNED(romedatao(0)),DA2_W) +
237
          (RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') +
238
          (RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"),
239
          DA2_W));
240
      else
241
        dcto_1 <= STD_LOGIC_VECTOR(RESIZE
242
          (RESIZE(SIGNED(romodatao(0)),DA2_W) +
243
          (RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') +
244
          (RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"),
245
          DA2_W));
246
      end if;
247
 
248
      if even_not_odd_d1 = '0' then
249
        dcto_2 <= STD_LOGIC_VECTOR(RESIZE
250
          (signed(dcto_1) +
251
          (RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") +
252
          (RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"),
253
          DA2_W));
254
      else
255
        dcto_2 <= STD_LOGIC_VECTOR(RESIZE
256
          (signed(dcto_1) +
257
          (RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") +
258
          (RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"),
259
          DA2_W));
260
      end if;
261
 
262
      if even_not_odd_d2 = '0' then
263
        dcto_3 <= STD_LOGIC_VECTOR(RESIZE
264
          (signed(dcto_2) +
265
          (RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") +
266
          (RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"),
267
          DA2_W));
268
      else
269
        dcto_3 <= STD_LOGIC_VECTOR(RESIZE
270
          (signed(dcto_2) +
271
          (RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") +
272
          (RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"),
273
          DA2_W));
274
      end if;
275
 
276
      if even_not_odd_d3 = '0' then
277
        dcto_4 <= STD_LOGIC_VECTOR(RESIZE
278
          (signed(dcto_3) +
279
          (RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") +
280
          (RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"),
281
          DA2_W));
282
      else
283
        dcto_4 <= STD_LOGIC_VECTOR(RESIZE
284
          (signed(dcto_3) +
285
          (RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") +
286
          (RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"),
287
          DA2_W));
288
      end if;
289
 
290
      if even_not_odd_d4 = '0' then
291
        dcto_5 <= STD_LOGIC_VECTOR(RESIZE
292
          (signed(dcto_4) +
293
          (RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") -
294
          (RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"),
295
          DA2_W));
296
      else
297
        dcto_5 <= STD_LOGIC_VECTOR(RESIZE
298
          (signed(dcto_4) +
299
          (RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") -
300
          (RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"),
301
          DA2_W));
302
      end if;
303
    end if;
304
  end process;
305
 
306
  dcto <= dcto_5(DA2_W-1 downto 12);
307
  odv  <= odv_d5;
308
 
309
  p_romaddr : process(CLK, RST)
310
  begin
311
    if RST = '1' then
312
      romeaddro   <= (others => (others => '0'));
313
      romoaddro   <= (others => (others => '0'));
314
    elsif CLK'event and CLK = '1' then
315
      for i in 0 to 10 loop
316
        -- read precomputed MAC results from LUT
317
        romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
318
                 databuf_reg(0)(i) &
319
                 databuf_reg(1)(i) &
320
                 databuf_reg(2)(i) &
321
                 databuf_reg(3)(i);
322
        -- odd
323
        romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
324
                 databuf_reg(4)(i) &
325
                 databuf_reg(5)(i) &
326
                 databuf_reg(6)(i) &
327
                 databuf_reg(7)(i);
328
      end loop;
329
    end if;
330
  end process;
331
 
332
  p_romdatao_dly : process(CLK, RST)
333
  begin
334
    if RST = '1' then
335
      romedatao_d1    <= (others => (others => '0'));
336
      romodatao_d1    <= (others => (others => '0'));
337
      romedatao_d2    <= (others => (others => '0'));
338
      romodatao_d2    <= (others => (others => '0'));
339
      romedatao_d3    <= (others => (others => '0'));
340
      romodatao_d3    <= (others => (others => '0'));
341
      romedatao_d4    <= (others => (others => '0'));
342
      romodatao_d4    <= (others => (others => '0'));
343
    elsif CLK'event and CLK = '1' then
344
      romedatao_d1   <= romedatao;
345
      romodatao_d1   <= romodatao;
346
      romedatao_d2   <= romedatao_d1;
347
      romodatao_d2   <= romodatao_d1;
348
      romedatao_d3   <= romedatao_d2;
349
      romodatao_d3   <= romodatao_d2;
350
      romedatao_d4   <= romedatao_d3;
351
      romodatao_d4   <= romodatao_d3;
352
    end if;
353
  end process;
354
 
355
end RTL;
356
--------------------------------------------------------------------------------
357
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.