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[/] [mkjpeg/] [trunk/] [design/] [mdct/] [DCT2D.VHD] - Blame information for rev 67

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--------------------------------------------------------------------------------
--                                                                            --
--                          V H D L    F I L E                                --
--                          COPYRIGHT (C) 2006                                --
--                                                                            --
--------------------------------------------------------------------------------
--
-- Title       : DCT2D
-- Design      : MDCT Core
-- Author      : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File        : DCT2D.VHD
-- Created     : Sat Mar 28 22:32 2006
--
--------------------------------------------------------------------------------
--
--  Description : 1D Discrete Cosine Transform (second stage)
--
--------------------------------------------------------------------------------
 
 
library IEEE;
  use IEEE.STD_LOGIC_1164.all;
  use ieee.numeric_std.all;
 
library WORK;
  use WORK.MDCT_PKG.all;
 
entity DCT2D is
        port(
      clk          : in STD_LOGIC;
      rst          : in std_logic;
      romedatao    : in T_ROM2DATAO;
      romodatao    : in T_ROM2DATAO;
      ramdatao     : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
      dataready    : in STD_LOGIC;
 
      odv          : out STD_LOGIC;
      dcto         : out std_logic_vector(OP_W-1 downto 0);
      romeaddro    : out T_ROM2ADDRO;
      romoaddro    : out T_ROM2ADDRO;
      ramraddro    : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
      rmemsel      : out STD_LOGIC;
      datareadyack : out STD_LOGIC
 
                );
end DCT2D;
 
architecture RTL of DCT2D is
 
  type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
 
  signal databuf_reg     : input_data2;
  signal latchbuf_reg    : input_data2;
  signal col_reg         : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal row_reg         : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal colram_reg      : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal rowram_reg      : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal colr_reg        : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal rowr_reg        : UNSIGNED(RAMADRR_W/2-1 downto 0);
  signal rmemsel_reg     : STD_LOGIC;
  signal stage1_reg      : STD_LOGIC;
  signal stage2_reg      : STD_LOGIC;
  signal stage2_cnt_reg  : UNSIGNED(RAMADRR_W-1 downto 0);
  signal dataready_2_reg : STD_LOGIC;
  signal even_not_odd    : std_logic;
  signal even_not_odd_d1 : std_logic;
  signal even_not_odd_d2 : std_logic;
  signal even_not_odd_d3 : std_logic;
  signal even_not_odd_d4 : std_logic;
  signal odv_d0          : std_logic;
  signal odv_d1          : std_logic;
  signal odv_d2          : std_logic;
  signal odv_d3          : std_logic;
  signal odv_d4          : std_logic;
  signal odv_d5          : std_logic;
  signal dcto_1          : std_logic_vector(DA2_W-1 downto 0);
  signal dcto_2          : std_logic_vector(DA2_W-1 downto 0);
  signal dcto_3          : std_logic_vector(DA2_W-1 downto 0);
  signal dcto_4          : std_logic_vector(DA2_W-1 downto 0);
  signal dcto_5          : std_logic_vector(DA2_W-1 downto 0);
  signal romedatao_d1    : T_ROM2DATAO;
  signal romodatao_d1    : T_ROM2DATAO;
  signal romedatao_d2    : T_ROM2DATAO;
  signal romodatao_d2    : T_ROM2DATAO;
  signal romedatao_d3    : T_ROM2DATAO;
  signal romodatao_d3    : T_ROM2DATAO;
  signal romedatao_d4    : T_ROM2DATAO;
  signal romodatao_d4    : T_ROM2DATAO;
 
  signal odv_s  : std_logic;
  signal dcto_s : std_logic_vector(OP_W-1 downto 0);
 
component FinitePrecRndNrst is
  generic
  (
    C_IN_SZ   : natural := 37;
    C_OUT_SZ  : natural := 16;
    C_FRAC_SZ : natural := 15
  );
  port (
    CLK     : in std_logic;
    RST     : in std_logic;
    datain  : in STD_LOGIC_VECTOR(C_IN_SZ-1 downto 0);
    dataval : in std_logic;
    dataout : out STD_LOGIC_VECTOR(C_OUT_SZ-1 downto 0);
 
    clip_inc : out std_logic;
    dval_out : out std_logic
  );
end component;
 
begin
 
  ramraddro_sg:
  ramraddro  <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);
 
  rmemsel_sg:
  rmemsel    <= rmemsel_reg;
 
  process(clk,rst)
  begin
    if rst = '1' then
      stage2_cnt_reg       <= (others => '1');
      rmemsel_reg          <= '0';
      stage1_reg           <= '0';
      stage2_reg           <= '0';
      colram_reg           <= (others => '0');
      rowram_reg           <= (others => '0');
      col_reg              <= (others => '0');
      row_reg              <= (others => '0');
      latchbuf_reg         <= (others => (others => '0'));
      databuf_reg          <= (others => (others => '0'));
      odv_d0               <= '0';
      colr_reg             <= (others => '0');
      rowr_reg             <= (others => '0');
      dataready_2_reg      <= '0';
    elsif clk='1' and clk'event then
      stage2_reg    <= '0';
      odv_d0        <= '0';
      datareadyack  <= '0';
      dataready_2_reg <= dataready;
 
      ----------------------------------
      -- read DCT 1D to barrel shifer
      ----------------------------------
      if stage1_reg = '1' then
 
        -- right shift input data
        latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
        latchbuf_reg(N-1)          <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
 
        colram_reg  <= colram_reg + 1;
        colr_reg    <= colr_reg + 1;
 
        if colram_reg = N-2 then
          rowr_reg <= rowr_reg + 1;
        end if;
 
        if colram_reg = N-1 then
          rowram_reg <= rowram_reg + 1;
          if rowram_reg = N-1 then
            stage1_reg    <= '0';
            colr_reg      <= (others => '0');
            -- release memory
            rmemsel_reg    <= not rmemsel_reg;
          end if;
 
          -- after this sum databuf_reg is in range of -256 to 254 (min to max)
          databuf_reg(0)  <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
          databuf_reg(1)  <= latchbuf_reg(2)+latchbuf_reg(7);
          databuf_reg(2)  <= latchbuf_reg(3)+latchbuf_reg(6);
          databuf_reg(3)  <= latchbuf_reg(4)+latchbuf_reg(5);
          databuf_reg(4)  <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
          databuf_reg(5)  <= latchbuf_reg(2)-latchbuf_reg(7);
          databuf_reg(6)  <= latchbuf_reg(3)-latchbuf_reg(6);
          databuf_reg(7)  <= latchbuf_reg(4)-latchbuf_reg(5);
 
          -- 8 point input latched
          stage2_reg      <= '1';
        end if;
      end if;
 
      --------------------------------
      -- 2nd stage
      --------------------------------
      if stage2_cnt_reg < N then
        stage2_cnt_reg <= stage2_cnt_reg + 1;
 
        -- output data valid
        odv_d0    <= '1';
 
        -- increment column counter
        col_reg   <= col_reg + 1;
 
        -- finished processing one input row
        if col_reg = N - 1 then
          row_reg         <= row_reg + 1;
        end if;
      end if;
 
      if stage2_reg = '1' then
        stage2_cnt_reg <= (others => '0');
        col_reg        <= (0=>'1',others => '0');
      end if;
      --------------------------------
 
      ----------------------------------
      -- wait for new data
      ----------------------------------
      -- one of ram buffers has new data, process it
      if dataready = '1' and dataready_2_reg = '0'  then
        stage1_reg    <= '1';
        -- to account for 1T RAM delay, increment RAM address counter
        colram_reg    <= (others => '0');
        colr_reg      <= (0=>'1',others => '0');
        datareadyack  <= '1';
      end if;
      ----------------------------------
 
 
    end if;
  end process;
 
  p_data_pipe : process(CLK, RST)
  begin
    if RST = '1' then
      even_not_odd         <= '0';
      even_not_odd_d1      <= '0';
      even_not_odd_d2      <= '0';
      even_not_odd_d3      <= '0';
      even_not_odd_d4      <= '0';
      odv_d1               <= '0';
      odv_d2               <= '0';
      odv_d3               <= '0';
      odv_d4               <= '0';
      odv_d5               <= '0';
      dcto_1               <= (others => '0');
      dcto_2               <= (others => '0');
      dcto_3               <= (others => '0');
      dcto_4               <= (others => '0');
      dcto_5               <= (others => '0');
    elsif CLK'event and CLK = '1' then
      even_not_odd    <= stage2_cnt_reg(0);
      even_not_odd_d1 <= even_not_odd;
      even_not_odd_d2 <= even_not_odd_d1;
      even_not_odd_d3 <= even_not_odd_d2;
      even_not_odd_d4 <= even_not_odd_d3;
      odv_d1          <= odv_d0;
      odv_d2          <= odv_d1;
      odv_d3          <= odv_d2;
      odv_d4          <= odv_d3;
      odv_d5          <= odv_d4;
 
      if even_not_odd = '0' then
        dcto_1 <= STD_LOGIC_VECTOR(RESIZE
          (RESIZE(SIGNED(romedatao(0)),DA2_W) +
          (RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') +
          (RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"),
          DA2_W));
      else
        dcto_1 <= STD_LOGIC_VECTOR(RESIZE
          (RESIZE(SIGNED(romodatao(0)),DA2_W) +
          (RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') +
          (RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"),
          DA2_W));
      end if;
 
      if even_not_odd_d1 = '0' then
        dcto_2 <= STD_LOGIC_VECTOR(RESIZE
          (signed(dcto_1) +
          (RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") +
          (RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"),
          DA2_W));
      else
        dcto_2 <= STD_LOGIC_VECTOR(RESIZE
          (signed(dcto_1) +
          (RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") +
          (RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"),
          DA2_W));
      end if;
 
      if even_not_odd_d2 = '0' then
        dcto_3 <= STD_LOGIC_VECTOR(RESIZE
          (signed(dcto_2) +
          (RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") +
          (RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"),
          DA2_W));
      else
        dcto_3 <= STD_LOGIC_VECTOR(RESIZE
          (signed(dcto_2) +
          (RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") +
          (RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"),
          DA2_W));
      end if;
 
      if even_not_odd_d3 = '0' then
        dcto_4 <= STD_LOGIC_VECTOR(RESIZE
          (signed(dcto_3) +
          (RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") +
          (RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"),
          DA2_W));
      else
        dcto_4 <= STD_LOGIC_VECTOR(RESIZE
          (signed(dcto_3) +
          (RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") +
          (RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"),
          DA2_W));
      end if;
 
      if even_not_odd_d4 = '0' then
        dcto_5 <= STD_LOGIC_VECTOR(RESIZE
          (signed(dcto_4) +
          (RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") -
          (RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"),
          DA2_W));
      else
        dcto_5 <= STD_LOGIC_VECTOR(RESIZE
          (signed(dcto_4) +
          (RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") -
          (RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"),
          DA2_W));
      end if;
    end if;
  end process;
 
  dcto <= dcto_s;
  odv  <= odv_s;
 
  U_FinitePrecRndNrst : FinitePrecRndNrst
  generic map(
    C_IN_SZ  => DA2_W,
    C_OUT_SZ => DA2_W-12,
    C_FRAC_SZ => 12
  )
  port map(
    CLK         => clk,
    RST         => rst,
 
    datain      => dcto_5,
    dataval     => odv_d5,
    dataout     => dcto_s,
 
    clip_inc    => open,
    dval_out    => odv_s
  );
 
  p_romaddr : process(CLK, RST)
  begin
    if RST = '1' then
      romeaddro   <= (others => (others => '0'));
      romoaddro   <= (others => (others => '0'));
    elsif CLK'event and CLK = '1' then
      for i in 0 to 10 loop
        -- read precomputed MAC results from LUT
        romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
                 databuf_reg(0)(i) &
                 databuf_reg(1)(i) &
                 databuf_reg(2)(i) &
                 databuf_reg(3)(i);
        -- odd
        romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
                 databuf_reg(4)(i) &
                 databuf_reg(5)(i) &
                 databuf_reg(6)(i) &
                 databuf_reg(7)(i);
      end loop;
    end if;
  end process;
 
  p_romdatao_dly : process(CLK, RST)
  begin
    if RST = '1' then
      romedatao_d1    <= (others => (others => '0'));
      romodatao_d1    <= (others => (others => '0'));
      romedatao_d2    <= (others => (others => '0'));
      romodatao_d2    <= (others => (others => '0'));
      romedatao_d3    <= (others => (others => '0'));
      romodatao_d3    <= (others => (others => '0'));
      romedatao_d4    <= (others => (others => '0'));
      romodatao_d4    <= (others => (others => '0'));
    elsif CLK'event and CLK = '1' then
      romedatao_d1   <= romedatao;
      romodatao_d1   <= romodatao;
      romedatao_d2   <= romedatao_d1;
      romodatao_d2   <= romodatao_d1;
      romedatao_d3   <= romedatao_d2;
      romodatao_d3   <= romodatao_d2;
      romedatao_d4   <= romedatao_d3;
      romodatao_d4   <= romodatao_d3;
    end if;
  end process;
 
end RTL;
--------------------------------------------------------------------------------
 

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[/] [mkjpeg/] [trunk/] [design/] [mdct/] [DCT2D.VHD] - Blame information for rev 67

Line No.	Rev	Author	Line
1	67	mikel262	`--------------------------------------------------------------------------------`
2			`-- --`
3			`-- V H D L F I L E --`
4			`-- COPYRIGHT (C) 2006 --`
5			`-- --`
6			`--------------------------------------------------------------------------------`
7			`--`
8			`-- Title : DCT2D`
9			`-- Design : MDCT Core`
10			`-- Author : Michal Krepa`
11			`--`
12			`--------------------------------------------------------------------------------`
13			`--`
14			`-- File : DCT2D.VHD`
15			`-- Created : Sat Mar 28 22:32 2006`
16			`--`
17			`--------------------------------------------------------------------------------`
18			`--`
19			`-- Description : 1D Discrete Cosine Transform (second stage)`
20			`--`
21			`--------------------------------------------------------------------------------`
22
23
24			`library IEEE;`
25			`use IEEE.STD_LOGIC_1164.all;`
26			`use ieee.numeric_std.all;`
27
28			`library WORK;`
29			`use WORK.MDCT_PKG.all;`
30
31			`entity DCT2D is`
32			`port(`
33			`clk : in STD_LOGIC;`
34			`rst : in std_logic;`
35			`romedatao : in T_ROM2DATAO;`
36			`romodatao : in T_ROM2DATAO;`
37			`ramdatao : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);`
38			`dataready : in STD_LOGIC;`
39
40			`odv : out STD_LOGIC;`
41			`dcto : out std_logic_vector(OP_W-1 downto 0);`
42			`romeaddro : out T_ROM2ADDRO;`
43			`romoaddro : out T_ROM2ADDRO;`
44			`ramraddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);`
45			`rmemsel : out STD_LOGIC;`
46			`datareadyack : out STD_LOGIC`
47
48			`);`
49			`end DCT2D;`
50
51			`architecture RTL of DCT2D is`
52
53			`type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);`
54
55			`signal databuf_reg : input_data2;`
56			`signal latchbuf_reg : input_data2;`
57			`signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
58			`signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
59			`signal colram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
60			`signal rowram_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
61			`signal colr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
62			`signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);`
63			`signal rmemsel_reg : STD_LOGIC;`
64			`signal stage1_reg : STD_LOGIC;`
65			`signal stage2_reg : STD_LOGIC;`
66			`signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);`
67			`signal dataready_2_reg : STD_LOGIC;`
68			`signal even_not_odd : std_logic;`
69			`signal even_not_odd_d1 : std_logic;`
70			`signal even_not_odd_d2 : std_logic;`
71			`signal even_not_odd_d3 : std_logic;`
72			`signal even_not_odd_d4 : std_logic;`
73			`signal odv_d0 : std_logic;`
74			`signal odv_d1 : std_logic;`
75			`signal odv_d2 : std_logic;`
76			`signal odv_d3 : std_logic;`
77			`signal odv_d4 : std_logic;`
78			`signal odv_d5 : std_logic;`
79			`signal dcto_1 : std_logic_vector(DA2_W-1 downto 0);`
80			`signal dcto_2 : std_logic_vector(DA2_W-1 downto 0);`
81			`signal dcto_3 : std_logic_vector(DA2_W-1 downto 0);`
82			`signal dcto_4 : std_logic_vector(DA2_W-1 downto 0);`
83			`signal dcto_5 : std_logic_vector(DA2_W-1 downto 0);`
84			`signal romedatao_d1 : T_ROM2DATAO;`
85			`signal romodatao_d1 : T_ROM2DATAO;`
86			`signal romedatao_d2 : T_ROM2DATAO;`
87			`signal romodatao_d2 : T_ROM2DATAO;`
88			`signal romedatao_d3 : T_ROM2DATAO;`
89			`signal romodatao_d3 : T_ROM2DATAO;`
90			`signal romedatao_d4 : T_ROM2DATAO;`
91			`signal romodatao_d4 : T_ROM2DATAO;`
92
93			`signal odv_s : std_logic;`
94			`signal dcto_s : std_logic_vector(OP_W-1 downto 0);`
95
96			`component FinitePrecRndNrst is`
97			`generic`
98			`(`
99			`C_IN_SZ : natural := 37;`
100			`C_OUT_SZ : natural := 16;`
101			`C_FRAC_SZ : natural := 15`
102			`);`
103			`port (`
104			`CLK : in std_logic;`
105			`RST : in std_logic;`
106			`datain : in STD_LOGIC_VECTOR(C_IN_SZ-1 downto 0);`
107			`dataval : in std_logic;`
108			`dataout : out STD_LOGIC_VECTOR(C_OUT_SZ-1 downto 0);`
109
110			`clip_inc : out std_logic;`
111			`dval_out : out std_logic`
112			`);`
113			`end component;`
114
115			`begin`
116
117			`ramraddro_sg:`
118			`ramraddro <= STD_LOGIC_VECTOR(rowr_reg & colr_reg);`
119
120			`rmemsel_sg:`
121			`rmemsel <= rmemsel_reg;`
122
123			`process(clk,rst)`
124			`begin`
125			`if rst = '1' then`
126			`stage2_cnt_reg <= (others => '1');`
127			`rmemsel_reg <= '0';`
128			`stage1_reg <= '0';`
129			`stage2_reg <= '0';`
130			`colram_reg <= (others => '0');`
131			`rowram_reg <= (others => '0');`
132			`col_reg <= (others => '0');`
133			`row_reg <= (others => '0');`
134			`latchbuf_reg <= (others => (others => '0'));`
135			`databuf_reg <= (others => (others => '0'));`
136			`odv_d0 <= '0';`
137			`colr_reg <= (others => '0');`
138			`rowr_reg <= (others => '0');`
139			`dataready_2_reg <= '0';`
140			`elsif clk='1' and clk'event then`
141			`stage2_reg <= '0';`
142			`odv_d0 <= '0';`
143			`datareadyack <= '0';`
144			`dataready_2_reg <= dataready;`
145
146			`----------------------------------`
147			`-- read DCT 1D to barrel shifer`
148			`----------------------------------`
149			`if stage1_reg = '1' then`
150
151			`-- right shift input data`
152			`latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);`
153			`latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);`
154
155			`colram_reg <= colram_reg + 1;`
156			`colr_reg <= colr_reg + 1;`
157
158			`if colram_reg = N-2 then`
159			`rowr_reg <= rowr_reg + 1;`
160			`end if;`
161
162			`if colram_reg = N-1 then`
163			`rowram_reg <= rowram_reg + 1;`
164			`if rowram_reg = N-1 then`
165			`stage1_reg <= '0';`
166			`colr_reg <= (others => '0');`
167			`-- release memory`
168			`rmemsel_reg <= not rmemsel_reg;`
169			`end if;`
170
171			`-- after this sum databuf_reg is in range of -256 to 254 (min to max)`
172			`databuf_reg(0) <= latchbuf_reg(1)+RESIZE(SIGNED(ramdatao),RAMDATA_W+1);`
173			`databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);`
174			`databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);`
175			`databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);`
176			`databuf_reg(4) <= latchbuf_reg(1)-RESIZE(SIGNED(ramdatao),RAMDATA_W+1);`
177			`databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);`
178			`databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);`
179			`databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);`
180
181			`-- 8 point input latched`
182			`stage2_reg <= '1';`
183			`end if;`
184			`end if;`
185
186			`--------------------------------`
187			`-- 2nd stage`
188			`--------------------------------`
189			`if stage2_cnt_reg < N then`
190			`stage2_cnt_reg <= stage2_cnt_reg + 1;`
191
192			`-- output data valid`
193			`odv_d0 <= '1';`
194
195			`-- increment column counter`
196			`col_reg <= col_reg + 1;`
197
198			`-- finished processing one input row`
199			`if col_reg = N - 1 then`
200			`row_reg <= row_reg + 1;`
201			`end if;`
202			`end if;`
203
204			`if stage2_reg = '1' then`
205			`stage2_cnt_reg <= (others => '0');`
206			`col_reg <= (0=>'1',others => '0');`
207			`end if;`
208			`--------------------------------`
209
210			`----------------------------------`
211			`-- wait for new data`
212			`----------------------------------`
213			`-- one of ram buffers has new data, process it`
214			`if dataready = '1' and dataready_2_reg = '0' then`
215			`stage1_reg <= '1';`
216			`-- to account for 1T RAM delay, increment RAM address counter`
217			`colram_reg <= (others => '0');`
218			`colr_reg <= (0=>'1',others => '0');`
219			`datareadyack <= '1';`
220			`end if;`
221			`----------------------------------`
222
223
224			`end if;`
225			`end process;`
226
227			`p_data_pipe : process(CLK, RST)`
228			`begin`
229			`if RST = '1' then`
230			`even_not_odd <= '0';`
231			`even_not_odd_d1 <= '0';`
232			`even_not_odd_d2 <= '0';`
233			`even_not_odd_d3 <= '0';`
234			`even_not_odd_d4 <= '0';`
235			`odv_d1 <= '0';`
236			`odv_d2 <= '0';`
237			`odv_d3 <= '0';`
238			`odv_d4 <= '0';`
239			`odv_d5 <= '0';`
240			`dcto_1 <= (others => '0');`
241			`dcto_2 <= (others => '0');`
242			`dcto_3 <= (others => '0');`
243			`dcto_4 <= (others => '0');`
244			`dcto_5 <= (others => '0');`
245			`elsif CLK'event and CLK = '1' then`
246			`even_not_odd <= stage2_cnt_reg(0);`
247			`even_not_odd_d1 <= even_not_odd;`
248			`even_not_odd_d2 <= even_not_odd_d1;`
249			`even_not_odd_d3 <= even_not_odd_d2;`
250			`even_not_odd_d4 <= even_not_odd_d3;`
251			`odv_d1 <= odv_d0;`
252			`odv_d2 <= odv_d1;`
253			`odv_d3 <= odv_d2;`
254			`odv_d4 <= odv_d3;`
255			`odv_d5 <= odv_d4;`
256
257			`if even_not_odd = '0' then`
258			`dcto_1 <= STD_LOGIC_VECTOR(RESIZE`
259			`(RESIZE(SIGNED(romedatao(0)),DA2_W) +`
260			`(RESIZE(SIGNED(romedatao(1)),DA2_W-1) & '0') +`
261			`(RESIZE(SIGNED(romedatao(2)),DA2_W-2) & "00"),`
262			`DA2_W));`
263			`else`
264			`dcto_1 <= STD_LOGIC_VECTOR(RESIZE`
265			`(RESIZE(SIGNED(romodatao(0)),DA2_W) +`
266			`(RESIZE(SIGNED(romodatao(1)),DA2_W-1) & '0') +`
267			`(RESIZE(SIGNED(romodatao(2)),DA2_W-2) & "00"),`
268			`DA2_W));`
269			`end if;`
270
271			`if even_not_odd_d1 = '0' then`
272			`dcto_2 <= STD_LOGIC_VECTOR(RESIZE`
273			`(signed(dcto_1) +`
274			`(RESIZE(SIGNED(romedatao_d1(3)),DA2_W-3) & "000") +`
275			`(RESIZE(SIGNED(romedatao_d1(4)),DA2_W-4) & "0000"),`
276			`DA2_W));`
277			`else`
278			`dcto_2 <= STD_LOGIC_VECTOR(RESIZE`
279			`(signed(dcto_1) +`
280			`(RESIZE(SIGNED(romodatao_d1(3)),DA2_W-3) & "000") +`
281			`(RESIZE(SIGNED(romodatao_d1(4)),DA2_W-4) & "0000"),`
282			`DA2_W));`
283			`end if;`
284
285			`if even_not_odd_d2 = '0' then`
286			`dcto_3 <= STD_LOGIC_VECTOR(RESIZE`
287			`(signed(dcto_2) +`
288			`(RESIZE(SIGNED(romedatao_d2(5)),DA2_W-5) & "00000") +`
289			`(RESIZE(SIGNED(romedatao_d2(6)),DA2_W-6) & "000000"),`
290			`DA2_W));`
291			`else`
292			`dcto_3 <= STD_LOGIC_VECTOR(RESIZE`
293			`(signed(dcto_2) +`
294			`(RESIZE(SIGNED(romodatao_d2(5)),DA2_W-5) & "00000") +`
295			`(RESIZE(SIGNED(romodatao_d2(6)),DA2_W-6) & "000000"),`
296			`DA2_W));`
297			`end if;`
298
299			`if even_not_odd_d3 = '0' then`
300			`dcto_4 <= STD_LOGIC_VECTOR(RESIZE`
301			`(signed(dcto_3) +`
302			`(RESIZE(SIGNED(romedatao_d3(7)),DA2_W-7) & "0000000") +`
303			`(RESIZE(SIGNED(romedatao_d3(8)),DA2_W-8) & "00000000"),`
304			`DA2_W));`
305			`else`
306			`dcto_4 <= STD_LOGIC_VECTOR(RESIZE`
307			`(signed(dcto_3) +`
308			`(RESIZE(SIGNED(romodatao_d3(7)),DA2_W-7) & "0000000") +`
309			`(RESIZE(SIGNED(romodatao_d3(8)),DA2_W-8) & "00000000"),`
310			`DA2_W));`
311			`end if;`
312
313			`if even_not_odd_d4 = '0' then`
314			`dcto_5 <= STD_LOGIC_VECTOR(RESIZE`
315			`(signed(dcto_4) +`
316			`(RESIZE(SIGNED(romedatao_d4(9)),DA2_W-9) & "000000000") -`
317			`(RESIZE(SIGNED(romedatao_d4(10)),DA2_W-10) & "0000000000"),`
318			`DA2_W));`
319			`else`
320			`dcto_5 <= STD_LOGIC_VECTOR(RESIZE`
321			`(signed(dcto_4) +`
322			`(RESIZE(SIGNED(romodatao_d4(9)),DA2_W-9) & "000000000") -`
323			`(RESIZE(SIGNED(romodatao_d4(10)),DA2_W-10) & "0000000000"),`
324			`DA2_W));`
325			`end if;`
326			`end if;`
327			`end process;`
328
329			`dcto <= dcto_s;`
330			`odv <= odv_s;`
331
332			`U_FinitePrecRndNrst : FinitePrecRndNrst`
333			`generic map(`
334			`C_IN_SZ => DA2_W,`
335			`C_OUT_SZ => DA2_W-12,`
336			`C_FRAC_SZ => 12`
337			`)`
338			`port map(`
339			`CLK => clk,`
340			`RST => rst,`
341
342			`datain => dcto_5,`
343			`dataval => odv_d5,`
344			`dataout => dcto_s,`
345
346			`clip_inc => open,`
347			`dval_out => odv_s`
348			`);`
349
350			`p_romaddr : process(CLK, RST)`
351			`begin`
352			`if RST = '1' then`
353			`romeaddro <= (others => (others => '0'));`
354			`romoaddro <= (others => (others => '0'));`
355			`elsif CLK'event and CLK = '1' then`
356			`for i in 0 to 10 loop`
357			`-- read precomputed MAC results from LUT`
358			`romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
359			`databuf_reg(0)(i) &`
360			`databuf_reg(1)(i) &`
361			`databuf_reg(2)(i) &`
362			`databuf_reg(3)(i);`
363			`-- odd`
364			`romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &`
365			`databuf_reg(4)(i) &`
366			`databuf_reg(5)(i) &`
367			`databuf_reg(6)(i) &`
368			`databuf_reg(7)(i);`
369			`end loop;`
370			`end if;`
371			`end process;`
372
373			`p_romdatao_dly : process(CLK, RST)`
374			`begin`
375			`if RST = '1' then`
376			`romedatao_d1 <= (others => (others => '0'));`
377			`romodatao_d1 <= (others => (others => '0'));`
378			`romedatao_d2 <= (others => (others => '0'));`
379			`romodatao_d2 <= (others => (others => '0'));`
380			`romedatao_d3 <= (others => (others => '0'));`
381			`romodatao_d3 <= (others => (others => '0'));`
382			`romedatao_d4 <= (others => (others => '0'));`
383			`romodatao_d4 <= (others => (others => '0'));`
384			`elsif CLK'event and CLK = '1' then`
385			`romedatao_d1 <= romedatao;`
386			`romodatao_d1 <= romodatao;`
387			`romedatao_d2 <= romedatao_d1;`
388			`romodatao_d2 <= romodatao_d1;`
389			`romedatao_d3 <= romedatao_d2;`
390			`romodatao_d3 <= romodatao_d2;`
391			`romedatao_d4 <= romedatao_d3;`
392			`romodatao_d4 <= romodatao_d3;`
393			`end if;`
394			`end process;`
395
396			`end RTL;`
397			`--------------------------------------------------------------------------------`
398