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[/] [mkjpeg/] [trunk/] [design/] [mdct/] [FDCT.vhd] - Blame information for rev 63

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1 25 mikel262
-------------------------------------------------------------------------------
2
-- File Name :  FDCT.vhd
3
--
4
-- Project   : JPEG_ENC
5
--
6
-- Module    : FDCT
7
--
8
-- Content   : FDCT
9
--
10
-- Description : 2D Discrete Cosine Transform
11
--
12
-- Spec.     : 
13
--
14
-- Author    : Michal Krepa
15
--
16
-------------------------------------------------------------------------------
17
-- History :
18
-- 20090301: (MK): Initial Creation.
19
-------------------------------------------------------------------------------
20
 
21
-------------------------------------------------------------------------------
22
-------------------------------------------------------------------------------
23
----------------------------------- LIBRARY/PACKAGE ---------------------------
24
-------------------------------------------------------------------------------
25
-------------------------------------------------------------------------------
26
 
27
-------------------------------------------------------------------------------
28
-- generic packages/libraries:
29
-------------------------------------------------------------------------------
30
library ieee;
31
  use ieee.std_logic_1164.all;
32
  use ieee.numeric_std.all;
33
 
34
-------------------------------------------------------------------------------
35
-- user packages/libraries:
36
-------------------------------------------------------------------------------
37
library work;
38
  use work.JPEG_PKG.all;
39
-------------------------------------------------------------------------------
40
-------------------------------------------------------------------------------
41
----------------------------------- ENTITY ------------------------------------
42
-------------------------------------------------------------------------------
43
-------------------------------------------------------------------------------
44
entity FDCT is
45
  port
46
  (
47
        CLK                : in  std_logic;
48
        RST                : in  std_logic;
49
        -- CTRL
50
        start_pb           : in  std_logic;
51
        ready_pb           : out std_logic;
52
        fdct_sm_settings   : in  T_SM_SETTINGS;
53
 
54
        -- BUF_FIFO
55
        bf_fifo_rd         : out std_logic;
56
        bf_fifo_q          : in  std_logic_vector(23 downto 0);
57
        bf_fifo_hf_full    : in  std_logic;
58
 
59
        -- ZIG ZAG
60
        zz_buf_sel         : in  std_logic;
61
        zz_rd_addr         : in  std_logic_vector(5 downto 0);
62
        zz_data            : out std_logic_vector(11 downto 0);
63
        zz_rden            : in  std_logic;
64
 
65
        -- HOST
66
        img_size_x         : in  std_logic_vector(15 downto 0);
67
        img_size_y         : in  std_logic_vector(15 downto 0);
68
        sof                : in  std_logic
69
    );
70
end entity FDCT;
71
 
72
-------------------------------------------------------------------------------
73
-------------------------------------------------------------------------------
74
----------------------------------- ARCHITECTURE ------------------------------
75
-------------------------------------------------------------------------------
76
-------------------------------------------------------------------------------
77
architecture RTL of FDCT is
78
 
79
  constant C_Y_1       : signed(14 downto 0) := to_signed(4899,  15);
80
  constant C_Y_2       : signed(14 downto 0) := to_signed(9617,  15);
81
  constant C_Y_3       : signed(14 downto 0) := to_signed(1868,  15);
82
  constant C_Cb_1      : signed(14 downto 0) := to_signed(-2764, 15);
83
  constant C_Cb_2      : signed(14 downto 0) := to_signed(-5428, 15);
84
  constant C_Cb_3      : signed(14 downto 0) := to_signed(8192,  15);
85
  constant C_Cr_1      : signed(14 downto 0) := to_signed(8192,  15);
86
  constant C_Cr_2      : signed(14 downto 0) := to_signed(-6860, 15);
87
  constant C_Cr_3      : signed(14 downto 0) := to_signed(-1332, 15);
88
 
89
 
90
  signal mdct_data_in      : std_logic_vector(7 downto 0);
91
  signal mdct_idval        : std_logic;
92
  signal mdct_odval        : std_logic;
93
  signal mdct_data_out     : std_logic_vector(11 downto 0);
94
  signal odv1              : std_logic;
95
  signal dcto1             : std_logic_vector(11 downto 0);
96 52 mikel262
  signal x_pixel_cnt       : unsigned(15 downto 0);
97
  signal y_line_cnt        : unsigned(15 downto 0);
98 25 mikel262
  signal rd_addr           : std_logic_vector(31 downto 0);
99 61 mikel262
  signal input_rd_cnt      : unsigned(6 downto 0);
100 25 mikel262
  signal rd_en             : std_logic;
101
  signal rd_en_d1          : std_logic;
102
  signal rdaddr            : unsigned(31 downto 0);
103 52 mikel262
  signal bf_dval           : std_logic;
104
  signal bf_dval_m1        : std_logic;
105
  signal bf_dval_m2        : std_logic;
106 56 mikel262
  signal bf_dval_m3        : std_logic;
107 25 mikel262
  signal wr_cnt            : unsigned(5 downto 0);
108
  signal dbuf_data         : std_logic_vector(11 downto 0);
109
  signal dbuf_q            : std_logic_vector(11 downto 0);
110
  signal dbuf_we           : std_logic;
111
  signal dbuf_waddr        : std_logic_vector(6 downto 0);
112
  signal dbuf_raddr        : std_logic_vector(6 downto 0);
113
  signal xw_cnt            : unsigned(2 downto 0);
114
  signal yw_cnt            : unsigned(2 downto 0);
115
 
116
  signal dbuf_q_z1         : std_logic_vector(11 downto 0);
117
  constant C_SIMA_ASZ      : integer := 9;
118
  signal sim_rd_addr       : unsigned(C_SIMA_ASZ-1 downto 0);
119
  signal Y_reg_1           : signed(23 downto 0);
120
  signal Y_reg_2           : signed(23 downto 0);
121
  signal Y_reg_3           : signed(23 downto 0);
122
  signal Cb_reg_1          : signed(23 downto 0);
123
  signal Cb_reg_2          : signed(23 downto 0);
124
  signal Cb_reg_3          : signed(23 downto 0);
125
  signal Cr_reg_1          : signed(23 downto 0);
126
  signal Cr_reg_2          : signed(23 downto 0);
127
  signal Cr_reg_3          : signed(23 downto 0);
128
  signal Y_reg             : signed(23 downto 0);
129
  signal Cb_reg            : signed(23 downto 0);
130
  signal Cr_reg            : signed(23 downto 0);
131
  signal R_s               : signed(8 downto 0);
132
  signal G_s               : signed(8 downto 0);
133
  signal B_s               : signed(8 downto 0);
134
  signal Y_8bit            : unsigned(7 downto 0);
135
  signal Cb_8bit           : unsigned(7 downto 0);
136
  signal Cr_8bit           : unsigned(7 downto 0);
137 61 mikel262
  signal cmp_idx           : unsigned(2 downto 0);
138
  signal cur_cmp_idx       : unsigned(2 downto 0);
139
  signal cur_cmp_idx_d1    : unsigned(2 downto 0);
140
  signal cur_cmp_idx_d2    : unsigned(2 downto 0);
141
  signal cur_cmp_idx_d3    : unsigned(2 downto 0);
142
  signal cur_cmp_idx_d4    : unsigned(2 downto 0);
143
  signal cur_cmp_idx_d5    : unsigned(2 downto 0);
144
  signal cur_cmp_idx_d6    : unsigned(2 downto 0);
145
  signal cur_cmp_idx_d7    : unsigned(2 downto 0);
146
  signal cur_cmp_idx_d8    : unsigned(2 downto 0);
147
  signal cur_cmp_idx_d9    : unsigned(2 downto 0);
148 25 mikel262
  signal fifo1_rd          : std_logic;
149
  signal fifo1_wr          : std_logic;
150
  signal fifo1_q           : std_logic_vector(11 downto 0);
151
  signal fifo1_full        : std_logic;
152
  signal fifo1_empty       : std_logic;
153 61 mikel262
  signal fifo1_count       : std_logic_vector(9 downto 0);
154 25 mikel262
  signal fifo1_rd_cnt      : unsigned(5 downto 0);
155
  signal fifo1_q_dval      : std_logic;
156
  signal fifo_data_in      : std_logic_vector(11 downto 0);
157
  signal fifo_rd_arm       : std_logic;
158
 
159
  signal eoi_fdct          : std_logic;
160 61 mikel262
  signal bf_fifo_rd_s      : std_logic;
161 25 mikel262
  signal start_int         : std_logic;
162 61 mikel262
  signal start_int_d       : std_logic_vector(4 downto 0);
163 25 mikel262
 
164
  signal fram1_data        : std_logic_vector(23 downto 0);
165
  signal fram1_q           : std_logic_vector(23 downto 0);
166
  signal fram1_we          : std_logic;
167 61 mikel262
  signal fram1_waddr       : std_logic_vector(6 downto 0);
168
  signal fram1_raddr       : std_logic_vector(6 downto 0);
169 28 mikel262
  signal fram1_rd_d        : std_logic_vector(8 downto 0);
170 25 mikel262
  signal fram1_rd          : std_logic;
171
  signal rd_started        : std_logic;
172
  signal writing_en        : std_logic;
173 61 mikel262
  signal fram1_q_vld       : std_logic;
174 25 mikel262
 
175 61 mikel262
  signal fram1_line_cnt    : unsigned(2 downto 0);
176
  signal fram1_pix_cnt     : unsigned(2 downto 0);
177
 
178
 
179 25 mikel262
-------------------------------------------------------------------------------
180
-- Architecture: begin
181
-------------------------------------------------------------------------------
182
begin
183
 
184
  zz_data      <= dbuf_q;
185
 
186
  bf_fifo_rd   <= bf_fifo_rd_s;
187
 
188
  -------------------------------------------------------------------
189
  -- FRAM1
190
  -------------------------------------------------------------------
191
  U_FRAM1 : entity work.RAMZ
192
  generic map
193
  (
194 61 mikel262
      RAMADDR_W     => 7,
195 25 mikel262
      RAMDATA_W     => 24
196
  )
197
  port map
198
  (
199
        d           => fram1_data,
200
        waddr       => fram1_waddr,
201
        raddr       => fram1_raddr,
202
        we          => fram1_we,
203
        clk         => CLK,
204
 
205
        q           => fram1_q
206
  );
207
 
208 52 mikel262
  fram1_we   <= bf_dval;
209 25 mikel262
  fram1_data <= bf_fifo_q;
210
 
211 61 mikel262
  fram1_q_vld <= fram1_rd_d(5);
212
 
213 25 mikel262
  -------------------------------------------------------------------
214
  -- FRAM1 process
215
  -------------------------------------------------------------------
216
  p_fram1_acc : process(CLK, RST)
217
  begin
218
    if RST = '1' then
219
      fram1_waddr <= (others => '0');
220
    elsif CLK'event and CLK = '1' then
221
      if fram1_we = '1' then
222
        fram1_waddr <= std_logic_vector(unsigned(fram1_waddr) + 1);
223
      end if;
224
    end if;
225
  end process;
226
 
227
  -------------------------------------------------------------------
228
  -- IRAM read process 
229
  -------------------------------------------------------------------
230
  p_counter1 : process(CLK, RST)
231
  begin
232
    if RST = '1' then
233
      rd_en           <= '0';
234
      rd_en_d1        <= '0';
235 52 mikel262
      x_pixel_cnt     <= (others => '0');
236
      y_line_cnt     <= (others => '0');
237 25 mikel262
      input_rd_cnt    <= (others => '0');
238
      cmp_idx         <= (others => '0');
239
      cur_cmp_idx     <= (others => '0');
240
      cur_cmp_idx_d1  <= (others => '0');
241
      cur_cmp_idx_d2  <= (others => '0');
242
      cur_cmp_idx_d3  <= (others => '0');
243
      cur_cmp_idx_d4  <= (others => '0');
244
      cur_cmp_idx_d5  <= (others => '0');
245
      cur_cmp_idx_d6  <= (others => '0');
246
      cur_cmp_idx_d7  <= (others => '0');
247
      cur_cmp_idx_d8  <= (others => '0');
248
      cur_cmp_idx_d9  <= (others => '0');
249
      eoi_fdct        <= '0';
250
      start_int       <= '0';
251
      bf_fifo_rd_s    <= '0';
252 52 mikel262
      bf_dval         <= '0';
253
      bf_dval_m1      <= '0';
254
      bf_dval_m2      <= '0';
255 25 mikel262
      fram1_rd        <= '0';
256
      fram1_rd_d      <= (others => '0');
257 61 mikel262
      start_int_d     <= (others => '0');
258 25 mikel262
      fram1_raddr     <= (others => '0');
259 61 mikel262
      fram1_line_cnt  <= (others => '0');
260
      fram1_pix_cnt   <= (others => '0');
261 25 mikel262
    elsif CLK'event and CLK = '1' then
262
      rd_en_d1 <= rd_en;
263
      cur_cmp_idx_d1 <= cur_cmp_idx;
264
      cur_cmp_idx_d2 <= cur_cmp_idx_d1;
265
      cur_cmp_idx_d3 <= cur_cmp_idx_d2;
266
      cur_cmp_idx_d4 <= cur_cmp_idx_d3;
267
      cur_cmp_idx_d5 <= cur_cmp_idx_d4;
268
      cur_cmp_idx_d6 <= cur_cmp_idx_d5;
269
      cur_cmp_idx_d7 <= cur_cmp_idx_d6;
270
      cur_cmp_idx_d8 <= cur_cmp_idx_d7;
271
      cur_cmp_idx_d9 <= cur_cmp_idx_d8;
272
      start_int      <= '0';
273
 
274 56 mikel262
      bf_dval_m3     <= bf_fifo_rd_s;
275
      bf_dval_m2     <= bf_dval_m3;
276 52 mikel262
      bf_dval_m1     <= bf_dval_m2;
277
      bf_dval        <= bf_dval_m1;
278 56 mikel262
 
279 25 mikel262
      fram1_rd_d     <= fram1_rd_d(fram1_rd_d'length-2 downto 0) & fram1_rd;
280 61 mikel262
      start_int_d    <= start_int_d(start_int_d'length-2 downto 0) & start_int;
281 25 mikel262
 
282
      -- SOF or internal self-start
283
      if (sof = '1' or start_int = '1') then
284
        input_rd_cnt <= (others => '0');
285
        -- enable BUF_FIFO/FRAM1 reading
286 61 mikel262
        rd_started      <= '1';
287 25 mikel262
 
288
        -- component index
289 61 mikel262
        if cmp_idx = 4-1 then
290 25 mikel262
          cmp_idx <= (others => '0');
291
          -- horizontal block counter
292 61 mikel262
          if x_pixel_cnt = unsigned(img_size_x)-16 then
293 52 mikel262
            x_pixel_cnt <= (others => '0');
294 25 mikel262
            -- vertical block counter
295 52 mikel262
            if y_line_cnt = unsigned(img_size_y)-8 then
296
              y_line_cnt <= (others => '0');
297
              -- set end of image flag
298 25 mikel262
              eoi_fdct <= '1';
299
            else
300 52 mikel262
              y_line_cnt <= y_line_cnt + 8;
301 25 mikel262
            end if;
302
          else
303 61 mikel262
            x_pixel_cnt <= x_pixel_cnt + 16;
304 25 mikel262
          end if;
305
        else
306
          cmp_idx <=cmp_idx + 1;
307
        end if;
308
 
309
        cur_cmp_idx     <= cmp_idx;
310 61 mikel262
 
311 25 mikel262
      end if;
312
 
313 52 mikel262
      -- wait until FIFO becomes half full but only for component 0
314
      -- as we read buf FIFO only during component 0
315 61 mikel262
      if rd_started = '1' and (bf_fifo_hf_full = '1' or cur_cmp_idx > 1) then
316 25 mikel262
        rd_en      <= '1';
317
        rd_started <= '0';
318
      end if;
319
 
320
      bf_fifo_rd_s   <= '0';
321
      fram1_rd       <= '0';
322
      -- stall reading from input FIFO and writing to output FIFO 
323
      -- when output FIFO is almost full
324 61 mikel262
      if rd_en = '1' and unsigned(fifo1_count) < 512-64 and
325
         (bf_fifo_hf_full = '1' or cur_cmp_idx > 1) then
326 25 mikel262
        -- read request goes to BUF_FIFO only for component 0. 
327 61 mikel262
        if cur_cmp_idx < 2 then
328 25 mikel262
          bf_fifo_rd_s <= '1';
329
        end if;
330
 
331
        -- count number of samples read from input in one run
332
        if input_rd_cnt = 64-1 then
333
          rd_en        <= '0';
334 52 mikel262
          -- internal restart
335 25 mikel262
          start_int    <= '1' and not eoi_fdct;
336
          eoi_fdct     <= '0';
337
        else
338
          input_rd_cnt <= input_rd_cnt + 1;
339
        end if;
340
        -- FRAM read enable
341
        fram1_rd <= '1';
342
      end if;
343
 
344 61 mikel262
      -- increment FRAM1 read address according to subsampling
345
      -- idea is to extract 8x8 from 16x8 block
346
      -- there are two luminance blocks left and right
347
      -- there is 2:1 subsampled Cb block
348
      -- there is 2:1 subsampled Cr block
349
      -- subsampling done as simple decimation by 2 wo/ averaging
350
      if sof = '1' then
351
        fram1_raddr     <= (others => '0');
352
        fram1_line_cnt  <= (others => '0');
353
        fram1_pix_cnt   <= (others => '0');
354
      elsif start_int_d(4) = '1' then
355
        fram1_line_cnt  <= (others => '0');
356
        fram1_pix_cnt   <= (others => '0');
357
        case cur_cmp_idx_d4 is
358
          -- Y1, Cr, Cb
359
          when "000" | "010" | "011" =>
360
            fram1_raddr <= (others => '0');
361
          -- Y2
362
          when "001" =>
363
            fram1_raddr <= std_logic_vector(to_unsigned(64, fram1_raddr'length));
364
          when others =>
365
            null;
366
        end case;
367
      elsif fram1_rd_d(4) = '1' then
368
 
369
        if fram1_pix_cnt = 8-1 then
370
          fram1_pix_cnt <= (others => '0');
371
          if fram1_line_cnt = 8-1 then
372
            fram1_line_cnt <= (others => '0');
373
          else
374
            fram1_line_cnt <= fram1_line_cnt + 1;
375
          end if;
376
        else
377
          fram1_pix_cnt <= fram1_pix_cnt + 1;
378
        end if;
379
 
380
        case cur_cmp_idx_d6 is
381
          when "000" | "001" =>
382
            fram1_raddr <= std_logic_vector(unsigned(fram1_raddr) + 1);
383
          when "010" | "011" =>
384
            if fram1_pix_cnt = 4-1 then
385
              fram1_raddr <= std_logic_vector('1' & fram1_line_cnt & "000");
386
            elsif fram1_pix_cnt = 8-1 then
387
              if fram1_line_cnt = 8-1 then
388
                fram1_raddr <= '0' & "000" & "000";
389
              else
390
                fram1_raddr <= std_logic_vector('0' & (fram1_line_cnt+1) & "000");
391
              end if;
392
            else
393
              fram1_raddr <= std_logic_vector(unsigned(fram1_raddr) + 2);
394
            end if;
395
          when others =>
396
            null;
397
        end case;
398
 
399 25 mikel262
      end if;
400
 
401
    end if;
402
  end process;
403
 
404
  -------------------------------------------------------------------
405
  -- FDCT with input level shift
406
  -------------------------------------------------------------------
407
  U_MDCT : entity work.MDCT
408
        port map
409
  (
410
                clk          => CLK,
411
                rst          => RST,
412
    dcti         => mdct_data_in,
413
    idv          => mdct_idval,
414
    odv          => mdct_odval,
415
    dcto         => mdct_data_out,
416
    odv1         => odv1,
417
    dcto1        => dcto1
418
        );
419
 
420 28 mikel262
  mdct_idval   <= fram1_rd_d(8);
421 25 mikel262
 
422
  R_s <= signed('0' & fram1_q(7 downto 0));
423
  G_s <= signed('0' & fram1_q(15 downto 8));
424
  B_s <= signed('0' & fram1_q(23 downto 16));
425
 
426
  -------------------------------------------------------------------
427
  -- Mux1
428
  -------------------------------------------------------------------
429
  p_mux1 : process(CLK, RST)
430
  begin
431
    if RST = '1' then
432
      mdct_data_in <= (others => '0');
433
    elsif CLK'event and CLK = '1' then
434
      case cur_cmp_idx_d9 is
435 61 mikel262
        when "000" | "001" =>
436 25 mikel262
          mdct_data_in <= std_logic_vector(Y_8bit);
437 61 mikel262
        when "010" =>
438 25 mikel262
          mdct_data_in <= std_logic_vector(Cb_8bit);
439 61 mikel262
        when "011" =>
440 25 mikel262
          mdct_data_in <= std_logic_vector(Cr_8bit);
441
        when others =>
442
          null;
443
      end case;
444
    end if;
445
  end process;
446
 
447
 
448
  -------------------------------------------------------------------
449
  -- FIFO1
450
  -------------------------------------------------------------------
451
  U_FIFO1 : entity work.FIFO
452
  generic map
453
  (
454
        DATA_WIDTH        => 12,
455 61 mikel262
        ADDR_WIDTH        => 9
456 25 mikel262
  )
457
  port map
458
  (
459
        rst               => RST,
460
        clk               => CLK,
461
        rinc              => fifo1_rd,
462
        winc              => fifo1_wr,
463
        datai             => fifo_data_in,
464
 
465
        datao             => fifo1_q,
466
        fullo             => fifo1_full,
467
        emptyo            => fifo1_empty,
468
        count             => fifo1_count
469
  );
470
 
471
  fifo1_wr     <= mdct_odval;
472
  fifo_data_in <= mdct_data_out;
473
 
474
 
475
 
476
  -------------------------------------------------------------------
477 52 mikel262
  -- FIFO1 rd controller
478 25 mikel262
  -------------------------------------------------------------------
479
  p_fifo_rd_ctrl : process(CLK, RST)
480
  begin
481
    if RST = '1' then
482
      fifo1_rd     <= '0';
483
      fifo_rd_arm  <= '0';
484
      fifo1_rd_cnt <= (others => '0');
485
      fifo1_q_dval <= '0';
486
    elsif CLK'event and CLK = '1' then
487
      fifo1_rd     <= '0';
488
 
489
      fifo1_q_dval <= fifo1_rd;
490
 
491
      if start_pb = '1' then
492
        fifo_rd_arm  <= '1';
493
        fifo1_rd_cnt <= (others => '0');
494
      end if;
495
 
496
      if fifo_rd_arm = '1' then
497
 
498
        if fifo1_rd_cnt = 64-1 then
499
          fifo_rd_arm  <= '0';
500
          fifo1_rd     <= '1';
501
        elsif fifo1_empty = '0' then
502
          fifo1_rd     <= '1';
503
          fifo1_rd_cnt <= fifo1_rd_cnt + 1;
504
        end if;
505
 
506
      end if;
507
    end if;
508
  end process;
509
 
510
  -------------------------------------------------------------------
511
  -- write counter
512
  -------------------------------------------------------------------
513
  p_wr_cnt : process(CLK, RST)
514
  begin
515
    if RST = '1' then
516
      wr_cnt   <= (others => '0');
517
      ready_pb <= '0';
518
      xw_cnt   <= (others => '0');
519
      yw_cnt   <= (others => '0');
520
      writing_en <= '0';
521
    elsif CLK'event and CLK = '1' then
522
      ready_pb <= '0';
523
 
524
      if start_pb = '1' then
525
        wr_cnt <= (others => '0');
526
        xw_cnt <= (others => '0');
527
        yw_cnt <= (others => '0');
528
        writing_en  <= '1';
529
      end if;
530
 
531
      if writing_en = '1' then
532
        if fifo1_q_dval = '1' then
533
          if wr_cnt = 64-1 then
534
            wr_cnt <= (others => '0');
535
            ready_pb <= '1';
536
            writing_en <= '0';
537
          else
538
            wr_cnt <= wr_cnt + 1;
539
          end if;
540
 
541
          if yw_cnt = 8-1 then
542
            yw_cnt <= (others => '0');
543
            xw_cnt <= xw_cnt+1;
544
          else
545
            yw_cnt <= yw_cnt+1;
546
          end if;
547
        end if;
548
      end if;
549
    end if;
550
  end process;
551
 
552
  -------------------------------------------------------------------
553
  -- RGB to YCbCr conversion
554
  -------------------------------------------------------------------
555
  p_rgb2ycbcr : process(CLK, RST)
556
  begin
557
    if RST = '1' then
558
      Y_Reg_1  <= (others => '0');
559
      Y_Reg_2  <= (others => '0');
560
      Y_Reg_3  <= (others => '0');
561
      Cb_Reg_1 <= (others => '0');
562
      Cb_Reg_2 <= (others => '0');
563
      Cb_Reg_3 <= (others => '0');
564
      Cr_Reg_1 <= (others => '0');
565
      Cr_Reg_2 <= (others => '0');
566
      Cr_Reg_3 <= (others => '0');
567
      Y_Reg    <= (others => '0');
568
      Cb_Reg   <= (others => '0');
569
      Cr_Reg   <= (others => '0');
570
    elsif CLK'event and CLK = '1' then
571 63 mikel262
      -- RGB input
572
      if C_YUV_INPUT = '0' then
573
        Y_Reg_1  <= R_s*C_Y_1;
574
        Y_Reg_2  <= G_s*C_Y_2;
575
        Y_Reg_3  <= B_s*C_Y_3;
576
 
577
        Cb_Reg_1 <= R_s*C_Cb_1;
578
        Cb_Reg_2 <= G_s*C_Cb_2;
579
        Cb_Reg_3 <= B_s*C_Cb_3;
580
 
581
        Cr_Reg_1 <= R_s*C_Cr_1;
582
        Cr_Reg_2 <= G_s*C_Cr_2;
583
        Cr_Reg_3 <= B_s*C_Cr_3;
584
 
585
        Y_Reg  <= Y_Reg_1 + Y_Reg_2 + Y_Reg_3;
586
        Cb_Reg <= Cb_Reg_1 + Cb_Reg_2 + Cb_Reg_3 + to_signed(128*16384,Cb_Reg'length);
587
        Cr_Reg <= Cr_Reg_1 + Cr_Reg_2 + Cr_Reg_3 + to_signed(128*16384,Cr_Reg'length);
588
      -- YCbCr input
589
      -- R-G-B misused as Y-Cb-Cr
590
      else
591
        Y_Reg_1  <= '0' & R_s & "00000000000000";
592
        Cb_Reg_1 <= '0' & G_s & "00000000000000";
593
        Cr_Reg_1 <= '0' & B_s & "00000000000000";
594
 
595
        Y_Reg  <= Y_Reg_1;
596
        Cb_Reg <= Cb_Reg_1;
597
        Cr_Reg <= Cr_Reg_1;
598
      end if;
599 25 mikel262
    end if;
600
  end process;
601
 
602
  Y_8bit  <= unsigned(Y_Reg(21 downto 14));
603
  Cb_8bit <= unsigned(Cb_Reg(21 downto 14));
604
  Cr_8bit <= unsigned(Cr_Reg(21 downto 14));
605
 
606
 
607
  -------------------------------------------------------------------
608
  -- DBUF
609
  -------------------------------------------------------------------
610
  U_RAMZ : entity work.RAMZ
611
  generic map
612
  (
613
      RAMADDR_W     => 7,
614
      RAMDATA_W     => 12
615
  )
616
  port map
617
  (
618
        d           => dbuf_data,
619
        waddr       => dbuf_waddr,
620
        raddr       => dbuf_raddr,
621
        we          => dbuf_we,
622
        clk         => CLK,
623
 
624
        q           => dbuf_q
625
  );
626
 
627
  dbuf_data  <= fifo1_q;
628
  dbuf_we    <= fifo1_q_dval;
629
  dbuf_waddr <= (not zz_buf_sel) & std_logic_vector(yw_cnt & xw_cnt);
630
  dbuf_raddr <= zz_buf_sel & zz_rd_addr;
631
 
632
end architecture RTL;
633
-------------------------------------------------------------------------------
634
-- Architecture: end
635
-------------------------------------------------------------------------------

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