OpenCores
URL https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk

Subversion Repositories mkjpeg

[/] [mkjpeg/] [trunk/] [design/] [mdct/] [RAM.VHD] - Blame information for rev 67

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 25 mikel262 
--------------------------------------------------------------------------------
2 
--                                                                            --
3 
--                          V H D L    F I L E                                --
4 
--                          COPYRIGHT (C) 2006                                --
5 
--                                                                            --
6 
--------------------------------------------------------------------------------
7 
--                                                                            --
8 
-- Title       : RAM                                                          --
9 
-- Design      : MDCT                                                         --
10 
-- Author      : Michal Krepa                                                 --                                                             --                                                           --
11 
--                                                                            --
12 
--------------------------------------------------------------------------------
13 
--
14 
-- File        : RAM.VHD
15 
-- Created     : Sat Mar 5 7:37 2006
16 
--
17 
--------------------------------------------------------------------------------
18 
--
19 
--  Description : RAM memory simulation model
20 
--
21 
--------------------------------------------------------------------------------
22 
 
23 
-- 5:3 row select
24 
-- 2:0 col select
25 
 
26 
library IEEE;
27 
  use IEEE.STD_LOGIC_1164.all;
28 
  use IEEE.NUMERIC_STD.all;
29 
 
30 
library WORK;
31 
  use WORK.MDCT_PKG.all;
32 
 
33 
entity RAM is
34 
  port (
35 
        d                 : in  STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
36 
        waddr             : in  STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
37 
        raddr             : in  STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
38 
        we                : in  STD_LOGIC;
39 
        clk               : in  STD_LOGIC;
40 
 
41 
        q                 : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0)
42 
  );
43 
end RAM;
44 
 
45 
architecture RTL of RAM is
46 
  type mem_type is array ((2**RAMADRR_W)-1 downto 0) of
47 
                              STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
48 
  signal mem                    : mem_type;
49 
  signal read_addr              : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
50 
 
51 
begin
52 
 
53 
  -------------------------------------------------------------------------------
54 
  q_sg:
55 
  -------------------------------------------------------------------------------
56 
  q <= mem(TO_INTEGER(UNSIGNED(read_addr)));
57 
 
58 
  -------------------------------------------------------------------------------
59 
  read_proc: -- register read address
60 
  -------------------------------------------------------------------------------
61 
  process (clk)
62 
  begin
63 
    if clk = '1' and clk'event then
64 
      read_addr <= raddr;
65 
    end if;
66 
  end process;
67 
 
68 
  -------------------------------------------------------------------------------
69 
  write_proc: --write access
70 
  -------------------------------------------------------------------------------
71 
  process (clk) begin
72 
    if clk = '1' and clk'event then
73 
      if we = '1'  then
74 
        mem(TO_INTEGER(UNSIGNED(waddr))) <= d;
75 
      end if;
76 
    end if;
77 
  end process;
78 
 
79 
end RTL;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.