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[/] [mkjpeg/] [trunk/] [design/] [quantizer/] [QUANTIZER.vhd] - Blame information for rev 67

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--------------------------------------------------------------------------------
--                                                                            --
--                          V H D L    F I L E                                --
--                          COPYRIGHT (C) 2006-2009                           --
--                                                                            --
--------------------------------------------------------------------------------
--                                                                            --
-- Title       : DIVIDER                                                      --
-- Design      : DCT QUANTIZER                                                --
-- Author      : Michal Krepa                                                 --
--                                                                            --
--------------------------------------------------------------------------------
--                                                                            --
-- File        : QUANTIZER.VHD                                                --
-- Created     : Sun Aug 27 2006                                              --
--                                                                            --
--------------------------------------------------------------------------------
--                                                                            --
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
library IEEE;
  use IEEE.STD_LOGIC_1164.All;
  use IEEE.NUMERIC_STD.all;
 
entity quantizer is
  generic
    (
      SIZE_C        : INTEGER := 12;
      RAMQADDR_W    : INTEGER := 7;
      RAMQDATA_W    : INTEGER := 8
    );
  port
    (
      rst        : in  STD_LOGIC;
      clk        : in  STD_LOGIC;
      di         : in  STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
      divalid    : in  STD_LOGIC;
      qdata      : in  std_logic_vector(7 downto 0);
      qwaddr     : in  std_logic_vector(6 downto 0);
      qwren      : in  std_logic;
      cmp_idx    : in  unsigned(2 downto 0);
 
      do         : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
      dovalid    : out STD_LOGIC
    );
end quantizer;
 
architecture rtl of quantizer is
 
  constant INTERN_PIPE_C : INTEGER := 3;
 
  signal romaddr_s     : UNSIGNED(RAMQADDR_W-2 downto 0);
  signal slv_romaddr_s : STD_LOGIC_VECTOR(RAMQADDR_W-1 downto 0);
  signal romdatao_s    : STD_LOGIC_VECTOR(RAMQDATA_W-1 downto 0);
  signal divisor_s     : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
  signal remainder_s   : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
  signal do_s          : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
  signal round_s       : STD_LOGIC;
  signal di_d1         : std_logic_vector(SIZE_C-1 downto 0);
 
  signal pipeline_reg  : STD_LOGIC_VECTOR(4 downto 0);
  signal sign_bit_pipe : std_logic_vector(SIZE_C+INTERN_PIPE_C+1-1 downto 0);
  signal do_rdiv       : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
  signal table_select  : std_logic;
 
begin
 
  ----------------------------
  -- RAMQ
  ----------------------------
  U_RAMQ : entity work.RAMZ
    generic map
    (
      RAMADDR_W    => RAMQADDR_W,
      RAMDATA_W    => RAMQDATA_W
    )
    port map
    (
      d           => qdata,
      waddr       => qwaddr,
      raddr       => slv_romaddr_s,
      we          => qwren,
      clk         => CLK,
 
      q           => romdatao_s
    );
 
 
 
  divisor_s(RAMQDATA_W-1 downto 0)      <= romdatao_s;
  divisor_s(SIZE_C-1 downto RAMQDATA_W) <= (others => '0');
 
  r_divider : entity work.r_divider
  port map
  (
       rst   => rst,
       clk   => clk,
       a     => di_d1,
       d     => romdatao_s,
 
       q     => do_s
  ) ;
  do <= do_s;
  slv_romaddr_s <= table_select & STD_LOGIC_VECTOR(romaddr_s);
 
  ------------------------------
  -- Quantization sub table select
  ------------------------------
  process(clk)
  begin
    if clk = '1' and clk'event then
      if rst = '1' then
        table_select <= '0';
      else
        -- luminance table select
        if cmp_idx < 2 then
          table_select <= '0';
        -- chrominance table select
        else
          table_select <= '1';
        end if;
      end if;
    end if;
  end process;
 
  ----------------------------
  -- address incrementer
  ----------------------------
  process(clk)
  begin
    if clk = '1' and clk'event then
      if rst = '1' then
        romaddr_s     <= (others => '0');
        pipeline_reg  <= (OTHERS => '0');
        di_d1         <= (OTHERS => '0');
        sign_bit_pipe <= (others => '0');
      else
        if divalid = '1' then
          romaddr_s <= romaddr_s + TO_UNSIGNED(1,romaddr_s'length);
        end if;
 
        pipeline_reg <= pipeline_reg(pipeline_reg'length-2 downto 0) & divalid;
 
        di_d1 <= di;
 
        sign_bit_pipe <= sign_bit_pipe(sign_bit_pipe'length-2 downto 0) & di(SIZE_C-1);
      end if;
    end if;
  end process;
 
  dovalid <= pipeline_reg(pipeline_reg'high);
 
end rtl;
--------------------------------------------------------------------------------

Line No.	Rev	Author	Line
1	25	mikel262	`--------------------------------------------------------------------------------`
2			`-- --`
3			`-- V H D L F I L E --`
4	32	mikel262	`-- COPYRIGHT (C) 2006-2009 --`
5	25	mikel262	`-- --`
6			`--------------------------------------------------------------------------------`
7			`-- --`
8			`-- Title : DIVIDER --`
9			`-- Design : DCT QUANTIZER --`
10			`-- Author : Michal Krepa --`
11			`-- --`
12			`--------------------------------------------------------------------------------`
13			`-- --`
14			`-- File : QUANTIZER.VHD --`
15			`-- Created : Sun Aug 27 2006 --`
16			`-- --`
17			`--------------------------------------------------------------------------------`
18			`-- --`
19			`--------------------------------------------------------------------------------`
20
21			`--------------------------------------------------------------------------------`
22
23			`library IEEE;`
24			`use IEEE.STD_LOGIC_1164.All;`
25			`use IEEE.NUMERIC_STD.all;`
26
27			`entity quantizer is`
28			`generic`
29			`(`
30			`SIZE_C : INTEGER := 12;`
31	32	mikel262	`RAMQADDR_W : INTEGER := 7;`
32	25	mikel262	`RAMQDATA_W : INTEGER := 8`
33			`);`
34			`port`
35			`(`
36			`rst : in STD_LOGIC;`
37			`clk : in STD_LOGIC;`
38			`di : in STD_LOGIC_VECTOR(SIZE_C-1 downto 0);`
39			`divalid : in STD_LOGIC;`
40			`qdata : in std_logic_vector(7 downto 0);`
41	32	mikel262	`qwaddr : in std_logic_vector(6 downto 0);`
42	25	mikel262	`qwren : in std_logic;`
43	61	mikel262	`cmp_idx : in unsigned(2 downto 0);`
44	25	mikel262
45			`do : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0);`
46			`dovalid : out STD_LOGIC`
47			`);`
48			`end quantizer;`
49
50			`architecture rtl of quantizer is`
51
52			`constant INTERN_PIPE_C : INTEGER := 3;`
53
54	32	mikel262	`signal romaddr_s : UNSIGNED(RAMQADDR_W-2 downto 0);`
55	25	mikel262	`signal slv_romaddr_s : STD_LOGIC_VECTOR(RAMQADDR_W-1 downto 0);`
56			`signal romdatao_s : STD_LOGIC_VECTOR(RAMQDATA_W-1 downto 0);`
57			`signal divisor_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);`
58			`signal remainder_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);`
59			`signal do_s : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);`
60			`signal round_s : STD_LOGIC;`
61			`signal di_d1 : std_logic_vector(SIZE_C-1 downto 0);`
62
63			`signal pipeline_reg : STD_LOGIC_VECTOR(4 downto 0);`
64			`signal sign_bit_pipe : std_logic_vector(SIZE_C+INTERN_PIPE_C+1-1 downto 0);`
65			`signal do_rdiv : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);`
66	32	mikel262	`signal table_select : std_logic;`
67
68	25	mikel262	`begin`
69
70			`----------------------------`
71			`-- RAMQ`
72			`----------------------------`
73			`U_RAMQ : entity work.RAMZ`
74			`generic map`
75			`(`
76			`RAMADDR_W => RAMQADDR_W,`
77			`RAMDATA_W => RAMQDATA_W`
78			`)`
79			`port map`
80			`(`
81			`d => qdata,`
82			`waddr => qwaddr,`
83			`raddr => slv_romaddr_s,`
84			`we => qwren,`
85			`clk => CLK,`
86
87			`q => romdatao_s`
88			`);`
89
90	32	mikel262
91	25	mikel262
92			`divisor_s(RAMQDATA_W-1 downto 0) <= romdatao_s;`
93			`divisor_s(SIZE_C-1 downto RAMQDATA_W) <= (others => '0');`
94
95			`r_divider : entity work.r_divider`
96			`port map`
97			`(`
98			`rst => rst,`
99			`clk => clk,`
100			`a => di_d1,`
101			`d => romdatao_s,`
102
103			`q => do_s`
104			`) ;`
105			`do <= do_s;`
106	32	mikel262	`slv_romaddr_s <= table_select & STD_LOGIC_VECTOR(romaddr_s);`
107	25	mikel262
108			`------------------------------`
109	32	mikel262	`-- Quantization sub table select`
110	25	mikel262	`------------------------------`
111	32	mikel262	`process(clk)`
112			`begin`
113			`if clk = '1' and clk'event then`
114			`if rst = '1' then`
115			`table_select <= '0';`
116			`else`
117			`-- luminance table select`
118	61	mikel262	`if cmp_idx < 2 then`
119	32	mikel262	`table_select <= '0';`
120			`-- chrominance table select`
121			`else`
122			`table_select <= '1';`
123			`end if;`
124			`end if;`
125			`end if;`
126			`end process;`
127	25	mikel262
128			`----------------------------`
129			`-- address incrementer`
130			`----------------------------`
131			`process(clk)`
132			`begin`
133			`if clk = '1' and clk'event then`
134			`if rst = '1' then`
135			`romaddr_s <= (others => '0');`
136			`pipeline_reg <= (OTHERS => '0');`
137			`di_d1 <= (OTHERS => '0');`
138			`sign_bit_pipe <= (others => '0');`
139			`else`
140			`if divalid = '1' then`
141	32	mikel262	`romaddr_s <= romaddr_s + TO_UNSIGNED(1,romaddr_s'length);`
142	25	mikel262	`end if;`
143
144			`pipeline_reg <= pipeline_reg(pipeline_reg'length-2 downto 0) & divalid;`
145
146			`di_d1 <= di;`
147
148			`sign_bit_pipe <= sign_bit_pipe(sign_bit_pipe'length-2 downto 0) & di(SIZE_C-1);`
149			`end if;`
150			`end if;`
151			`end process;`
152
153			`dovalid <= pipeline_reg(pipeline_reg'high);`
154
155			`end rtl;`
156			`--------------------------------------------------------------------------------`

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[/] [mkjpeg/] [trunk/] [design/] [quantizer/] [QUANTIZER.vhd] - Blame information for rev 67