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[/] [mkjpeg/] [trunk/] [design/] [quantizer/] [ROMQ.vhd] - Blame information for rev 61

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Line No. Rev Author Line
1 25 mikel262
--------------------------------------------------------------------------------
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--                                                                            --
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--                          V H D L    F I L E                                --
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--                          COPYRIGHT (C) 2006                                --
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--                                                                            --
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--------------------------------------------------------------------------------
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--
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-- Title       : DCT
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-- Design      : MDCT Core
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-- Author      : Michal Krepa
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--
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--------------------------------------------------------------------------------
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--
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-- File        : ROMQ.VHD
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-- Created     : Sun Aug 27 18:09 2006
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--
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--------------------------------------------------------------------------------
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--
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--  Description : ROM for DCT quantizer matrix
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--
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--------------------------------------------------------------------------------
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library IEEE;
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  use IEEE.STD_LOGIC_1164.all;
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  use ieee.numeric_std.all;
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entity ROMQ is
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  generic
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    (
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      ROMADDR_W     : INTEGER := 6;
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      ROMDATA_W     : INTEGER := 8
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    );
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  port(
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       addr         : in  STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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       clk          : in  STD_LOGIC;
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       datao        : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
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  );
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end ROMQ;
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architecture RTL of ROMQ is
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  type ROMQ_TYPE is array (0 to 2**ROMADDR_W-1)
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            of INTEGER range 0 to 2**ROMDATA_W-1;
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  constant rom : ROMQ_TYPE :=
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  -- (
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  -- 16,11,10,16,24,40,51,61,
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  -- 12,12,14,19,26,58,60,55,
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  -- 14,13,16,24,40,57,69,56,
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  -- 14,17,22,29,51,87,80,62,
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  -- 18,22,37,56,68,109,103,77,
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  -- 24,35,55,64,81,104,113,92,
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  -- 49,64,78,87,103,121,120,101,
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  -- 72,92,95,98,112,100,103,99);
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                          (
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                 --8,6,6,7,6,5,8,
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                 --7,7,7,9,9,8,10,12,
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                 --20,13,12,11,11,12,25,18,19,15,20,29,
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                 --26,31,30,29,26,28,28,32,36,46,39,32,
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                 --34,44,35,28,28,40,55,41,44,48,49,52,52,52,
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                 --31,39,57,61,56,50,60,46,51,52,50
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                          1,1,1,1,1,1,1,1,
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                          1,1,1,1,1,1,1,1,
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                          1,1,1,1,1,1,1,1,
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                          1,1,1,1,1,1,1,1,
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                          1,1,1,1,1,1,1,1,
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                          1,1,1,1,1,1,1,1,
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                          1,1,1,1,1,1,1,1,
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                          1,1,1,1,1,1,1,1
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                          );
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  signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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begin
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  datao <= STD_LOGIC_VECTOR(TO_UNSIGNED( rom( TO_INTEGER(UNSIGNED(addr_reg)) ), ROMDATA_W));
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  process(clk)
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  begin
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   if clk = '1' and clk'event then
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     addr_reg <= addr;
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   end if;
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  end process;
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end RTL;

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