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[/] [mkjpeg/] [trunk/] [design/] [quantizer/] [r_divider.vhd] - Blame information for rev 57

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--------------------------------------------------------------------------------
--                                                                            --
--                          V H D L    F I L E                                --
--                          COPYRIGHT (C) 2009                                --
--                                                                            --
--------------------------------------------------------------------------------
--                                                                            --
-- Title       : DIVIDER                                                      --
-- Design      : Divider using reciprocal table                               --
-- Author      : Michal Krepa                                                 --
--                                                                            --
--------------------------------------------------------------------------------
--                                                                            --
-- File        : R_DIVIDER.VHD                                                --
-- Created     : Wed 18-03-2009                                               --
--                                                                            --
--------------------------------------------------------------------------------
--                                                                            --
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
-- MAIN DIVIDER top level
--------------------------------------------------------------------------------
library IEEE;
  use IEEE.STD_LOGIC_1164.All;
  use IEEE.NUMERIC_STD.all;
 
entity r_divider is
  port
  (
       rst   : in  STD_LOGIC;
       clk   : in  STD_LOGIC;
       a     : in  STD_LOGIC_VECTOR(11 downto 0);
       d     : in  STD_LOGIC_VECTOR(7 downto 0);
 
       q     : out STD_LOGIC_VECTOR(11 downto 0)
  ) ;
end r_divider ;
 
architecture rtl of r_divider is
 
  signal romr_datao    : std_logic_vector(15 downto 0);
  signal romr_addr     : std_logic_vector(7 downto 0);
  signal dividend      : signed(11 downto 0);
  signal dividend_d1   : unsigned(11 downto 0);
  signal reciprocal    : unsigned(15 downto 0);
  signal mult_out      : unsigned(27 downto 0);
  signal mult_out_s    : signed(11 downto 0);
  signal signbit       : std_logic;
  signal signbit_d1    : std_logic;
  signal signbit_d2    : std_logic;
  signal signbit_d3    : std_logic;
  signal round         : std_logic;
 
begin
 
  U_ROMR : entity work.ROMR
    generic map
    (
      ROMADDR_W    => 8,
      ROMDATA_W    => 16
    )
    port map
    (
      addr  => romr_addr,
      clk   => CLK,
      datao => romr_datao
    );
 
  romr_addr <= d;
  reciprocal <= unsigned(romr_datao);
 
 dividend <= signed(a);
 signbit <= dividend(dividend'high);
 
 rdiv : process(clk,rst)
 begin
   if rst = '1' then
     mult_out    <= (others => '0');
     mult_out_s  <= (others => '0');
     dividend_d1 <= (others => '0');
     q           <= (others => '0');
     signbit_d1  <= '0';
     signbit_d2  <= '0';
     signbit_d3  <= '0';
     round       <= '0';
   elsif clk = '1' and clk'event then
     signbit_d1  <= signbit;
     signbit_d2  <= signbit_d1;
     signbit_d3  <= signbit_d2;
     if signbit = '1' then
       dividend_d1 <= unsigned(0-dividend);
     else
       dividend_d1 <= unsigned(dividend);
     end if;
 
     mult_out <= dividend_d1 * reciprocal;
 
     if signbit_d2 = '0' then
       mult_out_s <= resize(signed(mult_out(27 downto 16)),mult_out_s'length);
     else
       mult_out_s <= resize(0-signed(mult_out(27 downto 16)),mult_out_s'length);
     end if;
     round <= mult_out(15);
 
     if signbit_d3 = '0' then
       if round = '1' then
         q <= std_logic_vector(mult_out_s + 1);
       else
         q <= std_logic_vector(mult_out_s);
       end if;
     else
       if round = '1' then
         q <= std_logic_vector(mult_out_s - 1);
       else
         q <= std_logic_vector(mult_out_s);
       end if;
     end if;
   end if;
 end process;
 
end rtl;
 
 

Line No.	Rev	Author	Line
1	25	mikel262	`--------------------------------------------------------------------------------`
2			`-- --`
3			`-- V H D L F I L E --`
4			`-- COPYRIGHT (C) 2009 --`
5			`-- --`
6			`--------------------------------------------------------------------------------`
7			`-- --`
8			`-- Title : DIVIDER --`
9			`-- Design : Divider using reciprocal table --`
10			`-- Author : Michal Krepa --`
11			`-- --`
12			`--------------------------------------------------------------------------------`
13			`-- --`
14			`-- File : R_DIVIDER.VHD --`
15			`-- Created : Wed 18-03-2009 --`
16			`-- --`
17			`--------------------------------------------------------------------------------`
18			`-- --`
19			`--------------------------------------------------------------------------------`
20
21			`--------------------------------------------------------------------------------`
22			`-- MAIN DIVIDER top level`
23			`--------------------------------------------------------------------------------`
24			`library IEEE;`
25			`use IEEE.STD_LOGIC_1164.All;`
26			`use IEEE.NUMERIC_STD.all;`
27
28			`entity r_divider is`
29			`port`
30			`(`
31			`rst : in STD_LOGIC;`
32			`clk : in STD_LOGIC;`
33			`a : in STD_LOGIC_VECTOR(11 downto 0);`
34			`d : in STD_LOGIC_VECTOR(7 downto 0);`
35
36			`q : out STD_LOGIC_VECTOR(11 downto 0)`
37			`) ;`
38			`end r_divider ;`
39
40			`architecture rtl of r_divider is`
41
42			`signal romr_datao : std_logic_vector(15 downto 0);`
43			`signal romr_addr : std_logic_vector(7 downto 0);`
44			`signal dividend : signed(11 downto 0);`
45			`signal dividend_d1 : unsigned(11 downto 0);`
46			`signal reciprocal : unsigned(15 downto 0);`
47			`signal mult_out : unsigned(27 downto 0);`
48			`signal mult_out_s : signed(11 downto 0);`
49			`signal signbit : std_logic;`
50			`signal signbit_d1 : std_logic;`
51			`signal signbit_d2 : std_logic;`
52			`signal signbit_d3 : std_logic;`
53			`signal round : std_logic;`
54
55			`begin`
56
57			`U_ROMR : entity work.ROMR`
58			`generic map`
59			`(`
60			`ROMADDR_W => 8,`
61			`ROMDATA_W => 16`
62			`)`
63			`port map`
64			`(`
65			`addr => romr_addr,`
66			`clk => CLK,`
67			`datao => romr_datao`
68			`);`
69
70			`romr_addr <= d;`
71			`reciprocal <= unsigned(romr_datao);`
72
73			`dividend <= signed(a);`
74			`signbit <= dividend(dividend'high);`
75
76			`rdiv : process(clk,rst)`
77			`begin`
78			`if rst = '1' then`
79			`mult_out <= (others => '0');`
80			`mult_out_s <= (others => '0');`
81			`dividend_d1 <= (others => '0');`
82			`q <= (others => '0');`
83			`signbit_d1 <= '0';`
84			`signbit_d2 <= '0';`
85			`signbit_d3 <= '0';`
86			`round <= '0';`
87			`elsif clk = '1' and clk'event then`
88			`signbit_d1 <= signbit;`
89			`signbit_d2 <= signbit_d1;`
90			`signbit_d3 <= signbit_d2;`
91			`if signbit = '1' then`
92			`dividend_d1 <= unsigned(0-dividend);`
93			`else`
94			`dividend_d1 <= unsigned(dividend);`
95			`end if;`
96
97			`mult_out <= dividend_d1 * reciprocal;`
98
99			`if signbit_d2 = '0' then`
100			`mult_out_s <= resize(signed(mult_out(27 downto 16)),mult_out_s'length);`
101			`else`
102			`mult_out_s <= resize(0-signed(mult_out(27 downto 16)),mult_out_s'length);`
103			`end if;`
104			`round <= mult_out(15);`
105
106			`if signbit_d3 = '0' then`
107			`if round = '1' then`
108			`q <= std_logic_vector(mult_out_s + 1);`
109			`else`
110			`q <= std_logic_vector(mult_out_s);`
111			`end if;`
112			`else`
113			`if round = '1' then`
114			`q <= std_logic_vector(mult_out_s - 1);`
115			`else`
116			`q <= std_logic_vector(mult_out_s);`
117			`end if;`
118			`end if;`
119			`end if;`
120			`end process;`
121
122			`end rtl;`
123
124

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[/] [mkjpeg/] [trunk/] [design/] [quantizer/] [r_divider.vhd] - Blame information for rev 57