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[/] [mkjpeg/] [trunk/] [design/] [quantizer/] [s_divider.vhd] - Blame information for rev 34

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1 25 mikel262 
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--                                                                            --
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--                          V H D L    F I L E                                --
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--                          COPYRIGHT (C) 2006-2009                           --
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--                                                                            --
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--------------------------------------------------------------------------------
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--                                                                            --
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-- Title       : DIVIDER                                                      --
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-- Design      : Signed Pipelined Divider core                                --
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-- Author      : Michal Krepa                                                 --
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--                                                                            --
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--------------------------------------------------------------------------------
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--                                                                            --
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-- File        : S_DIVIDER.VHD                                                --
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-- Created     : Sat Aug 26 2006                                              --
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-- Modified    : Thu Mar 12 2009                                              --
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--                                                                            --
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--------------------------------------------------------------------------------
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--                                                                            --
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--  Description : Signed Pipelined Divider                                    --
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--                                                                            --
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-- dividend allowable range of -2**SIZE_C to 2**SIZE_C-1 [SIGNED number]      --
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-- divisor allowable range of 1 to (2**SIZE_C)/2-1 [UNSIGNED number]          --
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-- pipeline latency is 2*SIZE_C+2 (time from latching input to result ready)  --
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-- when pipeline is full new result is generated every clock cycle            --
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-- Non-Restoring division algorithm                                           --
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-- Use SIZE_C constant in divider entity to adjust bit width                  --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- MAIN DIVIDER top level
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--------------------------------------------------------------------------------
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library IEEE;
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  use IEEE.STD_LOGIC_1164.All;
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  use IEEE.NUMERIC_STD.all;
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entity s_divider is
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  generic
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  (
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       SIZE_C          : INTEGER := 32
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  ) ;            -- SIZE_C: Number of bits
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  port
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  (
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       rst   : in  STD_LOGIC;
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       clk   : in  STD_LOGIC;
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       a     : in  STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
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       d     : in  STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
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       q     : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
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       r     : out STD_LOGIC_VECTOR(SIZE_C-1 downto 0) ;
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       round : out STD_LOGIC
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  ) ;
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end s_divider ;
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architecture str of s_divider is
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  type S_ARRAY  is array(0 to SIZE_C+3) of unsigned(SIZE_C-1 downto 0);
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  type S2_ARRAY is array(0 to SIZE_C+1) of unsigned(2*SIZE_C-1 downto 0);
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  signal d_s          : S_ARRAY;
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  signal q_s          : S_ARRAY;
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  signal r_s          : S2_ARRAY;
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  signal diff         : S_ARRAY;
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  signal qu_s         : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
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  signal ru_s         : unsigned(SIZE_C-1 downto 0);
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  signal qu_s2        : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
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  signal ru_s2        : unsigned(SIZE_C-1 downto 0);
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  signal d_reg        : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
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  signal pipeline_reg : STD_LOGIC_VECTOR(SIZE_C+3-1 downto 0);
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  signal r_reg        : STD_LOGIC_VECTOR(SIZE_C-1 downto 0);
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begin
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 pipeline : process(clk,rst)
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 begin
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   if rst = '1' then
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     for k in 0 to SIZE_C loop
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       r_s(k) <= (others => '0');
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       q_s(k) <= (others => '0');
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       d_s(k) <= (others => '0');
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     end loop;
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     pipeline_reg <= (others => '0');
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   elsif clk = '1' and clk'event then
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     -- negative number
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     if a(SIZE_C-1) = '1' then
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       -- negate negative number to create positive
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       r_s(0)       <= unsigned(resize(unsigned(not(SIGNED(a)) + TO_SIGNED(1,SIZE_C)),2*SIZE_C));
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       -- left shift
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       pipeline_reg <= pipeline_reg(pipeline_reg'high-1 downto 0) & '1';
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     else
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       r_s(0)       <= resize(unsigned(a),2*SIZE_C);
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       -- left shift
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       pipeline_reg <= pipeline_reg(pipeline_reg'high-1 downto 0) & '0';
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     end if;
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     d_s(0) <= unsigned(d);
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     q_s(0) <= (others => '0');
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     -- pipeline
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     for k in 0 to SIZE_C loop
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       -- test remainder if positive/negative
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       if r_s(k)(2*SIZE_C-1) = '0' then
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         -- shift r_tmp one bit left and subtract d_tmp from upper part of r_tmp
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         r_s(k+1)(2*SIZE_C-1 downto SIZE_C) <= r_s(k)(2*SIZE_C-2 downto SIZE_C-1) - d_s(k);
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       else
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         r_s(k+1)(2*SIZE_C-1 downto SIZE_C) <= r_s(k)(2*SIZE_C-2 downto SIZE_C-1) + d_s(k);
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       end if;
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       -- shift r_tmp one bit left (lower part)
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       r_s(k+1)(SIZE_C-1 downto 0) <= r_s(k)(SIZE_C-2 downto 0) & '0';
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       if diff(k)(SIZE_C-1) = '0' then
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         q_s(k+1) <= q_s(k)(SIZE_C-2 downto 0) & '1';
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       else
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         q_s(k+1) <= q_s(k)(SIZE_C-2 downto 0) & '0';
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       end if;
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       d_s(k+1) <= d_s(k);
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     end loop;
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   end if;
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 end process;
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 G_DIFF: for x in 0 to SIZE_C generate
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   diff(x) <= r_s(x)(2*SIZE_C-2 downto SIZE_C-1) - d_s(x) when r_s(x)(2*SIZE_C-1) = '0'
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              else r_s(x)(2*SIZE_C-2 downto SIZE_C-1) + d_s(x);
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 end generate G_DIFF;
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 qu_s <= STD_LOGIC_VECTOR( q_s(SIZE_C) );
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 ru_s <= r_s(SIZE_C)(2*SIZE_C-1 downto SIZE_C);
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 process(clk,rst)
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 begin
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   if rst = '1' then
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     q     <= (others => '0');
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     r_reg <= (others => '0');
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     round <= '0';
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   elsif clk = '1' and clk'event then
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     if ru_s(SIZE_C-1) = '0' then
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       ru_s2 <= (ru_s);
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     else
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       ru_s2 <= (unsigned(ru_s) + d_s(SIZE_C));
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     end if;
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     qu_s2 <= qu_s;
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     -- negative number
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     if pipeline_reg(SIZE_C+1) = '1' then
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       -- negate positive number to create negative
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       q <= STD_LOGIC_VECTOR(not(SIGNED(qu_s2)) + TO_SIGNED(1,SIZE_C));
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       r_reg <= STD_LOGIC_VECTOR(not(SIGNED(ru_s2)) + TO_SIGNED(1,SIZE_C));
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     else
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       q <= STD_LOGIC_VECTOR(qu_s2);
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       r_reg <= STD_LOGIC_VECTOR(ru_s2);
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     end if;
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     -- if 2*remainder >= divisor then add 1 to round to nearest integer
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     if (ru_s2(SIZE_C-2 downto 0) & '0') >= d_s(SIZE_C+1) then
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       round <= '1';
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     else
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       round <= '0';
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     end if;
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   end if;
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 end process;
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 -- remainder
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 r <= r_reg;
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end str;
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