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--------------------------------------------------------------------------------
--                                                                            --
--                          V H D L    F I L E                                --
--                          COPYRIGHT (C) 2009                                --
--                                                                            --
--------------------------------------------------------------------------------
--                                                                            --
-- Title       : RLE                                                          --
-- Design      : MDCT CORE                                                    --
-- Author      : Michal Krepa                                                 --
--                                                                            --
--------------------------------------------------------------------------------
--                                                                            --
-- File        : RLE.VHD                                                      --
-- Created     : Wed Mar 04 2009                                              --
--                                                                            --
--------------------------------------------------------------------------------
--                                                                            --
--  Description : Run Length Encoder                                          --
--                Baseline Entropy Coding                                     --
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
library IEEE;
  use IEEE.STD_LOGIC_1164.All;
  use IEEE.NUMERIC_STD.all;
 
library work;
  use work.JPEG_PKG.all;
 
entity rle is
  generic
    (
      RAMADDR_W     : INTEGER := 6;
      RAMDATA_W     : INTEGER := 12
    );
  port
    (
      rst        : in  STD_LOGIC;
      clk        : in  STD_LOGIC;
      di         : in  STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
      start_pb   : in  std_logic;
      sof        : in  std_logic;
      rle_sm_settings : in T_SM_SETTINGS;
 
      runlength  : out STD_LOGIC_VECTOR(3 downto 0);
      size       : out STD_LOGIC_VECTOR(3 downto 0);
      amplitude  : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
      dovalid    : out STD_LOGIC;
      rd_addr    : out STD_LOGIC_VECTOR(5 downto 0)
    );
end rle;
 
architecture rtl of rle is
 
 
 
  constant SIZE_REG_C      : INTEGER := 4;
  constant ZEROS_32_C      : UNSIGNED(31 downto 0) := (others => '0');
 
  signal prev_dc_reg_0   : SIGNED(RAMDATA_W-1 downto 0);
  signal prev_dc_reg_1   : SIGNED(RAMDATA_W-1 downto 0);
  signal prev_dc_reg_2   : SIGNED(RAMDATA_W-1 downto 0);
  signal acc_reg         : SIGNED(RAMDATA_W downto 0);
  signal size_reg        : UNSIGNED(SIZE_REG_C-1 downto 0);
  signal ampli_vli_reg   : SIGNED(RAMDATA_W downto 0);
  signal runlength_reg   : UNSIGNED(3 downto 0);
  signal dovalid_reg     : STD_LOGIC;
  signal zero_cnt        : unsigned(5 downto 0);
  signal wr_cnt_d1       : unsigned(5 downto 0);
  signal wr_cnt          : unsigned(5 downto 0);
 
  signal rd_cnt         : unsigned(5 downto 0);
  signal rd_en          : std_logic;
 
  signal divalid        : STD_LOGIC;
  signal zrl_proc       : std_logic;
  signal zrl_proc_d1    : std_logic;
  signal zrl_di         : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
begin
 
  size      <= STD_LOGIC_VECTOR(size_reg);
  amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
 
  rd_addr <= STD_LOGIC_VECTOR(rd_cnt);
 
  -------------------------------------------
  -- Counter1
  -------------------------------------------
  process(clk,rst)
  begin
    if rst = '1' then
      rd_en           <= '0';
      rd_cnt          <= (others => '0');
    elsif clk = '1' and clk'event then
      if start_pb = '1' then
        rd_cnt <= (others => '0');
        rd_en <= '1';
      end if;
 
      -- input read enable
      if rd_en = '1' and zrl_proc = '0' then
        if rd_cnt = 64-1 then
          rd_cnt <= (others => '0');
          rd_en  <= '0';
        else
          rd_cnt <= rd_cnt + 1;
        end if;
      end if;
    end if;
  end process;
 
  -------------------------------------------
  -- MAIN PROCESSING
  -------------------------------------------
  process(clk,rst)
  begin
    if rst = '1' then
      wr_cnt_d1       <= (others => '0');
      prev_dc_reg_0   <= (others => '0');
      prev_dc_reg_1   <= (others => '0');
      prev_dc_reg_2   <= (others => '0');
      dovalid_reg     <= '0';
      acc_reg         <= (others => '0');
      runlength_reg   <= (others => '0');
      runlength       <= (others => '0');
      dovalid         <= '0';
      zero_cnt        <= (others => '0');
      zrl_proc        <= '0';
      zrl_proc_d1     <= '0';
    elsif clk = '1' and clk'event then
      dovalid_reg     <= '0';
      runlength_reg   <= (others => '0');
      wr_cnt_d1       <= wr_cnt;
      runlength       <= std_logic_vector(runlength_reg);
      dovalid         <= dovalid_reg;
      divalid         <= rd_en;
      zrl_proc_d1     <= zrl_proc;
 
      -- input data valid
      if divalid = '1' and zrl_proc_d1 = '0' then
        wr_cnt <= wr_cnt + 1;
 
        -- first DCT coefficient received, DC data
        if wr_cnt = 0 then
          -- differental coding of DC data per component
          case rle_sm_settings.cmp_idx is
            when "00" =>
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
              prev_dc_reg_0 <= SIGNED(di);
            when "01" =>
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
              prev_dc_reg_1 <= SIGNED(di);
            when "10" =>
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
              prev_dc_reg_2 <= SIGNED(di);
            when others =>
              null;
          end case;
          runlength_reg    <= (others => '0');
          dovalid_reg      <= '1';
        -- AC coefficient
        else
          -- zero AC
          if signed(di) = 0 then
            -- EOB
            if wr_cnt = 63 then
              acc_reg          <= (others => '0');
              runlength_reg    <= (others => '0');
              dovalid_reg      <= '1';
            -- no EOB
            else
              zero_cnt <= zero_cnt + 1;
            end if;
          -- non-zero AC
          else
            -- normal RLE case
            if zero_cnt <= 15 then
              acc_reg        <= RESIZE(SIGNED(di),RAMDATA_W+1);
              runlength_reg  <= zero_cnt(3 downto 0);
              zero_cnt       <= (others => '0');
              dovalid_reg    <= '1';
            -- zero_cnt > 15
            else
              -- generate ZRL
              acc_reg        <= (others => '0');
              runlength_reg  <= X"F";
              zero_cnt       <= zero_cnt - 16;
              dovalid_reg    <= '1';
              -- stall input until ZRL is handled
              zrl_proc       <= '1';
              zrl_di         <= di;
            end if;
          end if;
        end if;
      end if;
 
      -- ZRL processing
      if zrl_proc = '1' then
        if zero_cnt <= 15 then
          acc_reg        <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);
          runlength_reg  <= zero_cnt(3 downto 0);
          zero_cnt       <= (others => '0');
          dovalid_reg    <= '1';
          -- continue input handling
          zrl_proc <= '0';
        -- zero_cnt > 15
        else
          -- generate ZRL
          acc_reg        <= (others => '0');
          runlength_reg  <= X"F";
          zero_cnt       <= zero_cnt - 16;
          dovalid_reg    <= '1';
        end if;
      end if;
 
      -- start of 8x8 block processing
      if start_pb = '1' then
        zero_cnt <= (others => '0');
        wr_cnt   <= (others => '0');
      end if;
 
      if sof = '1' then
        prev_dc_reg_0 <= (others => '0');
        prev_dc_reg_1 <= (others => '0');
        prev_dc_reg_2 <= (others => '0');
      end if;
 
    end if;
  end process;
 
  -------------------------------------------------------------------
  -- Entropy Coder
  -------------------------------------------------------------------
  p_entropy_coder : process(CLK, RST)
  begin
    if RST = '1' then
      ampli_vli_reg <= (others => '0');
      size_reg      <= (others => '0');
    elsif CLK'event and CLK = '1' then
      -- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude)
      -- positive input
      if acc_reg >= 0 then
        ampli_vli_reg <= acc_reg;
      else
        ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1);
      end if;
 
      -- compute Symbol-1 Size
      if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then
        size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
      end if;
 
      -- compute Symbol-1 Size
      -- positive input
      if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then
        size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
      end if;
 
      -- DC coefficient amplitude=0 case OR EOB
      if acc_reg = 0 then
         size_reg <= TO_UNSIGNED(0,SIZE_REG_C);
      end if;
    end if;
  end process;
 
end rtl;
--------------------------------------------------------------------------------
 
 

Line No.	Rev	Author	Line
1	25	mikel262	`--------------------------------------------------------------------------------`
2			`-- --`
3			`-- V H D L F I L E --`
4			`-- COPYRIGHT (C) 2009 --`
5			`-- --`
6			`--------------------------------------------------------------------------------`
7			`-- --`
8			`-- Title : RLE --`
9			`-- Design : MDCT CORE --`
10			`-- Author : Michal Krepa --`
11			`-- --`
12			`--------------------------------------------------------------------------------`
13			`-- --`
14			`-- File : RLE.VHD --`
15			`-- Created : Wed Mar 04 2009 --`
16			`-- --`
17			`--------------------------------------------------------------------------------`
18			`-- --`
19			`-- Description : Run Length Encoder --`
20			`-- Baseline Entropy Coding --`
21			`--------------------------------------------------------------------------------`
22
23			`--------------------------------------------------------------------------------`
24
25			`library IEEE;`
26			`use IEEE.STD_LOGIC_1164.All;`
27			`use IEEE.NUMERIC_STD.all;`
28
29			`library work;`
30			`use work.JPEG_PKG.all;`
31
32			`entity rle is`
33			`generic`
34			`(`
35			`RAMADDR_W : INTEGER := 6;`
36			`RAMDATA_W : INTEGER := 12`
37			`);`
38			`port`
39			`(`
40			`rst : in STD_LOGIC;`
41			`clk : in STD_LOGIC;`
42			`di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);`
43			`start_pb : in std_logic;`
44			`sof : in std_logic;`
45			`rle_sm_settings : in T_SM_SETTINGS;`
46
47			`runlength : out STD_LOGIC_VECTOR(3 downto 0);`
48			`size : out STD_LOGIC_VECTOR(3 downto 0);`
49			`amplitude : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);`
50	36	mikel262	`dovalid : out STD_LOGIC;`
51			`rd_addr : out STD_LOGIC_VECTOR(5 downto 0)`
52	25	mikel262	`);`
53			`end rle;`
54
55			`architecture rtl of rle is`
56
57
58
59			`constant SIZE_REG_C : INTEGER := 4;`
60			`constant ZEROS_32_C : UNSIGNED(31 downto 0) := (others => '0');`
61
62			`signal prev_dc_reg_0 : SIGNED(RAMDATA_W-1 downto 0);`
63			`signal prev_dc_reg_1 : SIGNED(RAMDATA_W-1 downto 0);`
64			`signal prev_dc_reg_2 : SIGNED(RAMDATA_W-1 downto 0);`
65			`signal acc_reg : SIGNED(RAMDATA_W downto 0);`
66			`signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0);`
67			`signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0);`
68			`signal runlength_reg : UNSIGNED(3 downto 0);`
69			`signal dovalid_reg : STD_LOGIC;`
70	36	mikel262	`signal zero_cnt : unsigned(5 downto 0);`
71	25	mikel262	`signal wr_cnt_d1 : unsigned(5 downto 0);`
72			`signal wr_cnt : unsigned(5 downto 0);`
73
74	36	mikel262	`signal rd_cnt : unsigned(5 downto 0);`
75			`signal rd_en : std_logic;`
76
77			`signal divalid : STD_LOGIC;`
78			`signal zrl_proc : std_logic;`
79			`signal zrl_proc_d1 : std_logic;`
80			`signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);`
81	25	mikel262	`begin`
82
83			`size <= STD_LOGIC_VECTOR(size_reg);`
84			`amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));`
85
86	36	mikel262	`rd_addr <= STD_LOGIC_VECTOR(rd_cnt);`
87
88	25	mikel262	`-------------------------------------------`
89	36	mikel262	`-- Counter1`
90			`-------------------------------------------`
91			`process(clk,rst)`
92			`begin`
93			`if rst = '1' then`
94			`rd_en <= '0';`
95			`rd_cnt <= (others => '0');`
96			`elsif clk = '1' and clk'event then`
97			`if start_pb = '1' then`
98			`rd_cnt <= (others => '0');`
99			`rd_en <= '1';`
100			`end if;`
101
102			`-- input read enable`
103			`if rd_en = '1' and zrl_proc = '0' then`
104			`if rd_cnt = 64-1 then`
105			`rd_cnt <= (others => '0');`
106			`rd_en <= '0';`
107			`else`
108			`rd_cnt <= rd_cnt + 1;`
109			`end if;`
110			`end if;`
111			`end if;`
112			`end process;`
113
114			`-------------------------------------------`
115	25	mikel262	`-- MAIN PROCESSING`
116			`-------------------------------------------`
117	36	mikel262	`process(clk,rst)`
118	25	mikel262	`begin`
119	36	mikel262	`if rst = '1' then`
120			`wr_cnt_d1 <= (others => '0');`
121			`prev_dc_reg_0 <= (others => '0');`
122			`prev_dc_reg_1 <= (others => '0');`
123			`prev_dc_reg_2 <= (others => '0');`
124			`dovalid_reg <= '0';`
125			`acc_reg <= (others => '0');`
126			`runlength_reg <= (others => '0');`
127			`runlength <= (others => '0');`
128			`dovalid <= '0';`
129			`zero_cnt <= (others => '0');`
130			`zrl_proc <= '0';`
131			`zrl_proc_d1 <= '0';`
132			`elsif clk = '1' and clk'event then`
133			`dovalid_reg <= '0';`
134			`runlength_reg <= (others => '0');`
135			`wr_cnt_d1 <= wr_cnt;`
136			`runlength <= std_logic_vector(runlength_reg);`
137			`dovalid <= dovalid_reg;`
138			`divalid <= rd_en;`
139			`zrl_proc_d1 <= zrl_proc;`
140
141			`-- input data valid`
142			`if divalid = '1' and zrl_proc_d1 = '0' then`
143			`wr_cnt <= wr_cnt + 1;`
144
145			`-- first DCT coefficient received, DC data`
146			`if wr_cnt = 0 then`
147			`-- differental coding of DC data per component`
148			`case rle_sm_settings.cmp_idx is`
149			`when "00" =>`
150			`acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);`
151			`prev_dc_reg_0 <= SIGNED(di);`
152			`when "01" =>`
153			`acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);`
154			`prev_dc_reg_1 <= SIGNED(di);`
155			`when "10" =>`
156			`acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);`
157			`prev_dc_reg_2 <= SIGNED(di);`
158			`when others =>`
159			`null;`
160			`end case;`
161			`runlength_reg <= (others => '0');`
162			`dovalid_reg <= '1';`
163			`-- AC coefficient`
164			`else`
165			`-- zero AC`
166			`if signed(di) = 0 then`
167			`-- EOB`
168			`if wr_cnt = 63 then`
169			`acc_reg <= (others => '0');`
170			`runlength_reg <= (others => '0');`
171			`dovalid_reg <= '1';`
172			`-- no EOB`
173			`else`
174			`zero_cnt <= zero_cnt + 1;`
175			`end if;`
176			`-- non-zero AC`
177	25	mikel262	`else`
178	36	mikel262	`-- normal RLE case`
179			`if zero_cnt <= 15 then`
180	25	mikel262	`acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1);`
181	36	mikel262	`runlength_reg <= zero_cnt(3 downto 0);`
182	25	mikel262	`zero_cnt <= (others => '0');`
183			`dovalid_reg <= '1';`
184	36	mikel262	`-- zero_cnt > 15`
185			`else`
186			`-- generate ZRL`
187			`acc_reg <= (others => '0');`
188			`runlength_reg <= X"F";`
189			`zero_cnt <= zero_cnt - 16;`
190			`dovalid_reg <= '1';`
191			`-- stall input until ZRL is handled`
192			`zrl_proc <= '1';`
193			`zrl_di <= di;`
194	25	mikel262	`end if;`
195			`end if;`
196			`end if;`
197	36	mikel262	`end if;`
198
199			`-- ZRL processing`
200			`if zrl_proc = '1' then`
201			`if zero_cnt <= 15 then`
202			`acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);`
203			`runlength_reg <= zero_cnt(3 downto 0);`
204			`zero_cnt <= (others => '0');`
205			`dovalid_reg <= '1';`
206			`-- continue input handling`
207			`zrl_proc <= '0';`
208			`-- zero_cnt > 15`
209			`else`
210			`-- generate ZRL`
211			`acc_reg <= (others => '0');`
212			`runlength_reg <= X"F";`
213			`zero_cnt <= zero_cnt - 16;`
214			`dovalid_reg <= '1';`
215			`end if;`
216			`end if;`
217
218			`-- start of 8x8 block processing`
219			`if start_pb = '1' then`
220			`zero_cnt <= (others => '0');`
221			`wr_cnt <= (others => '0');`
222			`end if;`
223
224			`if sof = '1' then`
225			`prev_dc_reg_0 <= (others => '0');`
226			`prev_dc_reg_1 <= (others => '0');`
227			`prev_dc_reg_2 <= (others => '0');`
228			`end if;`
229	25	mikel262
230			`end if;`
231			`end process;`
232
233			`-------------------------------------------------------------------`
234			`-- Entropy Coder`
235			`-------------------------------------------------------------------`
236			`p_entropy_coder : process(CLK, RST)`
237			`begin`
238			`if RST = '1' then`
239			`ampli_vli_reg <= (others => '0');`
240			`size_reg <= (others => '0');`
241			`elsif CLK'event and CLK = '1' then`
242			`-- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude)`
243			`-- positive input`
244			`if acc_reg >= 0 then`
245			`ampli_vli_reg <= acc_reg;`
246			`else`
247			`ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1);`
248			`end if;`
249
250			`-- compute Symbol-1 Size`
251			`if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then`
252			`size_reg <= TO_UNSIGNED(1,SIZE_REG_C);`
253			`elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then`
254			`size_reg <= TO_UNSIGNED(2,SIZE_REG_C);`
255			`elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then`
256			`size_reg <= TO_UNSIGNED(3,SIZE_REG_C);`
257			`elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then`
258			`size_reg <= TO_UNSIGNED(4,SIZE_REG_C);`
259			`elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then`
260			`size_reg <= TO_UNSIGNED(5,SIZE_REG_C);`
261			`elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then`
262			`size_reg <= TO_UNSIGNED(6,SIZE_REG_C);`
263			`elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then`
264			`size_reg <= TO_UNSIGNED(7,SIZE_REG_C);`
265			`elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then`
266			`size_reg <= TO_UNSIGNED(8,SIZE_REG_C);`
267			`elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then`
268			`size_reg <= TO_UNSIGNED(9,SIZE_REG_C);`
269			`elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then`
270			`size_reg <= TO_UNSIGNED(10,SIZE_REG_C);`
271			`elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then`
272			`size_reg <= TO_UNSIGNED(11,SIZE_REG_C);`
273			`end if;`
274
275			`-- compute Symbol-1 Size`
276			`-- positive input`
277			`if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then`
278			`size_reg <= TO_UNSIGNED(1,SIZE_REG_C);`
279			`elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then`
280			`size_reg <= TO_UNSIGNED(2,SIZE_REG_C);`
281			`elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then`
282			`size_reg <= TO_UNSIGNED(3,SIZE_REG_C);`
283			`elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then`
284			`size_reg <= TO_UNSIGNED(4,SIZE_REG_C);`
285			`elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then`
286			`size_reg <= TO_UNSIGNED(5,SIZE_REG_C);`
287			`elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then`
288			`size_reg <= TO_UNSIGNED(6,SIZE_REG_C);`
289			`elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then`
290			`size_reg <= TO_UNSIGNED(7,SIZE_REG_C);`
291			`elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then`
292			`size_reg <= TO_UNSIGNED(8,SIZE_REG_C);`
293			`elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then`
294			`size_reg <= TO_UNSIGNED(9,SIZE_REG_C);`
295			`elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then`
296			`size_reg <= TO_UNSIGNED(10,SIZE_REG_C);`
297			`elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then`
298			`size_reg <= TO_UNSIGNED(11,SIZE_REG_C);`
299			`end if;`
300
301			`-- DC coefficient amplitude=0 case OR EOB`
302			`if acc_reg = 0 then`
303			`size_reg <= TO_UNSIGNED(0,SIZE_REG_C);`
304			`end if;`
305			`end if;`
306			`end process;`
307
308			`end rtl;`
309			`--------------------------------------------------------------------------------`
310
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