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--------------------------------------------------------------------------------
--                                                                            --
--                          V H D L    F I L E                                --
--                          COPYRIGHT (C) 2009                                --
--                                                                            --
--------------------------------------------------------------------------------
--                                                                            --
-- Title       : RLE                                                          --
-- Design      : MDCT CORE                                                    --
-- Author      : Michal Krepa                                                 --
--                                                                            --
--------------------------------------------------------------------------------
--                                                                            --
-- File        : RLE.VHD                                                      --
-- Created     : Wed Mar 04 2009                                              --
--                                                                            --
--------------------------------------------------------------------------------
--                                                                            --
--  Description : Run Length Encoder                                          --
--                Baseline Entropy Coding                                     --
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
library IEEE;
  use IEEE.STD_LOGIC_1164.All;
  use IEEE.NUMERIC_STD.all;
 
library work;
  use work.JPEG_PKG.all;
 
entity rle is
  generic
    (
      RAMADDR_W     : INTEGER := 6;
      RAMDATA_W     : INTEGER := 12
    );
  port
    (
      rst        : in  STD_LOGIC;
      clk        : in  STD_LOGIC;
      di         : in  STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
      start_pb   : in  std_logic;
      sof        : in  std_logic;
      rle_sm_settings : in T_SM_SETTINGS;
 
      runlength  : out STD_LOGIC_VECTOR(3 downto 0);
      size       : out STD_LOGIC_VECTOR(3 downto 0);
      amplitude  : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
      dovalid    : out STD_LOGIC;
      rd_addr    : out STD_LOGIC_VECTOR(5 downto 0)
    );
end rle;
 
architecture rtl of rle is
 
 
 
  constant SIZE_REG_C      : INTEGER := 4;
  constant ZEROS_32_C      : UNSIGNED(31 downto 0) := (others => '0');
 
  signal prev_dc_reg_0   : SIGNED(RAMDATA_W-1 downto 0);
  signal prev_dc_reg_1   : SIGNED(RAMDATA_W-1 downto 0);
  signal prev_dc_reg_2   : SIGNED(RAMDATA_W-1 downto 0);
  signal acc_reg         : SIGNED(RAMDATA_W downto 0);
  signal size_reg        : UNSIGNED(SIZE_REG_C-1 downto 0);
  signal ampli_vli_reg   : SIGNED(RAMDATA_W downto 0);
  signal runlength_reg   : UNSIGNED(3 downto 0);
  signal dovalid_reg     : STD_LOGIC;
  signal zero_cnt        : unsigned(5 downto 0);
  signal wr_cnt_d1       : unsigned(5 downto 0);
  signal wr_cnt          : unsigned(5 downto 0);
 
  signal rd_cnt         : unsigned(5 downto 0);
  signal rd_en          : std_logic;
 
  signal divalid        : STD_LOGIC;
  signal zrl_proc       : std_logic;
  signal zrl_di         : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
begin
 
  size      <= STD_LOGIC_VECTOR(size_reg);
  amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
 
  rd_addr <= STD_LOGIC_VECTOR(rd_cnt);
 
  -------------------------------------------
  -- MAIN PROCESSING
  -------------------------------------------
  process(clk,rst)
  begin
    if rst = '1' then
      wr_cnt_d1       <= (others => '0');
      prev_dc_reg_0   <= (others => '0');
      prev_dc_reg_1   <= (others => '0');
      prev_dc_reg_2   <= (others => '0');
      dovalid_reg     <= '0';
      acc_reg         <= (others => '0');
      runlength_reg   <= (others => '0');
      runlength       <= (others => '0');
      dovalid         <= '0';
      zero_cnt        <= (others => '0');
      zrl_proc        <= '0';
      rd_en           <= '0';
      rd_cnt          <= (others => '0');
    elsif clk = '1' and clk'event then
      dovalid_reg     <= '0';
      runlength_reg   <= (others => '0');
      wr_cnt_d1       <= wr_cnt;
      runlength       <= std_logic_vector(runlength_reg);
      dovalid         <= dovalid_reg;
      divalid         <= rd_en;
 
      if start_pb = '1' then
        rd_cnt <= (others => '0');
        rd_en <= '1';
      end if;
 
      -- input read enable
      if rd_en = '1' then
        if rd_cnt = 64-1 then
          rd_cnt <= (others => '0');
          rd_en  <= '0';
        else
          rd_cnt <= rd_cnt + 1;
        end if;
      end if;
 
      -- input data valid
      if divalid = '1' then
        wr_cnt <= wr_cnt + 1;
 
        -- first DCT coefficient received, DC data
        if wr_cnt = 0 then
          -- differental coding of DC data per component
          case rle_sm_settings.cmp_idx is
            when "00" =>
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
              prev_dc_reg_0 <= SIGNED(di);
            when "01" =>
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
              prev_dc_reg_1 <= SIGNED(di);
            when "10" =>
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
              prev_dc_reg_2 <= SIGNED(di);
            when others =>
              null;
          end case;
          runlength_reg    <= (others => '0');
          dovalid_reg      <= '1';
        -- AC coefficient
        else
          -- zero AC
          if signed(di) = 0 then
            -- EOB
            if wr_cnt = 63 then
              acc_reg          <= (others => '0');
              runlength_reg    <= (others => '0');
              dovalid_reg      <= '1';
            -- no EOB
            else
              zero_cnt <= zero_cnt + 1;
            end if;
          -- non-zero AC
          else
            -- normal RLE case
            if zero_cnt <= 15 then
              acc_reg        <= RESIZE(SIGNED(di),RAMDATA_W+1);
              runlength_reg  <= zero_cnt(3 downto 0);
              zero_cnt       <= (others => '0');
              dovalid_reg    <= '1';
            -- zero_cnt > 15
            else
              -- generate ZRL
              acc_reg        <= (others => '0');
              runlength_reg  <= X"F";
              zero_cnt       <= zero_cnt - 16;
              dovalid_reg    <= '1';
              -- stall input until ZRL is handled
              zrl_proc       <= '1';
              zrl_di         <= di;
              divalid <= '0';
              rd_cnt  <= rd_cnt;
            end if;
          end if;
        end if;
      end if;
 
      -- ZRL processing
      if zrl_proc = '1' then
        if zero_cnt <= 15 then
          acc_reg        <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);
          runlength_reg  <= zero_cnt(3 downto 0);
          if signed(zrl_di) = 0 then
            zero_cnt     <= to_unsigned(1,zero_cnt'length);
          else
            zero_cnt     <= (others => '0');
          end if;
          dovalid_reg    <= '1';
          divalid <= '1';
          -- continue input handling
          zrl_proc <= '0';
        -- zero_cnt > 15
        else
          -- generate ZRL
          acc_reg        <= (others => '0');
          runlength_reg  <= X"F";
          zero_cnt       <= zero_cnt - 16;
          dovalid_reg    <= '1';
          divalid <= '0';
          rd_cnt <= rd_cnt;
        end if;
      end if;
 
      -- start of 8x8 block processing
      if start_pb = '1' then
        zero_cnt <= (others => '0');
        wr_cnt   <= (others => '0');
      end if;
 
      if sof = '1' then
        prev_dc_reg_0 <= (others => '0');
        prev_dc_reg_1 <= (others => '0');
        prev_dc_reg_2 <= (others => '0');
      end if;
 
    end if;
  end process;
 
  -------------------------------------------------------------------
  -- Entropy Coder
  -------------------------------------------------------------------
  p_entropy_coder : process(CLK, RST)
  begin
    if RST = '1' then
      ampli_vli_reg <= (others => '0');
      size_reg      <= (others => '0');
    elsif CLK'event and CLK = '1' then
      -- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude)
      -- positive input
      if acc_reg >= 0 then
        ampli_vli_reg <= acc_reg;
      else
        ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1);
      end if;
 
      -- compute Symbol-1 Size
      if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then
        size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
      end if;
 
      -- compute Symbol-1 Size
      -- positive input
      if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then
        size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
      end if;
 
      -- DC coefficient amplitude=0 case OR EOB
      if acc_reg = 0 then
         size_reg <= TO_UNSIGNED(0,SIZE_REG_C);
      end if;
    end if;
  end process;
 
end rtl;
--------------------------------------------------------------------------------
 
 

Line No.	Rev	Author	Line
1	25	mikel262	`--------------------------------------------------------------------------------`
2			`-- --`
3			`-- V H D L F I L E --`
4			`-- COPYRIGHT (C) 2009 --`
5			`-- --`
6			`--------------------------------------------------------------------------------`
7			`-- --`
8			`-- Title : RLE --`
9			`-- Design : MDCT CORE --`
10			`-- Author : Michal Krepa --`
11			`-- --`
12			`--------------------------------------------------------------------------------`
13			`-- --`
14			`-- File : RLE.VHD --`
15			`-- Created : Wed Mar 04 2009 --`
16			`-- --`
17			`--------------------------------------------------------------------------------`
18			`-- --`
19			`-- Description : Run Length Encoder --`
20			`-- Baseline Entropy Coding --`
21			`--------------------------------------------------------------------------------`
22
23			`--------------------------------------------------------------------------------`
24
25			`library IEEE;`
26			`use IEEE.STD_LOGIC_1164.All;`
27			`use IEEE.NUMERIC_STD.all;`
28
29			`library work;`
30			`use work.JPEG_PKG.all;`
31
32			`entity rle is`
33			`generic`
34			`(`
35			`RAMADDR_W : INTEGER := 6;`
36			`RAMDATA_W : INTEGER := 12`
37			`);`
38			`port`
39			`(`
40			`rst : in STD_LOGIC;`
41			`clk : in STD_LOGIC;`
42			`di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);`
43			`start_pb : in std_logic;`
44			`sof : in std_logic;`
45			`rle_sm_settings : in T_SM_SETTINGS;`
46
47			`runlength : out STD_LOGIC_VECTOR(3 downto 0);`
48			`size : out STD_LOGIC_VECTOR(3 downto 0);`
49			`amplitude : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);`
50	36	mikel262	`dovalid : out STD_LOGIC;`
51			`rd_addr : out STD_LOGIC_VECTOR(5 downto 0)`
52	25	mikel262	`);`
53			`end rle;`
54
55			`architecture rtl of rle is`
56
57
58
59			`constant SIZE_REG_C : INTEGER := 4;`
60			`constant ZEROS_32_C : UNSIGNED(31 downto 0) := (others => '0');`
61
62			`signal prev_dc_reg_0 : SIGNED(RAMDATA_W-1 downto 0);`
63			`signal prev_dc_reg_1 : SIGNED(RAMDATA_W-1 downto 0);`
64			`signal prev_dc_reg_2 : SIGNED(RAMDATA_W-1 downto 0);`
65			`signal acc_reg : SIGNED(RAMDATA_W downto 0);`
66			`signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0);`
67			`signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0);`
68			`signal runlength_reg : UNSIGNED(3 downto 0);`
69			`signal dovalid_reg : STD_LOGIC;`
70	36	mikel262	`signal zero_cnt : unsigned(5 downto 0);`
71	25	mikel262	`signal wr_cnt_d1 : unsigned(5 downto 0);`
72			`signal wr_cnt : unsigned(5 downto 0);`
73
74	36	mikel262	`signal rd_cnt : unsigned(5 downto 0);`
75			`signal rd_en : std_logic;`
76
77			`signal divalid : STD_LOGIC;`
78			`signal zrl_proc : std_logic;`
79			`signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);`
80	25	mikel262	`begin`
81
82			`size <= STD_LOGIC_VECTOR(size_reg);`
83			`amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));`
84
85	36	mikel262	`rd_addr <= STD_LOGIC_VECTOR(rd_cnt);`
86
87			`-------------------------------------------`
88	25	mikel262	`-- MAIN PROCESSING`
89			`-------------------------------------------`
90	36	mikel262	`process(clk,rst)`
91	25	mikel262	`begin`
92	36	mikel262	`if rst = '1' then`
93			`wr_cnt_d1 <= (others => '0');`
94			`prev_dc_reg_0 <= (others => '0');`
95			`prev_dc_reg_1 <= (others => '0');`
96			`prev_dc_reg_2 <= (others => '0');`
97			`dovalid_reg <= '0';`
98			`acc_reg <= (others => '0');`
99			`runlength_reg <= (others => '0');`
100			`runlength <= (others => '0');`
101			`dovalid <= '0';`
102			`zero_cnt <= (others => '0');`
103			`zrl_proc <= '0';`
104	40	mikel262	`rd_en <= '0';`
105			`rd_cnt <= (others => '0');`
106	36	mikel262	`elsif clk = '1' and clk'event then`
107			`dovalid_reg <= '0';`
108			`runlength_reg <= (others => '0');`
109			`wr_cnt_d1 <= wr_cnt;`
110			`runlength <= std_logic_vector(runlength_reg);`
111			`dovalid <= dovalid_reg;`
112			`divalid <= rd_en;`
113	40	mikel262
114			`if start_pb = '1' then`
115			`rd_cnt <= (others => '0');`
116			`rd_en <= '1';`
117			`end if;`
118
119			`-- input read enable`
120			`if rd_en = '1' then`
121			`if rd_cnt = 64-1 then`
122			`rd_cnt <= (others => '0');`
123			`rd_en <= '0';`
124			`else`
125			`rd_cnt <= rd_cnt + 1;`
126			`end if;`
127			`end if;`
128	36	mikel262
129			`-- input data valid`
130	40	mikel262	`if divalid = '1' then`
131	36	mikel262	`wr_cnt <= wr_cnt + 1;`
132
133			`-- first DCT coefficient received, DC data`
134			`if wr_cnt = 0 then`
135			`-- differental coding of DC data per component`
136			`case rle_sm_settings.cmp_idx is`
137			`when "00" =>`
138			`acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);`
139			`prev_dc_reg_0 <= SIGNED(di);`
140			`when "01" =>`
141			`acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);`
142			`prev_dc_reg_1 <= SIGNED(di);`
143			`when "10" =>`
144			`acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);`
145			`prev_dc_reg_2 <= SIGNED(di);`
146			`when others =>`
147			`null;`
148			`end case;`
149			`runlength_reg <= (others => '0');`
150			`dovalid_reg <= '1';`
151			`-- AC coefficient`
152			`else`
153			`-- zero AC`
154			`if signed(di) = 0 then`
155			`-- EOB`
156			`if wr_cnt = 63 then`
157			`acc_reg <= (others => '0');`
158			`runlength_reg <= (others => '0');`
159			`dovalid_reg <= '1';`
160			`-- no EOB`
161			`else`
162			`zero_cnt <= zero_cnt + 1;`
163			`end if;`
164			`-- non-zero AC`
165	25	mikel262	`else`
166	36	mikel262	`-- normal RLE case`
167			`if zero_cnt <= 15 then`
168	25	mikel262	`acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1);`
169	36	mikel262	`runlength_reg <= zero_cnt(3 downto 0);`
170	25	mikel262	`zero_cnt <= (others => '0');`
171			`dovalid_reg <= '1';`
172	36	mikel262	`-- zero_cnt > 15`
173			`else`
174			`-- generate ZRL`
175			`acc_reg <= (others => '0');`
176			`runlength_reg <= X"F";`
177			`zero_cnt <= zero_cnt - 16;`
178			`dovalid_reg <= '1';`
179			`-- stall input until ZRL is handled`
180			`zrl_proc <= '1';`
181			`zrl_di <= di;`
182	40	mikel262	`divalid <= '0';`
183			`rd_cnt <= rd_cnt;`
184	25	mikel262	`end if;`
185			`end if;`
186			`end if;`
187	36	mikel262	`end if;`
188
189			`-- ZRL processing`
190			`if zrl_proc = '1' then`
191			`if zero_cnt <= 15 then`
192			`acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);`
193			`runlength_reg <= zero_cnt(3 downto 0);`
194	40	mikel262	`if signed(zrl_di) = 0 then`
195	39	mikel262	`zero_cnt <= to_unsigned(1,zero_cnt'length);`
196			`else`
197			`zero_cnt <= (others => '0');`
198			`end if;`
199	36	mikel262	`dovalid_reg <= '1';`
200	40	mikel262	`divalid <= '1';`
201	36	mikel262	`-- continue input handling`
202			`zrl_proc <= '0';`
203			`-- zero_cnt > 15`
204			`else`
205			`-- generate ZRL`
206			`acc_reg <= (others => '0');`
207			`runlength_reg <= X"F";`
208			`zero_cnt <= zero_cnt - 16;`
209			`dovalid_reg <= '1';`
210	40	mikel262	`divalid <= '0';`
211			`rd_cnt <= rd_cnt;`
212	36	mikel262	`end if;`
213			`end if;`
214
215			`-- start of 8x8 block processing`
216			`if start_pb = '1' then`
217			`zero_cnt <= (others => '0');`
218			`wr_cnt <= (others => '0');`
219			`end if;`
220
221			`if sof = '1' then`
222			`prev_dc_reg_0 <= (others => '0');`
223			`prev_dc_reg_1 <= (others => '0');`
224			`prev_dc_reg_2 <= (others => '0');`
225			`end if;`
226	25	mikel262
227			`end if;`
228			`end process;`
229
230			`-------------------------------------------------------------------`
231			`-- Entropy Coder`
232			`-------------------------------------------------------------------`
233			`p_entropy_coder : process(CLK, RST)`
234			`begin`
235			`if RST = '1' then`
236			`ampli_vli_reg <= (others => '0');`
237			`size_reg <= (others => '0');`
238			`elsif CLK'event and CLK = '1' then`
239			`-- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude)`
240			`-- positive input`
241			`if acc_reg >= 0 then`
242			`ampli_vli_reg <= acc_reg;`
243			`else`
244			`ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1);`
245			`end if;`
246
247			`-- compute Symbol-1 Size`
248			`if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then`
249			`size_reg <= TO_UNSIGNED(1,SIZE_REG_C);`
250			`elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then`
251			`size_reg <= TO_UNSIGNED(2,SIZE_REG_C);`
252			`elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then`
253			`size_reg <= TO_UNSIGNED(3,SIZE_REG_C);`
254			`elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then`
255			`size_reg <= TO_UNSIGNED(4,SIZE_REG_C);`
256			`elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then`
257			`size_reg <= TO_UNSIGNED(5,SIZE_REG_C);`
258			`elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then`
259			`size_reg <= TO_UNSIGNED(6,SIZE_REG_C);`
260			`elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then`
261			`size_reg <= TO_UNSIGNED(7,SIZE_REG_C);`
262			`elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then`
263			`size_reg <= TO_UNSIGNED(8,SIZE_REG_C);`
264			`elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then`
265			`size_reg <= TO_UNSIGNED(9,SIZE_REG_C);`
266			`elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then`
267			`size_reg <= TO_UNSIGNED(10,SIZE_REG_C);`
268			`elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then`
269			`size_reg <= TO_UNSIGNED(11,SIZE_REG_C);`
270			`end if;`
271
272			`-- compute Symbol-1 Size`
273			`-- positive input`
274			`if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then`
275			`size_reg <= TO_UNSIGNED(1,SIZE_REG_C);`
276			`elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then`
277			`size_reg <= TO_UNSIGNED(2,SIZE_REG_C);`
278			`elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then`
279			`size_reg <= TO_UNSIGNED(3,SIZE_REG_C);`
280			`elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then`
281			`size_reg <= TO_UNSIGNED(4,SIZE_REG_C);`
282			`elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then`
283			`size_reg <= TO_UNSIGNED(5,SIZE_REG_C);`
284			`elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then`
285			`size_reg <= TO_UNSIGNED(6,SIZE_REG_C);`
286			`elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then`
287			`size_reg <= TO_UNSIGNED(7,SIZE_REG_C);`
288			`elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then`
289			`size_reg <= TO_UNSIGNED(8,SIZE_REG_C);`
290			`elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then`
291			`size_reg <= TO_UNSIGNED(9,SIZE_REG_C);`
292			`elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then`
293			`size_reg <= TO_UNSIGNED(10,SIZE_REG_C);`
294			`elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then`
295			`size_reg <= TO_UNSIGNED(11,SIZE_REG_C);`
296			`end if;`
297
298			`-- DC coefficient amplitude=0 case OR EOB`
299			`if acc_reg = 0 then`
300			`size_reg <= TO_UNSIGNED(0,SIZE_REG_C);`
301			`end if;`
302			`end if;`
303			`end process;`
304
305			`end rtl;`
306			`--------------------------------------------------------------------------------`
307
308

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