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--------------------------------------------------------------------------------
--                                                                            --
--                          V H D L    F I L E                                --
--                          COPYRIGHT (C) 2009                                --
--                                                                            --
--------------------------------------------------------------------------------
--                                                                            --
-- Title       : RLE                                                          --
-- Design      : MDCT CORE                                                    --
-- Author      : Michal Krepa                                                 --
--                                                                            --
--------------------------------------------------------------------------------
--                                                                            --
-- File        : RLE.VHD                                                      --
-- Created     : Wed Mar 04 2009                                              --
--                                                                            --
--------------------------------------------------------------------------------
--                                                                            --
--  Description : Run Length Encoder                                          --
--                Baseline Entropy Coding                                     --
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
library IEEE;
  use IEEE.STD_LOGIC_1164.All;
  use IEEE.NUMERIC_STD.all;
 
library work;
  use work.JPEG_PKG.all;
 
entity rle is
  generic
    (
      RAMADDR_W     : INTEGER := 6;
      RAMDATA_W     : INTEGER := 12
    );
  port
    (
      rst        : in  STD_LOGIC;
      clk        : in  STD_LOGIC;
      di         : in  STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
      start_pb   : in  std_logic;
      sof        : in  std_logic;
      rle_sm_settings : in T_SM_SETTINGS;
 
      runlength  : out STD_LOGIC_VECTOR(3 downto 0);
      size       : out STD_LOGIC_VECTOR(3 downto 0);
      amplitude  : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
      dovalid    : out STD_LOGIC;
      rd_addr    : out STD_LOGIC_VECTOR(5 downto 0)
    );
end rle;
 
architecture rtl of rle is
 
 
 
  constant SIZE_REG_C      : INTEGER := 4;
  constant ZEROS_32_C      : UNSIGNED(31 downto 0) := (others => '0');
 
  signal prev_dc_reg_0   : SIGNED(RAMDATA_W-1 downto 0);
  signal prev_dc_reg_1   : SIGNED(RAMDATA_W-1 downto 0);
  signal prev_dc_reg_2   : SIGNED(RAMDATA_W-1 downto 0);
  signal acc_reg         : SIGNED(RAMDATA_W downto 0);
  signal size_reg        : UNSIGNED(SIZE_REG_C-1 downto 0);
  signal ampli_vli_reg   : SIGNED(RAMDATA_W downto 0);
  signal runlength_reg   : UNSIGNED(3 downto 0);
  signal dovalid_reg     : STD_LOGIC;
  signal zero_cnt        : unsigned(5 downto 0);
  signal wr_cnt_d1       : unsigned(5 downto 0);
  signal wr_cnt          : unsigned(5 downto 0);
 
  signal rd_cnt         : unsigned(5 downto 0);
  signal rd_en          : std_logic;
 
  signal divalid        : STD_LOGIC;
  signal divalid_en     : std_logic;
  signal zrl_proc       : std_logic;
  signal zrl_di         : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
begin
 
  size      <= STD_LOGIC_VECTOR(size_reg);
  amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));
 
  rd_addr <= STD_LOGIC_VECTOR(rd_cnt);
 
  -------------------------------------------
  -- MAIN PROCESSING
  -------------------------------------------
  process(clk,rst)
  begin
    if rst = '1' then
      wr_cnt_d1       <= (others => '0');
      prev_dc_reg_0   <= (others => '0');
      prev_dc_reg_1   <= (others => '0');
      prev_dc_reg_2   <= (others => '0');
      dovalid_reg     <= '0';
      acc_reg         <= (others => '0');
      runlength_reg   <= (others => '0');
      runlength       <= (others => '0');
      dovalid         <= '0';
      zero_cnt        <= (others => '0');
      zrl_proc        <= '0';
      rd_en           <= '0';
      rd_cnt          <= (others => '0');
      divalid_en      <= '0';
    elsif clk = '1' and clk'event then
      dovalid_reg     <= '0';
      runlength_reg   <= (others => '0');
      wr_cnt_d1       <= wr_cnt;
      runlength       <= std_logic_vector(runlength_reg);
      dovalid         <= dovalid_reg;
      divalid         <= rd_en;
 
      if start_pb = '1' then
        rd_cnt     <= (others => '0');
        rd_en      <= '1';
        divalid_en <= '1';
      end if;
 
      if divalid = '1' and wr_cnt = 63 then
        divalid_en <= '0';
      end if;
 
      -- input read enable
      if rd_en = '1' then
        if rd_cnt = 64-1 then
          rd_cnt <= (others => '0');
          rd_en  <= '0';
        else
          rd_cnt <= rd_cnt + 1;
        end if;
      end if;
 
      -- input data valid
      if divalid = '1' then
        wr_cnt <= wr_cnt + 1;
 
        -- first DCT coefficient received, DC data
        if wr_cnt = 0 then
          -- differental coding of DC data per component
          case rle_sm_settings.cmp_idx is
            when "00" =>
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);
              prev_dc_reg_0 <= SIGNED(di);
            when "01" =>
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);
              prev_dc_reg_1 <= SIGNED(di);
            when "10" =>
              acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);
              prev_dc_reg_2 <= SIGNED(di);
            when others =>
              null;
          end case;
          runlength_reg    <= (others => '0');
          dovalid_reg      <= '1';
        -- AC coefficient
        else
          -- zero AC
          if signed(di) = 0 then
            -- EOB
            if wr_cnt = 63 then
              acc_reg          <= (others => '0');
              runlength_reg    <= (others => '0');
              dovalid_reg      <= '1';
            -- no EOB
            else
              zero_cnt <= zero_cnt + 1;
            end if;
          -- non-zero AC
          else
            -- normal RLE case
            if zero_cnt <= 15 then
              acc_reg        <= RESIZE(SIGNED(di),RAMDATA_W+1);
              runlength_reg  <= zero_cnt(3 downto 0);
              zero_cnt       <= (others => '0');
              dovalid_reg    <= '1';
            -- zero_cnt > 15
            else
              -- generate ZRL
              acc_reg        <= (others => '0');
              runlength_reg  <= X"F";
              zero_cnt       <= zero_cnt - 16;
              dovalid_reg    <= '1';
              -- stall input until ZRL is handled
              zrl_proc       <= '1';
              zrl_di         <= di;
              divalid <= '0';
              rd_cnt  <= rd_cnt;
            end if;
          end if;
        end if;
      end if;
 
      -- ZRL processing
      if zrl_proc = '1' then
        if zero_cnt <= 15 then
          acc_reg        <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);
          runlength_reg  <= zero_cnt(3 downto 0);
          if signed(zrl_di) = 0 then
            zero_cnt     <= to_unsigned(1,zero_cnt'length);
          else
            zero_cnt     <= (others => '0');
          end if;
          dovalid_reg    <= '1';
          divalid <= divalid_en;
          -- continue input handling
          zrl_proc <= '0';
        -- zero_cnt > 15
        else
          -- generate ZRL
          acc_reg        <= (others => '0');
          runlength_reg  <= X"F";
          zero_cnt       <= zero_cnt - 16;
          dovalid_reg    <= '1';
          divalid <= '0';
          rd_cnt <= rd_cnt;
        end if;
      end if;
 
      -- start of 8x8 block processing
      if start_pb = '1' then
        zero_cnt <= (others => '0');
        wr_cnt   <= (others => '0');
      end if;
 
      if sof = '1' then
        prev_dc_reg_0 <= (others => '0');
        prev_dc_reg_1 <= (others => '0');
        prev_dc_reg_2 <= (others => '0');
      end if;
 
    end if;
  end process;
 
  -------------------------------------------------------------------
  -- Entropy Coder
  -------------------------------------------------------------------
  p_entropy_coder : process(CLK, RST)
  begin
    if RST = '1' then
      ampli_vli_reg <= (others => '0');
      size_reg      <= (others => '0');
    elsif CLK'event and CLK = '1' then
      -- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude)
      -- positive input
      if acc_reg >= 0 then
        ampli_vli_reg <= acc_reg;
      else
        ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1);
      end if;
 
      -- compute Symbol-1 Size
      if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then
        size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
      elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
      end if;
 
      -- compute Symbol-1 Size
      -- positive input
      if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then
        size_reg <= TO_UNSIGNED(1,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(2,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(3,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(4,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(5,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(6,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(7,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(8,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(9,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(10,SIZE_REG_C);
      elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then
        size_reg <= TO_UNSIGNED(11,SIZE_REG_C);
      end if;
 
      -- DC coefficient amplitude=0 case OR EOB
      if acc_reg = 0 then
         size_reg <= TO_UNSIGNED(0,SIZE_REG_C);
      end if;
    end if;
  end process;
 
end rtl;
--------------------------------------------------------------------------------
 
 

Line No.	Rev	Author	Line
1	25	mikel262	`--------------------------------------------------------------------------------`
2			`-- --`
3			`-- V H D L F I L E --`
4			`-- COPYRIGHT (C) 2009 --`
5			`-- --`
6			`--------------------------------------------------------------------------------`
7			`-- --`
8			`-- Title : RLE --`
9			`-- Design : MDCT CORE --`
10			`-- Author : Michal Krepa --`
11			`-- --`
12			`--------------------------------------------------------------------------------`
13			`-- --`
14			`-- File : RLE.VHD --`
15			`-- Created : Wed Mar 04 2009 --`
16			`-- --`
17			`--------------------------------------------------------------------------------`
18			`-- --`
19			`-- Description : Run Length Encoder --`
20			`-- Baseline Entropy Coding --`
21			`--------------------------------------------------------------------------------`
22
23			`--------------------------------------------------------------------------------`
24
25			`library IEEE;`
26			`use IEEE.STD_LOGIC_1164.All;`
27			`use IEEE.NUMERIC_STD.all;`
28
29			`library work;`
30			`use work.JPEG_PKG.all;`
31
32			`entity rle is`
33			`generic`
34			`(`
35			`RAMADDR_W : INTEGER := 6;`
36			`RAMDATA_W : INTEGER := 12`
37			`);`
38			`port`
39			`(`
40			`rst : in STD_LOGIC;`
41			`clk : in STD_LOGIC;`
42			`di : in STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);`
43			`start_pb : in std_logic;`
44			`sof : in std_logic;`
45			`rle_sm_settings : in T_SM_SETTINGS;`
46
47			`runlength : out STD_LOGIC_VECTOR(3 downto 0);`
48			`size : out STD_LOGIC_VECTOR(3 downto 0);`
49			`amplitude : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);`
50	36	mikel262	`dovalid : out STD_LOGIC;`
51			`rd_addr : out STD_LOGIC_VECTOR(5 downto 0)`
52	25	mikel262	`);`
53			`end rle;`
54
55			`architecture rtl of rle is`
56
57
58
59			`constant SIZE_REG_C : INTEGER := 4;`
60			`constant ZEROS_32_C : UNSIGNED(31 downto 0) := (others => '0');`
61
62			`signal prev_dc_reg_0 : SIGNED(RAMDATA_W-1 downto 0);`
63			`signal prev_dc_reg_1 : SIGNED(RAMDATA_W-1 downto 0);`
64			`signal prev_dc_reg_2 : SIGNED(RAMDATA_W-1 downto 0);`
65			`signal acc_reg : SIGNED(RAMDATA_W downto 0);`
66			`signal size_reg : UNSIGNED(SIZE_REG_C-1 downto 0);`
67			`signal ampli_vli_reg : SIGNED(RAMDATA_W downto 0);`
68			`signal runlength_reg : UNSIGNED(3 downto 0);`
69			`signal dovalid_reg : STD_LOGIC;`
70	36	mikel262	`signal zero_cnt : unsigned(5 downto 0);`
71	25	mikel262	`signal wr_cnt_d1 : unsigned(5 downto 0);`
72			`signal wr_cnt : unsigned(5 downto 0);`
73
74	36	mikel262	`signal rd_cnt : unsigned(5 downto 0);`
75			`signal rd_en : std_logic;`
76
77			`signal divalid : STD_LOGIC;`
78	41	mikel262	`signal divalid_en : std_logic;`
79	36	mikel262	`signal zrl_proc : std_logic;`
80			`signal zrl_di : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);`
81	25	mikel262	`begin`
82
83			`size <= STD_LOGIC_VECTOR(size_reg);`
84			`amplitude <= STD_LOGIC_VECTOR(ampli_vli_reg(11 downto 0));`
85
86	36	mikel262	`rd_addr <= STD_LOGIC_VECTOR(rd_cnt);`
87
88			`-------------------------------------------`
89	25	mikel262	`-- MAIN PROCESSING`
90			`-------------------------------------------`
91	36	mikel262	`process(clk,rst)`
92	25	mikel262	`begin`
93	36	mikel262	`if rst = '1' then`
94			`wr_cnt_d1 <= (others => '0');`
95			`prev_dc_reg_0 <= (others => '0');`
96			`prev_dc_reg_1 <= (others => '0');`
97			`prev_dc_reg_2 <= (others => '0');`
98			`dovalid_reg <= '0';`
99			`acc_reg <= (others => '0');`
100			`runlength_reg <= (others => '0');`
101			`runlength <= (others => '0');`
102			`dovalid <= '0';`
103			`zero_cnt <= (others => '0');`
104			`zrl_proc <= '0';`
105	40	mikel262	`rd_en <= '0';`
106			`rd_cnt <= (others => '0');`
107	41	mikel262	`divalid_en <= '0';`
108	36	mikel262	`elsif clk = '1' and clk'event then`
109			`dovalid_reg <= '0';`
110			`runlength_reg <= (others => '0');`
111			`wr_cnt_d1 <= wr_cnt;`
112			`runlength <= std_logic_vector(runlength_reg);`
113			`dovalid <= dovalid_reg;`
114			`divalid <= rd_en;`
115	40	mikel262
116			`if start_pb = '1' then`
117	41	mikel262	`rd_cnt <= (others => '0');`
118			`rd_en <= '1';`
119			`divalid_en <= '1';`
120	40	mikel262	`end if;`
121
122	41	mikel262	`if divalid = '1' and wr_cnt = 63 then`
123			`divalid_en <= '0';`
124			`end if;`
125
126	40	mikel262	`-- input read enable`
127			`if rd_en = '1' then`
128			`if rd_cnt = 64-1 then`
129			`rd_cnt <= (others => '0');`
130			`rd_en <= '0';`
131			`else`
132			`rd_cnt <= rd_cnt + 1;`
133			`end if;`
134			`end if;`
135	36	mikel262
136			`-- input data valid`
137	40	mikel262	`if divalid = '1' then`
138	36	mikel262	`wr_cnt <= wr_cnt + 1;`
139
140			`-- first DCT coefficient received, DC data`
141			`if wr_cnt = 0 then`
142			`-- differental coding of DC data per component`
143			`case rle_sm_settings.cmp_idx is`
144			`when "00" =>`
145			`acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_0,RAMDATA_W+1);`
146			`prev_dc_reg_0 <= SIGNED(di);`
147			`when "01" =>`
148			`acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_1,RAMDATA_W+1);`
149			`prev_dc_reg_1 <= SIGNED(di);`
150			`when "10" =>`
151			`acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1) - RESIZE(prev_dc_reg_2,RAMDATA_W+1);`
152			`prev_dc_reg_2 <= SIGNED(di);`
153			`when others =>`
154			`null;`
155			`end case;`
156			`runlength_reg <= (others => '0');`
157			`dovalid_reg <= '1';`
158			`-- AC coefficient`
159			`else`
160			`-- zero AC`
161			`if signed(di) = 0 then`
162			`-- EOB`
163			`if wr_cnt = 63 then`
164			`acc_reg <= (others => '0');`
165			`runlength_reg <= (others => '0');`
166			`dovalid_reg <= '1';`
167			`-- no EOB`
168			`else`
169			`zero_cnt <= zero_cnt + 1;`
170			`end if;`
171			`-- non-zero AC`
172	25	mikel262	`else`
173	36	mikel262	`-- normal RLE case`
174			`if zero_cnt <= 15 then`
175	25	mikel262	`acc_reg <= RESIZE(SIGNED(di),RAMDATA_W+1);`
176	36	mikel262	`runlength_reg <= zero_cnt(3 downto 0);`
177	25	mikel262	`zero_cnt <= (others => '0');`
178			`dovalid_reg <= '1';`
179	36	mikel262	`-- zero_cnt > 15`
180			`else`
181			`-- generate ZRL`
182			`acc_reg <= (others => '0');`
183			`runlength_reg <= X"F";`
184			`zero_cnt <= zero_cnt - 16;`
185			`dovalid_reg <= '1';`
186			`-- stall input until ZRL is handled`
187			`zrl_proc <= '1';`
188			`zrl_di <= di;`
189	40	mikel262	`divalid <= '0';`
190			`rd_cnt <= rd_cnt;`
191	25	mikel262	`end if;`
192			`end if;`
193			`end if;`
194	36	mikel262	`end if;`
195
196			`-- ZRL processing`
197			`if zrl_proc = '1' then`
198			`if zero_cnt <= 15 then`
199			`acc_reg <= RESIZE(SIGNED(zrl_di),RAMDATA_W+1);`
200			`runlength_reg <= zero_cnt(3 downto 0);`
201	40	mikel262	`if signed(zrl_di) = 0 then`
202	39	mikel262	`zero_cnt <= to_unsigned(1,zero_cnt'length);`
203			`else`
204			`zero_cnt <= (others => '0');`
205			`end if;`
206	36	mikel262	`dovalid_reg <= '1';`
207	41	mikel262	`divalid <= divalid_en;`
208	36	mikel262	`-- continue input handling`
209			`zrl_proc <= '0';`
210			`-- zero_cnt > 15`
211			`else`
212			`-- generate ZRL`
213			`acc_reg <= (others => '0');`
214			`runlength_reg <= X"F";`
215			`zero_cnt <= zero_cnt - 16;`
216			`dovalid_reg <= '1';`
217	40	mikel262	`divalid <= '0';`
218			`rd_cnt <= rd_cnt;`
219	36	mikel262	`end if;`
220			`end if;`
221
222			`-- start of 8x8 block processing`
223			`if start_pb = '1' then`
224			`zero_cnt <= (others => '0');`
225			`wr_cnt <= (others => '0');`
226			`end if;`
227
228			`if sof = '1' then`
229			`prev_dc_reg_0 <= (others => '0');`
230			`prev_dc_reg_1 <= (others => '0');`
231			`prev_dc_reg_2 <= (others => '0');`
232			`end if;`
233	25	mikel262
234			`end if;`
235			`end process;`
236
237			`-------------------------------------------------------------------`
238			`-- Entropy Coder`
239			`-------------------------------------------------------------------`
240			`p_entropy_coder : process(CLK, RST)`
241			`begin`
242			`if RST = '1' then`
243			`ampli_vli_reg <= (others => '0');`
244			`size_reg <= (others => '0');`
245			`elsif CLK'event and CLK = '1' then`
246			`-- perform VLI (variable length integer) encoding for Symbol-2 (Amplitude)`
247			`-- positive input`
248			`if acc_reg >= 0 then`
249			`ampli_vli_reg <= acc_reg;`
250			`else`
251			`ampli_vli_reg <= acc_reg - TO_SIGNED(1,RAMDATA_W+1);`
252			`end if;`
253
254			`-- compute Symbol-1 Size`
255			`if acc_reg = TO_SIGNED(-1,RAMDATA_W+1) then`
256			`size_reg <= TO_UNSIGNED(1,SIZE_REG_C);`
257			`elsif (acc_reg < TO_SIGNED(-1,RAMDATA_W+1) and acc_reg > TO_SIGNED(-4,RAMDATA_W+1)) then`
258			`size_reg <= TO_UNSIGNED(2,SIZE_REG_C);`
259			`elsif (acc_reg < TO_SIGNED(-3,RAMDATA_W+1) and acc_reg > TO_SIGNED(-8,RAMDATA_W+1)) then`
260			`size_reg <= TO_UNSIGNED(3,SIZE_REG_C);`
261			`elsif (acc_reg < TO_SIGNED(-7,RAMDATA_W+1) and acc_reg > TO_SIGNED(-16,RAMDATA_W+1)) then`
262			`size_reg <= TO_UNSIGNED(4,SIZE_REG_C);`
263			`elsif (acc_reg < TO_SIGNED(-15,RAMDATA_W+1) and acc_reg > TO_SIGNED(-32,RAMDATA_W+1)) then`
264			`size_reg <= TO_UNSIGNED(5,SIZE_REG_C);`
265			`elsif (acc_reg < TO_SIGNED(-31,RAMDATA_W+1) and acc_reg > TO_SIGNED(-64,RAMDATA_W+1)) then`
266			`size_reg <= TO_UNSIGNED(6,SIZE_REG_C);`
267			`elsif (acc_reg < TO_SIGNED(-63,RAMDATA_W+1) and acc_reg > TO_SIGNED(-128,RAMDATA_W+1)) then`
268			`size_reg <= TO_UNSIGNED(7,SIZE_REG_C);`
269			`elsif (acc_reg < TO_SIGNED(-127,RAMDATA_W+1) and acc_reg > TO_SIGNED(-256,RAMDATA_W+1)) then`
270			`size_reg <= TO_UNSIGNED(8,SIZE_REG_C);`
271			`elsif (acc_reg < TO_SIGNED(-255,RAMDATA_W+1) and acc_reg > TO_SIGNED(-512,RAMDATA_W+1)) then`
272			`size_reg <= TO_UNSIGNED(9,SIZE_REG_C);`
273			`elsif (acc_reg < TO_SIGNED(-511,RAMDATA_W+1) and acc_reg > TO_SIGNED(-1024,RAMDATA_W+1)) then`
274			`size_reg <= TO_UNSIGNED(10,SIZE_REG_C);`
275			`elsif (acc_reg < TO_SIGNED(-1023,RAMDATA_W+1) and acc_reg > TO_SIGNED(-2048,RAMDATA_W+1)) then`
276			`size_reg <= TO_UNSIGNED(11,SIZE_REG_C);`
277			`end if;`
278
279			`-- compute Symbol-1 Size`
280			`-- positive input`
281			`if acc_reg = TO_SIGNED(1,RAMDATA_W+1) then`
282			`size_reg <= TO_UNSIGNED(1,SIZE_REG_C);`
283			`elsif (acc_reg > TO_SIGNED(1,RAMDATA_W+1) and acc_reg < TO_SIGNED(4,RAMDATA_W+1)) then`
284			`size_reg <= TO_UNSIGNED(2,SIZE_REG_C);`
285			`elsif (acc_reg > TO_SIGNED(3,RAMDATA_W+1) and acc_reg < TO_SIGNED(8,RAMDATA_W+1)) then`
286			`size_reg <= TO_UNSIGNED(3,SIZE_REG_C);`
287			`elsif (acc_reg > TO_SIGNED(7,RAMDATA_W+1) and acc_reg < TO_SIGNED(16,RAMDATA_W+1)) then`
288			`size_reg <= TO_UNSIGNED(4,SIZE_REG_C);`
289			`elsif (acc_reg > TO_SIGNED(15,RAMDATA_W+1) and acc_reg < TO_SIGNED(32,RAMDATA_W+1)) then`
290			`size_reg <= TO_UNSIGNED(5,SIZE_REG_C);`
291			`elsif (acc_reg > TO_SIGNED(31,RAMDATA_W+1) and acc_reg < TO_SIGNED(64,RAMDATA_W+1)) then`
292			`size_reg <= TO_UNSIGNED(6,SIZE_REG_C);`
293			`elsif (acc_reg > TO_SIGNED(63,RAMDATA_W+1) and acc_reg < TO_SIGNED(128,RAMDATA_W+1)) then`
294			`size_reg <= TO_UNSIGNED(7,SIZE_REG_C);`
295			`elsif (acc_reg > TO_SIGNED(127,RAMDATA_W+1) and acc_reg < TO_SIGNED(256,RAMDATA_W+1)) then`
296			`size_reg <= TO_UNSIGNED(8,SIZE_REG_C);`
297			`elsif (acc_reg > TO_SIGNED(255,RAMDATA_W+1) and acc_reg < TO_SIGNED(512,RAMDATA_W+1)) then`
298			`size_reg <= TO_UNSIGNED(9,SIZE_REG_C);`
299			`elsif (acc_reg > TO_SIGNED(511,RAMDATA_W+1) and acc_reg < TO_SIGNED(1024,RAMDATA_W+1)) then`
300			`size_reg <= TO_UNSIGNED(10,SIZE_REG_C);`
301			`elsif (acc_reg > TO_SIGNED(1023,RAMDATA_W+1) and acc_reg < TO_SIGNED(2048,RAMDATA_W+1)) then`
302			`size_reg <= TO_UNSIGNED(11,SIZE_REG_C);`
303			`end if;`
304
305			`-- DC coefficient amplitude=0 case OR EOB`
306			`if acc_reg = 0 then`
307			`size_reg <= TO_UNSIGNED(0,SIZE_REG_C);`
308			`end if;`
309			`end if;`
310			`end process;`
311
312			`end rtl;`
313			`--------------------------------------------------------------------------------`
314
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