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[/] [mkjpeg/] [trunk/] [design/] [top/] [JpegEnc.vhd] - Blame information for rev 34

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-------------------------------------------------------------------------------
-- File Name : JpegEnc.vhd
--
-- Project   : JPEG_ENC
--
-- Module    : JpegEnc
--
-- Content   : JPEG Encoder Top Level
--
-- Description : 
--
-- Spec.     : 
--
-- Author    : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
 
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
  use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JpegEnc is
  port
  (
        CLK                : in  std_logic;
        RST                : in  std_logic;
 
        -- OPB
        OPB_ABus           : in  std_logic_vector(31 downto 0);
        OPB_BE             : in  std_logic_vector(3 downto 0);
        OPB_DBus_in        : in  std_logic_vector(31 downto 0);
        OPB_RNW            : in  std_logic;
        OPB_select         : in  std_logic;
        OPB_DBus_out       : out std_logic_vector(31 downto 0);
        OPB_XferAck        : out std_logic;
        OPB_retry          : out std_logic;
        OPB_toutSup        : out std_logic;
        OPB_errAck         : out std_logic;
 
        -- IMAGE RAM
        iram_wdata         : in  std_logic_vector(23 downto 0);
        iram_wren          : in  std_logic;
        iram_fifo_afull    : out std_logic;
 
        -- OUT RAM
        ram_byte           : out std_logic_vector(7 downto 0);
        ram_wren           : out std_logic;
        ram_wraddr         : out std_logic_vector(23 downto 0)
    );
end entity JpegEnc;
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JpegEnc is
 
  signal qdata              : std_logic_vector(7 downto 0);
  signal qaddr              : std_logic_vector(6 downto 0);
  signal qwren              : std_logic;
  signal jpeg_ready         : std_logic;
  signal jpeg_busy          : std_logic;
  signal outram_base_addr   : std_logic_vector(9 downto 0);
  signal num_enc_bytes      : std_logic_vector(23 downto 0);
  signal img_size_x         : std_logic_vector(15 downto 0);
  signal img_size_y         : std_logic_vector(15 downto 0);
  signal sof                : std_logic;
  signal jpg_iram_rden      : std_logic;
  signal jpg_iram_rdaddr    : std_logic_vector(31 downto 0);
  signal jpg_iram_rdata     : std_logic_vector(23 downto 0);
  signal fdct_start         : std_logic;
  signal fdct_ready         : std_logic;
  signal zig_start          : std_logic;
  signal zig_ready          : std_logic;
  signal qua_start          : std_logic;
  signal qua_ready          : std_logic;
  signal rle_start          : std_logic;
  signal rle_ready          : std_logic;
  signal huf_start          : std_logic;
  signal huf_ready          : std_logic;
  signal bs_start           : std_logic;
  signal bs_ready           : std_logic;
  signal zz_buf_sel         : std_logic;
  signal zz_rd_addr         : std_logic_vector(5 downto 0);
  signal zz_data            : std_logic_vector(11 downto 0);
  signal rle_buf_sel        : std_logic;
  signal rle_rdaddr         : std_logic_vector(5 downto 0);
  signal rle_data           : std_logic_vector(11 downto 0);
  signal qua_buf_sel        : std_logic;
  signal qua_rdaddr         : std_logic_vector(5 downto 0);
  signal qua_data           : std_logic_vector(11 downto 0);
  signal huf_buf_sel        : std_logic;
  signal huf_rdaddr         : std_logic_vector(5 downto 0);
  signal huf_rden           : std_logic;
  signal huf_runlength      : std_logic_vector(3 downto 0);
  signal huf_size           : std_logic_vector(3 downto 0);
  signal huf_amplitude      : std_logic_vector(11 downto 0);
  signal huf_dval           : std_logic;
  signal bs_buf_sel         : std_logic;
  signal bs_fifo_empty      : std_logic;
  signal bs_rd_req          : std_logic;
  signal bs_packed_byte     : std_logic_vector(7 downto 0);
  signal huf_fifo_empty     : std_logic;
  signal zz_rden            : std_logic;
  signal fdct_sm_settings   : T_SM_SETTINGS;
  signal zig_sm_settings    : T_SM_SETTINGS;
  signal qua_sm_settings    : T_SM_SETTINGS;
  signal rle_sm_settings    : T_SM_SETTINGS;
  signal huf_sm_settings    : T_SM_SETTINGS;
  signal bs_sm_settings     : T_SM_SETTINGS;
  signal cmp_max            : std_logic_vector(1 downto 0);
  signal image_size_reg     : std_logic_vector(31 downto 0);
  signal jfif_ram_byte      : std_logic_vector(7 downto 0);
  signal jfif_ram_wren      : std_logic;
  signal jfif_ram_wraddr    : std_logic_vector(23 downto 0);
  signal out_mux_ctrl       : std_logic;
  signal img_size_wr        : std_logic;
  signal jfif_start         : std_logic;
  signal jfif_ready         : std_logic;
  signal bs_ram_byte        : std_logic_vector(7 downto 0);
  signal bs_ram_wren        : std_logic;
  signal bs_ram_wraddr      : std_logic_vector(23 downto 0);
  signal jfif_eoi           : std_logic;
  signal fdct_block_cnt     : std_logic_vector(12 downto 0);
  signal fdct_fifo_rd       : std_logic;
  signal fdct_fifo_empty    : std_logic;
  signal fdct_fifo_q        : std_logic_vector(23 downto 0);
  signal fdct_fifo_hf_full  : std_logic;
 
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
 
  -------------------------------------------------------------------
  -- Host Interface
  -------------------------------------------------------------------
  U_HostIF : entity work.HostIF
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- OPB
        OPB_ABus           => OPB_ABus,
        OPB_BE             => OPB_BE,
        OPB_DBus_in        => OPB_DBus_in,
        OPB_RNW            => OPB_RNW,
        OPB_select         => OPB_select,
        OPB_DBus_out       => OPB_DBus_out,
        OPB_XferAck        => OPB_XferAck,
        OPB_retry          => OPB_retry,
        OPB_toutSup        => OPB_toutSup,
        OPB_errAck         => OPB_errAck,
 
        -- Quantizer RAM
        qdata              => qdata,
        qaddr              => qaddr,
        qwren              => qwren,
 
        -- CTRL
        jpeg_ready         => jpeg_ready,
        jpeg_busy          => jpeg_busy,
 
        -- ByteStuffer
        outram_base_addr   => outram_base_addr,
        num_enc_bytes      => num_enc_bytes,
 
        -- global
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        img_size_wr        => img_size_wr,
        sof                => sof,
        cmp_max            => cmp_max
    );
 
  -------------------------------------------------------------------
  -- BUF_FIFO
  -------------------------------------------------------------------
  U_BUF_FIFO : entity work.BUF_FIFO
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- HOST PROG
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        sof                => sof,
 
        -- HOST DATA
        iram_wren          => iram_wren,
        iram_wdata         => iram_wdata,
        fifo_almost_full   => iram_fifo_afull,
 
        -- FDCT
        fdct_block_cnt     => fdct_block_cnt,
        fdct_fifo_rd       => fdct_fifo_rd,
        fdct_fifo_empty    => fdct_fifo_empty,
        fdct_fifo_q        => fdct_fifo_q,
        fdct_fifo_hf_full  => fdct_fifo_hf_full
    );
 
  -------------------------------------------------------------------
  -- Controller
  -------------------------------------------------------------------
  U_CtrlSM : entity work.CtrlSM
  port map
  (
        CLK                => CLK,
        RST                => RST,
 
        -- HOST IF
        sof                => sof,
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        jpeg_ready         => jpeg_ready,
        jpeg_busy          => jpeg_busy,
        cmp_max            => cmp_max,
 
        -- FDCT
        fdct_start         => fdct_start,
        fdct_ready         => fdct_ready,
        fdct_sm_settings   => fdct_sm_settings,
 
        -- ZIGZAG
        zig_start          => zig_start,
        zig_ready          => zig_ready,
        zig_sm_settings    => zig_sm_settings,
 
        -- Quantizer
        qua_start          => qua_start,
        qua_ready          => qua_ready,
        qua_sm_settings    => qua_sm_settings,
 
        -- RLE
        rle_start          => rle_start,
        rle_ready          => rle_ready,
        rle_sm_settings    => rle_sm_settings,
 
        -- Huffman
        huf_start          => huf_start,
        huf_ready          => huf_ready,
        huf_sm_settings    => huf_sm_settings,
 
        -- ByteStuffdr
        bs_start           => bs_start,
        bs_ready           => bs_ready,
        bs_sm_settings     => bs_sm_settings,
 
        -- JFIF GEN
        jfif_start         => jfif_start,
        jfif_ready         => jfif_ready,
        jfif_eoi           => jfif_eoi,
 
        -- OUT MUX         
        out_mux_ctrl       => out_mux_ctrl
    );
 
  -------------------------------------------------------------------
  -- FDCT
  -------------------------------------------------------------------
  U_FDCT : entity work.FDCT
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => fdct_start,
        ready_pb           => fdct_ready,
        fdct_sm_settings   => fdct_sm_settings,
 
        -- BUF_FIFO
        bf_block_cnt       => fdct_block_cnt,
        bf_fifo_rd         => fdct_fifo_rd,
        bf_fifo_empty      => fdct_fifo_empty,
        bf_fifo_q          => fdct_fifo_q,
        bf_fifo_hf_full    => fdct_fifo_hf_full,
 
        -- ZIG ZAG
        zz_buf_sel         => zz_buf_sel,
        zz_rd_addr         => zz_rd_addr,
        zz_data            => zz_data,
        zz_rden            => zz_rden,
 
        -- HOST
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        sof                => sof
    );
 
  -------------------------------------------------------------------
  -- ZigZag top level
  -------------------------------------------------------------------
  U_ZZ_TOP : entity work.ZZ_TOP
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => zig_start,
        ready_pb           => zig_ready,
        zig_sm_settings    => zig_sm_settings,
 
        -- Quantizer
        qua_buf_sel        => qua_buf_sel,
        qua_rdaddr         => qua_rdaddr,
        qua_data           => qua_data,
 
        -- FDCT
        fdct_buf_sel       => zz_buf_sel,
        fdct_rd_addr       => zz_rd_addr,
        fdct_data          => zz_data,
        fdct_rden          => zz_rden
    );
 
  -------------------------------------------------------------------
  -- Quantizer top level
  -------------------------------------------------------------------
  U_QUANT_TOP : entity work.QUANT_TOP
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => qua_start,
        ready_pb           => qua_ready,
        qua_sm_settings    => qua_sm_settings,
 
        -- RLE
        rle_buf_sel        => rle_buf_sel,
        rle_rdaddr         => rle_rdaddr,
        rle_data           => rle_data,
 
        -- ZIGZAG
        zig_buf_sel        => qua_buf_sel,
        zig_rd_addr        => qua_rdaddr,
        zig_data           => qua_data,
 
        -- HOST
        qdata              => qdata,
        qaddr              => qaddr,
        qwren              => qwren
    );
 
  -------------------------------------------------------------------
  -- RLE TOP
  -------------------------------------------------------------------
  U_RLE_TOP : entity work.RLE_TOP
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => rle_start,
        ready_pb           => rle_ready,
        rle_sm_settings    => rle_sm_settings,
 
        -- HUFFMAN
        huf_buf_sel        => huf_buf_sel,
        huf_rden           => huf_rden,
        huf_runlength      => huf_runlength,
        huf_size           => huf_size,
        huf_amplitude      => huf_amplitude,
        huf_dval           => huf_dval,
        huf_fifo_empty     => huf_fifo_empty,
 
        -- Quantizer
        qua_buf_sel        => rle_buf_sel,
        qua_rd_addr        => rle_rdaddr,
        qua_data           => rle_data,
 
        -- HostIF
        sof                => sof
    );
 
  -------------------------------------------------------------------
  -- Huffman Encoder
  -------------------------------------------------------------------
  U_Huffman : entity work.Huffman
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => huf_start,
        ready_pb           => huf_ready,
 
        -- HOST IF
        sof                => sof,
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        cmp_max            => cmp_max,
 
        -- RLE
        rle_buf_sel        => huf_buf_sel,
        rd_en              => huf_rden,
        runlength          => huf_runlength,
        VLI_size           => huf_size,
        VLI                => huf_amplitude,
        d_val              => huf_dval,
        rle_fifo_empty     => huf_fifo_empty,
 
 
        -- Byte Stuffer
        bs_buf_sel         => bs_buf_sel,
        bs_fifo_empty      => bs_fifo_empty,
        bs_rd_req          => bs_rd_req,
        bs_packed_byte     => bs_packed_byte
    );
 
 
  -------------------------------------------------------------------
  -- Byte Stuffer
  -------------------------------------------------------------------
  U_ByteStuffer : entity work.ByteStuffer
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => bs_start,
        ready_pb           => bs_ready,
 
        -- HOST IF
        sof                => sof,
        num_enc_bytes      => num_enc_bytes,
        outram_base_addr   => outram_base_addr,
 
        -- Huffman
        huf_buf_sel        => bs_buf_sel,
        huf_fifo_empty     => bs_fifo_empty,
        huf_rd_req         => bs_rd_req,
        huf_packed_byte    => bs_packed_byte,
 
        -- OUT RAM
        ram_byte           => bs_ram_byte,
        ram_wren           => bs_ram_wren,
        ram_wraddr         => bs_ram_wraddr
    );
 
  -------------------------------------------------------------------
  -- JFIF Generator
  -------------------------------------------------------------------
  U_JFIFGen : entity work.JFIFGen
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start              => jfif_start,
        ready              => jfif_ready,
        eoi                => jfif_eoi,
 
        -- ByteStuffer
        num_enc_bytes         => num_enc_bytes,
 
        -- HOST IF
        qwren              => qwren,
        qwaddr             => qaddr,
        qwdata             => qdata,
        image_size_reg     => image_size_reg,
        image_size_reg_wr  => img_size_wr,
 
        -- OUT RAM
        ram_byte           => jfif_ram_byte,
        ram_wren           => jfif_ram_wren,
        ram_wraddr         => jfif_ram_wraddr
    );
 
  image_size_reg <= img_size_x & img_size_y;
 
  -------------------------------------------------------------------
  -- OutMux
  -------------------------------------------------------------------
  U_OutMux : entity work.OutMux
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        out_mux_ctrl       => out_mux_ctrl,
 
        -- ByteStuffer
        bs_ram_byte        => bs_ram_byte,
        bs_ram_wren        => bs_ram_wren,
        bs_ram_wraddr      => bs_ram_wraddr,
        -- ByteStuffer
        jfif_ram_byte      => jfif_ram_byte,
        jfif_ram_wren      => jfif_ram_wren,
        jfif_ram_wraddr    => jfif_ram_wraddr,
 
        -- OUT RAM
        ram_byte           => ram_byte,
        ram_wren           => ram_wren,
        ram_wraddr         => ram_wraddr
    );
 
 
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------

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Subversion Repositories mkjpeg

[/] [mkjpeg/] [trunk/] [design/] [top/] [JpegEnc.vhd] - Blame information for rev 34

Line No.	Rev	Author	Line
1	25	mikel262	`-------------------------------------------------------------------------------`
2			`-- File Name : JpegEnc.vhd`
3			`--`
4			`-- Project : JPEG_ENC`
5			`--`
6			`-- Module : JpegEnc`
7			`--`
8			`-- Content : JPEG Encoder Top Level`
9			`--`
10			`-- Description :`
11			`--`
12			`-- Spec. :`
13			`--`
14			`-- Author : Michal Krepa`
15			`--`
16			`-------------------------------------------------------------------------------`
17			`-- History :`
18			`-- 20090301: (MK): Initial Creation.`
19			`-------------------------------------------------------------------------------`
20
21			`-------------------------------------------------------------------------------`
22			`-------------------------------------------------------------------------------`
23			`----------------------------------- LIBRARY/PACKAGE ---------------------------`
24			`-------------------------------------------------------------------------------`
25			`-------------------------------------------------------------------------------`
26
27			`-------------------------------------------------------------------------------`
28			`-- generic packages/libraries:`
29			`-------------------------------------------------------------------------------`
30			`library ieee;`
31			`use ieee.std_logic_1164.all;`
32			`use ieee.numeric_std.all;`
33
34			`-------------------------------------------------------------------------------`
35			`-- user packages/libraries:`
36			`-------------------------------------------------------------------------------`
37			`library work;`
38			`use work.JPEG_PKG.all;`
39			`-------------------------------------------------------------------------------`
40			`-------------------------------------------------------------------------------`
41			`----------------------------------- ENTITY ------------------------------------`
42			`-------------------------------------------------------------------------------`
43			`-------------------------------------------------------------------------------`
44			`entity JpegEnc is`
45			`port`
46			`(`
47			`CLK : in std_logic;`
48			`RST : in std_logic;`
49
50			`-- OPB`
51			`OPB_ABus : in std_logic_vector(31 downto 0);`
52			`OPB_BE : in std_logic_vector(3 downto 0);`
53			`OPB_DBus_in : in std_logic_vector(31 downto 0);`
54			`OPB_RNW : in std_logic;`
55			`OPB_select : in std_logic;`
56			`OPB_DBus_out : out std_logic_vector(31 downto 0);`
57			`OPB_XferAck : out std_logic;`
58			`OPB_retry : out std_logic;`
59			`OPB_toutSup : out std_logic;`
60			`OPB_errAck : out std_logic;`
61
62			`-- IMAGE RAM`
63			`iram_wdata : in std_logic_vector(23 downto 0);`
64			`iram_wren : in std_logic;`
65			`iram_fifo_afull : out std_logic;`
66
67			`-- OUT RAM`
68			`ram_byte : out std_logic_vector(7 downto 0);`
69			`ram_wren : out std_logic;`
70			`ram_wraddr : out std_logic_vector(23 downto 0)`
71			`);`
72			`end entity JpegEnc;`
73
74			`-------------------------------------------------------------------------------`
75			`-------------------------------------------------------------------------------`
76			`----------------------------------- ARCHITECTURE ------------------------------`
77			`-------------------------------------------------------------------------------`
78			`-------------------------------------------------------------------------------`
79			`architecture RTL of JpegEnc is`
80
81			`signal qdata : std_logic_vector(7 downto 0);`
82	32	mikel262	`signal qaddr : std_logic_vector(6 downto 0);`
83	25	mikel262	`signal qwren : std_logic;`
84			`signal jpeg_ready : std_logic;`
85			`signal jpeg_busy : std_logic;`
86			`signal outram_base_addr : std_logic_vector(9 downto 0);`
87			`signal num_enc_bytes : std_logic_vector(23 downto 0);`
88			`signal img_size_x : std_logic_vector(15 downto 0);`
89			`signal img_size_y : std_logic_vector(15 downto 0);`
90			`signal sof : std_logic;`
91			`signal jpg_iram_rden : std_logic;`
92			`signal jpg_iram_rdaddr : std_logic_vector(31 downto 0);`
93			`signal jpg_iram_rdata : std_logic_vector(23 downto 0);`
94			`signal fdct_start : std_logic;`
95			`signal fdct_ready : std_logic;`
96			`signal zig_start : std_logic;`
97			`signal zig_ready : std_logic;`
98	34	mikel262	`signal qua_start : std_logic;`
99			`signal qua_ready : std_logic;`
100	25	mikel262	`signal rle_start : std_logic;`
101			`signal rle_ready : std_logic;`
102			`signal huf_start : std_logic;`
103			`signal huf_ready : std_logic;`
104			`signal bs_start : std_logic;`
105			`signal bs_ready : std_logic;`
106			`signal zz_buf_sel : std_logic;`
107			`signal zz_rd_addr : std_logic_vector(5 downto 0);`
108			`signal zz_data : std_logic_vector(11 downto 0);`
109			`signal rle_buf_sel : std_logic;`
110			`signal rle_rdaddr : std_logic_vector(5 downto 0);`
111			`signal rle_data : std_logic_vector(11 downto 0);`
112	34	mikel262	`signal qua_buf_sel : std_logic;`
113			`signal qua_rdaddr : std_logic_vector(5 downto 0);`
114			`signal qua_data : std_logic_vector(11 downto 0);`
115	25	mikel262	`signal huf_buf_sel : std_logic;`
116			`signal huf_rdaddr : std_logic_vector(5 downto 0);`
117			`signal huf_rden : std_logic;`
118			`signal huf_runlength : std_logic_vector(3 downto 0);`
119			`signal huf_size : std_logic_vector(3 downto 0);`
120			`signal huf_amplitude : std_logic_vector(11 downto 0);`
121			`signal huf_dval : std_logic;`
122			`signal bs_buf_sel : std_logic;`
123			`signal bs_fifo_empty : std_logic;`
124			`signal bs_rd_req : std_logic;`
125			`signal bs_packed_byte : std_logic_vector(7 downto 0);`
126			`signal huf_fifo_empty : std_logic;`
127			`signal zz_rden : std_logic;`
128			`signal fdct_sm_settings : T_SM_SETTINGS;`
129			`signal zig_sm_settings : T_SM_SETTINGS;`
130	34	mikel262	`signal qua_sm_settings : T_SM_SETTINGS;`
131	25	mikel262	`signal rle_sm_settings : T_SM_SETTINGS;`
132			`signal huf_sm_settings : T_SM_SETTINGS;`
133			`signal bs_sm_settings : T_SM_SETTINGS;`
134			`signal cmp_max : std_logic_vector(1 downto 0);`
135			`signal image_size_reg : std_logic_vector(31 downto 0);`
136			`signal jfif_ram_byte : std_logic_vector(7 downto 0);`
137			`signal jfif_ram_wren : std_logic;`
138			`signal jfif_ram_wraddr : std_logic_vector(23 downto 0);`
139			`signal out_mux_ctrl : std_logic;`
140			`signal img_size_wr : std_logic;`
141			`signal jfif_start : std_logic;`
142			`signal jfif_ready : std_logic;`
143			`signal bs_ram_byte : std_logic_vector(7 downto 0);`
144			`signal bs_ram_wren : std_logic;`
145			`signal bs_ram_wraddr : std_logic_vector(23 downto 0);`
146			`signal jfif_eoi : std_logic;`
147			`signal fdct_block_cnt : std_logic_vector(12 downto 0);`
148			`signal fdct_fifo_rd : std_logic;`
149			`signal fdct_fifo_empty : std_logic;`
150			`signal fdct_fifo_q : std_logic_vector(23 downto 0);`
151			`signal fdct_fifo_hf_full : std_logic;`
152
153			`-------------------------------------------------------------------------------`
154			`-- Architecture: begin`
155			`-------------------------------------------------------------------------------`
156			`begin`
157
158			`-------------------------------------------------------------------`
159			`-- Host Interface`
160			`-------------------------------------------------------------------`
161			`U_HostIF : entity work.HostIF`
162			`port map`
163			`(`
164			`CLK => CLK,`
165			`RST => RST,`
166			`-- OPB`
167			`OPB_ABus => OPB_ABus,`
168			`OPB_BE => OPB_BE,`
169			`OPB_DBus_in => OPB_DBus_in,`
170			`OPB_RNW => OPB_RNW,`
171			`OPB_select => OPB_select,`
172			`OPB_DBus_out => OPB_DBus_out,`
173			`OPB_XferAck => OPB_XferAck,`
174			`OPB_retry => OPB_retry,`
175			`OPB_toutSup => OPB_toutSup,`
176			`OPB_errAck => OPB_errAck,`
177
178			`-- Quantizer RAM`
179			`qdata => qdata,`
180			`qaddr => qaddr,`
181			`qwren => qwren,`
182
183			`-- CTRL`
184			`jpeg_ready => jpeg_ready,`
185			`jpeg_busy => jpeg_busy,`
186
187			`-- ByteStuffer`
188			`outram_base_addr => outram_base_addr,`
189			`num_enc_bytes => num_enc_bytes,`
190
191			`-- global`
192			`img_size_x => img_size_x,`
193			`img_size_y => img_size_y,`
194			`img_size_wr => img_size_wr,`
195			`sof => sof,`
196			`cmp_max => cmp_max`
197			`);`
198
199			`-------------------------------------------------------------------`
200			`-- BUF_FIFO`
201			`-------------------------------------------------------------------`
202			`U_BUF_FIFO : entity work.BUF_FIFO`
203			`port map`
204			`(`
205			`CLK => CLK,`
206			`RST => RST,`
207			`-- HOST PROG`
208			`img_size_x => img_size_x,`
209			`img_size_y => img_size_y,`
210			`sof => sof,`
211
212			`-- HOST DATA`
213			`iram_wren => iram_wren,`
214			`iram_wdata => iram_wdata,`
215			`fifo_almost_full => iram_fifo_afull,`
216
217			`-- FDCT`
218			`fdct_block_cnt => fdct_block_cnt,`
219			`fdct_fifo_rd => fdct_fifo_rd,`
220			`fdct_fifo_empty => fdct_fifo_empty,`
221			`fdct_fifo_q => fdct_fifo_q,`
222			`fdct_fifo_hf_full => fdct_fifo_hf_full`
223			`);`
224
225			`-------------------------------------------------------------------`
226			`-- Controller`
227			`-------------------------------------------------------------------`
228			`U_CtrlSM : entity work.CtrlSM`
229			`port map`
230			`(`
231			`CLK => CLK,`
232			`RST => RST,`
233
234			`-- HOST IF`
235			`sof => sof,`
236			`img_size_x => img_size_x,`
237			`img_size_y => img_size_y,`
238			`jpeg_ready => jpeg_ready,`
239			`jpeg_busy => jpeg_busy,`
240			`cmp_max => cmp_max,`
241
242			`-- FDCT`
243			`fdct_start => fdct_start,`
244			`fdct_ready => fdct_ready,`
245			`fdct_sm_settings => fdct_sm_settings,`
246
247			`-- ZIGZAG`
248			`zig_start => zig_start,`
249			`zig_ready => zig_ready,`
250			`zig_sm_settings => zig_sm_settings,`
251	34	mikel262
252			`-- Quantizer`
253			`qua_start => qua_start,`
254			`qua_ready => qua_ready,`
255			`qua_sm_settings => qua_sm_settings,`
256	25	mikel262
257			`-- RLE`
258			`rle_start => rle_start,`
259			`rle_ready => rle_ready,`
260			`rle_sm_settings => rle_sm_settings,`
261
262			`-- Huffman`
263			`huf_start => huf_start,`
264			`huf_ready => huf_ready,`
265			`huf_sm_settings => huf_sm_settings,`
266
267			`-- ByteStuffdr`
268			`bs_start => bs_start,`
269			`bs_ready => bs_ready,`
270			`bs_sm_settings => bs_sm_settings,`
271
272			`-- JFIF GEN`
273			`jfif_start => jfif_start,`
274			`jfif_ready => jfif_ready,`
275			`jfif_eoi => jfif_eoi,`
276
277			`-- OUT MUX`
278			`out_mux_ctrl => out_mux_ctrl`
279			`);`
280
281			`-------------------------------------------------------------------`
282			`-- FDCT`
283			`-------------------------------------------------------------------`
284			`U_FDCT : entity work.FDCT`
285			`port map`
286			`(`
287			`CLK => CLK,`
288			`RST => RST,`
289			`-- CTRL`
290			`start_pb => fdct_start,`
291			`ready_pb => fdct_ready,`
292			`fdct_sm_settings => fdct_sm_settings,`
293
294			`-- BUF_FIFO`
295			`bf_block_cnt => fdct_block_cnt,`
296			`bf_fifo_rd => fdct_fifo_rd,`
297			`bf_fifo_empty => fdct_fifo_empty,`
298			`bf_fifo_q => fdct_fifo_q,`
299			`bf_fifo_hf_full => fdct_fifo_hf_full,`
300
301			`-- ZIG ZAG`
302			`zz_buf_sel => zz_buf_sel,`
303			`zz_rd_addr => zz_rd_addr,`
304			`zz_data => zz_data,`
305			`zz_rden => zz_rden,`
306
307			`-- HOST`
308			`img_size_x => img_size_x,`
309			`img_size_y => img_size_y,`
310			`sof => sof`
311			`);`
312
313			`-------------------------------------------------------------------`
314			`-- ZigZag top level`
315			`-------------------------------------------------------------------`
316			`U_ZZ_TOP : entity work.ZZ_TOP`
317			`port map`
318			`(`
319			`CLK => CLK,`
320			`RST => RST,`
321			`-- CTRL`
322			`start_pb => zig_start,`
323			`ready_pb => zig_ready,`
324	32	mikel262	`zig_sm_settings => zig_sm_settings,`
325	25	mikel262
326	34	mikel262	`-- Quantizer`
327			`qua_buf_sel => qua_buf_sel,`
328			`qua_rdaddr => qua_rdaddr,`
329			`qua_data => qua_data,`
330	25	mikel262
331			`-- FDCT`
332			`fdct_buf_sel => zz_buf_sel,`
333			`fdct_rd_addr => zz_rd_addr,`
334			`fdct_data => zz_data,`
335	34	mikel262	`fdct_rden => zz_rden`
336			`);`
337
338			`-------------------------------------------------------------------`
339			`-- Quantizer top level`
340			`-------------------------------------------------------------------`
341			`U_QUANT_TOP : entity work.QUANT_TOP`
342			`port map`
343			`(`
344			`CLK => CLK,`
345			`RST => RST,`
346			`-- CTRL`
347			`start_pb => qua_start,`
348			`ready_pb => qua_ready,`
349			`qua_sm_settings => qua_sm_settings,`
350	25	mikel262
351	34	mikel262	`-- RLE`
352			`rle_buf_sel => rle_buf_sel,`
353			`rle_rdaddr => rle_rdaddr,`
354			`rle_data => rle_data,`
355
356			`-- ZIGZAG`
357			`zig_buf_sel => qua_buf_sel,`
358			`zig_rd_addr => qua_rdaddr,`
359			`zig_data => qua_data,`
360
361	25	mikel262	`-- HOST`
362			`qdata => qdata,`
363			`qaddr => qaddr,`
364			`qwren => qwren`
365	34	mikel262	`);`
366
367	25	mikel262	`-------------------------------------------------------------------`
368			`-- RLE TOP`
369			`-------------------------------------------------------------------`
370			`U_RLE_TOP : entity work.RLE_TOP`
371			`port map`
372			`(`
373			`CLK => CLK,`
374			`RST => RST,`
375			`-- CTRL`
376			`start_pb => rle_start,`
377			`ready_pb => rle_ready,`
378			`rle_sm_settings => rle_sm_settings,`
379
380			`-- HUFFMAN`
381			`huf_buf_sel => huf_buf_sel,`
382			`huf_rden => huf_rden,`
383			`huf_runlength => huf_runlength,`
384			`huf_size => huf_size,`
385			`huf_amplitude => huf_amplitude,`
386			`huf_dval => huf_dval,`
387			`huf_fifo_empty => huf_fifo_empty,`
388
389	34	mikel262	`-- Quantizer`
390			`qua_buf_sel => rle_buf_sel,`
391			`qua_rd_addr => rle_rdaddr,`
392			`qua_data => rle_data,`
393	25	mikel262
394			`-- HostIF`
395			`sof => sof`
396			`);`
397
398			`-------------------------------------------------------------------`
399			`-- Huffman Encoder`
400			`-------------------------------------------------------------------`
401			`U_Huffman : entity work.Huffman`
402			`port map`
403			`(`
404			`CLK => CLK,`
405			`RST => RST,`
406			`-- CTRL`
407			`start_pb => huf_start,`
408			`ready_pb => huf_ready,`
409
410			`-- HOST IF`
411			`sof => sof,`
412			`img_size_x => img_size_x,`
413			`img_size_y => img_size_y,`
414			`cmp_max => cmp_max,`
415
416			`-- RLE`
417			`rle_buf_sel => huf_buf_sel,`
418			`rd_en => huf_rden,`
419			`runlength => huf_runlength,`
420			`VLI_size => huf_size,`
421			`VLI => huf_amplitude,`
422			`d_val => huf_dval,`
423			`rle_fifo_empty => huf_fifo_empty,`
424
425
426			`-- Byte Stuffer`
427			`bs_buf_sel => bs_buf_sel,`
428			`bs_fifo_empty => bs_fifo_empty,`
429			`bs_rd_req => bs_rd_req,`
430			`bs_packed_byte => bs_packed_byte`
431			`);`
432
433
434			`-------------------------------------------------------------------`
435			`-- Byte Stuffer`
436			`-------------------------------------------------------------------`
437			`U_ByteStuffer : entity work.ByteStuffer`
438			`port map`
439			`(`
440			`CLK => CLK,`
441			`RST => RST,`
442			`-- CTRL`
443			`start_pb => bs_start,`
444			`ready_pb => bs_ready,`
445
446			`-- HOST IF`
447			`sof => sof,`
448			`num_enc_bytes => num_enc_bytes,`
449			`outram_base_addr => outram_base_addr,`
450
451			`-- Huffman`
452			`huf_buf_sel => bs_buf_sel,`
453			`huf_fifo_empty => bs_fifo_empty,`
454			`huf_rd_req => bs_rd_req,`
455			`huf_packed_byte => bs_packed_byte,`
456
457			`-- OUT RAM`
458			`ram_byte => bs_ram_byte,`
459			`ram_wren => bs_ram_wren,`
460			`ram_wraddr => bs_ram_wraddr`
461			`);`
462
463			`-------------------------------------------------------------------`
464			`-- JFIF Generator`
465			`-------------------------------------------------------------------`
466			`U_JFIFGen : entity work.JFIFGen`
467			`port map`
468			`(`
469			`CLK => CLK,`
470			`RST => RST,`
471			`-- CTRL`
472			`start => jfif_start,`
473			`ready => jfif_ready,`
474			`eoi => jfif_eoi,`
475
476			`-- ByteStuffer`
477			`num_enc_bytes => num_enc_bytes,`
478
479			`-- HOST IF`
480			`qwren => qwren,`
481			`qwaddr => qaddr,`
482			`qwdata => qdata,`
483			`image_size_reg => image_size_reg,`
484			`image_size_reg_wr => img_size_wr,`
485
486			`-- OUT RAM`
487			`ram_byte => jfif_ram_byte,`
488			`ram_wren => jfif_ram_wren,`
489			`ram_wraddr => jfif_ram_wraddr`
490			`);`
491
492			`image_size_reg <= img_size_x & img_size_y;`
493
494			`-------------------------------------------------------------------`
495			`-- OutMux`
496			`-------------------------------------------------------------------`
497			`U_OutMux : entity work.OutMux`
498			`port map`
499			`(`
500			`CLK => CLK,`
501			`RST => RST,`
502			`-- CTRL`
503			`out_mux_ctrl => out_mux_ctrl,`
504
505			`-- ByteStuffer`
506			`bs_ram_byte => bs_ram_byte,`
507			`bs_ram_wren => bs_ram_wren,`
508			`bs_ram_wraddr => bs_ram_wraddr,`
509			`-- ByteStuffer`
510			`jfif_ram_byte => jfif_ram_byte,`
511			`jfif_ram_wren => jfif_ram_wren,`
512			`jfif_ram_wraddr => jfif_ram_wraddr,`
513
514			`-- OUT RAM`
515			`ram_byte => ram_byte,`
516			`ram_wren => ram_wren,`
517			`ram_wraddr => ram_wraddr`
518			`);`
519
520
521			`end architecture RTL;`
522			`-------------------------------------------------------------------------------`
523			`-- Architecture: end`
524			`-------------------------------------------------------------------------------`