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-------------------------------------------------------------------------------
-- File Name : JpegEnc.vhd
--
-- Project   : JPEG_ENC
--
-- Module    : JpegEnc
--
-- Content   : JPEG Encoder Top Level
--
-- Description : 
--
-- Spec.     : 
--
-- Author    : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
 
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
  use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JpegEnc is
  port
  (
        CLK                : in  std_logic;
        RST                : in  std_logic;
 
        -- OPB
        OPB_ABus           : in  std_logic_vector(31 downto 0);
        OPB_BE             : in  std_logic_vector(3 downto 0);
        OPB_DBus_in        : in  std_logic_vector(31 downto 0);
        OPB_RNW            : in  std_logic;
        OPB_select         : in  std_logic;
        OPB_DBus_out       : out std_logic_vector(31 downto 0);
        OPB_XferAck        : out std_logic;
        OPB_retry          : out std_logic;
        OPB_toutSup        : out std_logic;
        OPB_errAck         : out std_logic;
 
        -- IMAGE RAM
        iram_wdata         : in  std_logic_vector(23 downto 0);
        iram_wren          : in  std_logic;
        iram_fifo_afull    : out std_logic;
 
        -- OUT RAM
        ram_byte           : out std_logic_vector(7 downto 0);
        ram_wren           : out std_logic;
        ram_wraddr         : out std_logic_vector(23 downto 0);
        outif_almost_full  : in  std_logic
    );
end entity JpegEnc;
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JpegEnc is
 
  signal qdata              : std_logic_vector(7 downto 0);
  signal qaddr              : std_logic_vector(6 downto 0);
  signal qwren              : std_logic;
  signal jpeg_ready         : std_logic;
  signal jpeg_busy          : std_logic;
  signal outram_base_addr   : std_logic_vector(9 downto 0);
  signal num_enc_bytes      : std_logic_vector(23 downto 0);
  signal img_size_x         : std_logic_vector(15 downto 0);
  signal img_size_y         : std_logic_vector(15 downto 0);
  signal sof                : std_logic;
  signal jpg_iram_rden      : std_logic;
  signal jpg_iram_rdaddr    : std_logic_vector(31 downto 0);
  signal jpg_iram_rdata     : std_logic_vector(23 downto 0);
  signal fdct_start         : std_logic;
  signal fdct_ready         : std_logic;
  signal zig_start          : std_logic;
  signal zig_ready          : std_logic;
  signal qua_start          : std_logic;
  signal qua_ready          : std_logic;
  signal rle_start          : std_logic;
  signal rle_ready          : std_logic;
  signal huf_start          : std_logic;
  signal huf_ready          : std_logic;
  signal bs_start           : std_logic;
  signal bs_ready           : std_logic;
  signal zz_buf_sel         : std_logic;
  signal zz_rd_addr         : std_logic_vector(5 downto 0);
  signal zz_data            : std_logic_vector(11 downto 0);
  signal rle_buf_sel        : std_logic;
  signal rle_rdaddr         : std_logic_vector(5 downto 0);
  signal rle_data           : std_logic_vector(11 downto 0);
  signal qua_buf_sel        : std_logic;
  signal qua_rdaddr         : std_logic_vector(5 downto 0);
  signal qua_data           : std_logic_vector(11 downto 0);
  signal huf_buf_sel        : std_logic;
  signal huf_rdaddr         : std_logic_vector(5 downto 0);
  signal huf_rden           : std_logic;
  signal huf_runlength      : std_logic_vector(3 downto 0);
  signal huf_size           : std_logic_vector(3 downto 0);
  signal huf_amplitude      : std_logic_vector(11 downto 0);
  signal huf_dval           : std_logic;
  signal bs_buf_sel         : std_logic;
  signal bs_fifo_empty      : std_logic;
  signal bs_rd_req          : std_logic;
  signal bs_packed_byte     : std_logic_vector(7 downto 0);
  signal huf_fifo_empty     : std_logic;
  signal zz_rden            : std_logic;
  signal fdct_sm_settings   : T_SM_SETTINGS;
  signal zig_sm_settings    : T_SM_SETTINGS;
  signal qua_sm_settings    : T_SM_SETTINGS;
  signal rle_sm_settings    : T_SM_SETTINGS;
  signal huf_sm_settings    : T_SM_SETTINGS;
  signal bs_sm_settings     : T_SM_SETTINGS;
  signal cmp_max            : std_logic_vector(1 downto 0);
  signal image_size_reg     : std_logic_vector(31 downto 0);
  signal jfif_ram_byte      : std_logic_vector(7 downto 0);
  signal jfif_ram_wren      : std_logic;
  signal jfif_ram_wraddr    : std_logic_vector(23 downto 0);
  signal out_mux_ctrl       : std_logic;
  signal img_size_wr        : std_logic;
  signal jfif_start         : std_logic;
  signal jfif_ready         : std_logic;
  signal bs_ram_byte        : std_logic_vector(7 downto 0);
  signal bs_ram_wren        : std_logic;
  signal bs_ram_wraddr      : std_logic_vector(23 downto 0);
  signal jfif_eoi           : std_logic;
  signal fdct_block_cnt     : std_logic_vector(12 downto 0);
  signal fdct_fifo_rd       : std_logic;
  signal fdct_fifo_empty    : std_logic;
  signal fdct_fifo_q        : std_logic_vector(23 downto 0);
  signal fdct_fifo_hf_full  : std_logic;
 
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
 
  -------------------------------------------------------------------
  -- Host Interface
  -------------------------------------------------------------------
  U_HostIF : entity work.HostIF
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- OPB
        OPB_ABus           => OPB_ABus,
        OPB_BE             => OPB_BE,
        OPB_DBus_in        => OPB_DBus_in,
        OPB_RNW            => OPB_RNW,
        OPB_select         => OPB_select,
        OPB_DBus_out       => OPB_DBus_out,
        OPB_XferAck        => OPB_XferAck,
        OPB_retry          => OPB_retry,
        OPB_toutSup        => OPB_toutSup,
        OPB_errAck         => OPB_errAck,
 
        -- Quantizer RAM
        qdata              => qdata,
        qaddr              => qaddr,
        qwren              => qwren,
 
        -- CTRL
        jpeg_ready         => jpeg_ready,
        jpeg_busy          => jpeg_busy,
 
        -- ByteStuffer
        outram_base_addr   => outram_base_addr,
        num_enc_bytes      => num_enc_bytes,
 
        -- global
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        img_size_wr        => img_size_wr,
        sof                => sof,
        cmp_max            => cmp_max
    );
 
  -------------------------------------------------------------------
  -- BUF_FIFO
  -------------------------------------------------------------------
  U_BUF_FIFO : entity work.BUF_FIFO
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- HOST PROG
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        sof                => sof,
 
        -- HOST DATA
        iram_wren          => iram_wren,
        iram_wdata         => iram_wdata,
        fifo_almost_full   => iram_fifo_afull,
 
        -- FDCT
        fdct_block_cnt     => fdct_block_cnt,
        fdct_fifo_rd       => fdct_fifo_rd,
        fdct_fifo_empty    => fdct_fifo_empty,
        fdct_fifo_q        => fdct_fifo_q,
        fdct_fifo_hf_full  => fdct_fifo_hf_full
    );
 
  -------------------------------------------------------------------
  -- Controller
  -------------------------------------------------------------------
  U_CtrlSM : entity work.CtrlSM
  port map
  (
        CLK                => CLK,
        RST                => RST,
 
        -- output IF
        outif_almost_full  => outif_almost_full,
 
        -- HOST IF
        sof                => sof,
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        jpeg_ready         => jpeg_ready,
        jpeg_busy          => jpeg_busy,
        cmp_max            => cmp_max,
 
        -- FDCT
        fdct_start         => fdct_start,
        fdct_ready         => fdct_ready,
        fdct_sm_settings   => fdct_sm_settings,
 
        -- ZIGZAG
        zig_start          => zig_start,
        zig_ready          => zig_ready,
        zig_sm_settings    => zig_sm_settings,
 
        -- Quantizer
        qua_start          => qua_start,
        qua_ready          => qua_ready,
        qua_sm_settings    => qua_sm_settings,
 
        -- RLE
        rle_start          => rle_start,
        rle_ready          => rle_ready,
        rle_sm_settings    => rle_sm_settings,
 
        -- Huffman
        huf_start          => huf_start,
        huf_ready          => huf_ready,
        huf_sm_settings    => huf_sm_settings,
 
        -- ByteStuffdr
        bs_start           => bs_start,
        bs_ready           => bs_ready,
        bs_sm_settings     => bs_sm_settings,
 
        -- JFIF GEN
        jfif_start         => jfif_start,
        jfif_ready         => jfif_ready,
        jfif_eoi           => jfif_eoi,
 
        -- OUT MUX         
        out_mux_ctrl       => out_mux_ctrl
    );
 
  -------------------------------------------------------------------
  -- FDCT
  -------------------------------------------------------------------
  U_FDCT : entity work.FDCT
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => fdct_start,
        ready_pb           => fdct_ready,
        fdct_sm_settings   => fdct_sm_settings,
 
        -- BUF_FIFO
        bf_block_cnt       => fdct_block_cnt,
        bf_fifo_rd         => fdct_fifo_rd,
        bf_fifo_empty      => fdct_fifo_empty,
        bf_fifo_q          => fdct_fifo_q,
        bf_fifo_hf_full    => fdct_fifo_hf_full,
 
        -- ZIG ZAG
        zz_buf_sel         => zz_buf_sel,
        zz_rd_addr         => zz_rd_addr,
        zz_data            => zz_data,
        zz_rden            => zz_rden,
 
        -- HOST
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        sof                => sof
    );
 
  -------------------------------------------------------------------
  -- ZigZag top level
  -------------------------------------------------------------------
  U_ZZ_TOP : entity work.ZZ_TOP
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => zig_start,
        ready_pb           => zig_ready,
        zig_sm_settings    => zig_sm_settings,
 
        -- Quantizer
        qua_buf_sel        => qua_buf_sel,
        qua_rdaddr         => qua_rdaddr,
        qua_data           => qua_data,
 
        -- FDCT
        fdct_buf_sel       => zz_buf_sel,
        fdct_rd_addr       => zz_rd_addr,
        fdct_data          => zz_data,
        fdct_rden          => zz_rden
    );
 
  -------------------------------------------------------------------
  -- Quantizer top level
  -------------------------------------------------------------------
  U_QUANT_TOP : entity work.QUANT_TOP
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => qua_start,
        ready_pb           => qua_ready,
        qua_sm_settings    => qua_sm_settings,
 
        -- RLE
        rle_buf_sel        => rle_buf_sel,
        rle_rdaddr         => rle_rdaddr,
        rle_data           => rle_data,
 
        -- ZIGZAG
        zig_buf_sel        => qua_buf_sel,
        zig_rd_addr        => qua_rdaddr,
        zig_data           => qua_data,
 
        -- HOST
        qdata              => qdata,
        qaddr              => qaddr,
        qwren              => qwren
    );
 
  -------------------------------------------------------------------
  -- RLE TOP
  -------------------------------------------------------------------
  U_RLE_TOP : entity work.RLE_TOP
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => rle_start,
        ready_pb           => rle_ready,
        rle_sm_settings    => rle_sm_settings,
 
        -- HUFFMAN
        huf_buf_sel        => huf_buf_sel,
        huf_rden           => huf_rden,
        huf_runlength      => huf_runlength,
        huf_size           => huf_size,
        huf_amplitude      => huf_amplitude,
        huf_dval           => huf_dval,
        huf_fifo_empty     => huf_fifo_empty,
 
        -- Quantizer
        qua_buf_sel        => rle_buf_sel,
        qua_rd_addr        => rle_rdaddr,
        qua_data           => rle_data,
 
        -- HostIF
        sof                => sof
    );
 
  -------------------------------------------------------------------
  -- Huffman Encoder
  -------------------------------------------------------------------
  U_Huffman : entity work.Huffman
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => huf_start,
        ready_pb           => huf_ready,
        huf_sm_settings    => huf_sm_settings,
 
        -- HOST IF
        sof                => sof,
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        cmp_max            => cmp_max,
 
        -- RLE
        rle_buf_sel        => huf_buf_sel,
        rd_en              => huf_rden,
        runlength          => huf_runlength,
        VLI_size           => huf_size,
        VLI                => huf_amplitude,
        d_val              => huf_dval,
        rle_fifo_empty     => huf_fifo_empty,
 
        -- Byte Stuffer
        bs_buf_sel         => bs_buf_sel,
        bs_fifo_empty      => bs_fifo_empty,
        bs_rd_req          => bs_rd_req,
        bs_packed_byte     => bs_packed_byte
    );
 
 
  -------------------------------------------------------------------
  -- Byte Stuffer
  -------------------------------------------------------------------
  U_ByteStuffer : entity work.ByteStuffer
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => bs_start,
        ready_pb           => bs_ready,
 
        -- HOST IF
        sof                => sof,
        num_enc_bytes      => num_enc_bytes,
        outram_base_addr   => outram_base_addr,
 
        -- Huffman
        huf_buf_sel        => bs_buf_sel,
        huf_fifo_empty     => bs_fifo_empty,
        huf_rd_req         => bs_rd_req,
        huf_packed_byte    => bs_packed_byte,
 
        -- OUT RAM
        ram_byte           => bs_ram_byte,
        ram_wren           => bs_ram_wren,
        ram_wraddr         => bs_ram_wraddr
    );
 
  -------------------------------------------------------------------
  -- JFIF Generator
  -------------------------------------------------------------------
  U_JFIFGen : entity work.JFIFGen
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start              => jfif_start,
        ready              => jfif_ready,
        eoi                => jfif_eoi,
 
        -- ByteStuffer
        num_enc_bytes         => num_enc_bytes,
 
        -- HOST IF
        qwren              => qwren,
        qwaddr             => qaddr,
        qwdata             => qdata,
        image_size_reg     => image_size_reg,
        image_size_reg_wr  => img_size_wr,
 
        -- OUT RAM
        ram_byte           => jfif_ram_byte,
        ram_wren           => jfif_ram_wren,
        ram_wraddr         => jfif_ram_wraddr
    );
 
  image_size_reg <= img_size_x & img_size_y;
 
  -------------------------------------------------------------------
  -- OutMux
  -------------------------------------------------------------------
  U_OutMux : entity work.OutMux
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        out_mux_ctrl       => out_mux_ctrl,
 
        -- ByteStuffer
        bs_ram_byte        => bs_ram_byte,
        bs_ram_wren        => bs_ram_wren,
        bs_ram_wraddr      => bs_ram_wraddr,
        -- ByteStuffer
        jfif_ram_byte      => jfif_ram_byte,
        jfif_ram_wren      => jfif_ram_wren,
        jfif_ram_wraddr    => jfif_ram_wraddr,
 
        -- OUT RAM
        ram_byte           => ram_byte,
        ram_wren           => ram_wren,
        ram_wraddr         => ram_wraddr
    );
 
 
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------

Line No.	Rev	Author	Line
1	25	mikel262	`-------------------------------------------------------------------------------`
2			`-- File Name : JpegEnc.vhd`
3			`--`
4			`-- Project : JPEG_ENC`
5			`--`
6			`-- Module : JpegEnc`
7			`--`
8			`-- Content : JPEG Encoder Top Level`
9			`--`
10			`-- Description :`
11			`--`
12			`-- Spec. :`
13			`--`
14			`-- Author : Michal Krepa`
15			`--`
16			`-------------------------------------------------------------------------------`
17			`-- History :`
18			`-- 20090301: (MK): Initial Creation.`
19			`-------------------------------------------------------------------------------`
20
21			`-------------------------------------------------------------------------------`
22			`-------------------------------------------------------------------------------`
23			`----------------------------------- LIBRARY/PACKAGE ---------------------------`
24			`-------------------------------------------------------------------------------`
25			`-------------------------------------------------------------------------------`
26
27			`-------------------------------------------------------------------------------`
28			`-- generic packages/libraries:`
29			`-------------------------------------------------------------------------------`
30			`library ieee;`
31			`use ieee.std_logic_1164.all;`
32			`use ieee.numeric_std.all;`
33
34			`-------------------------------------------------------------------------------`
35			`-- user packages/libraries:`
36			`-------------------------------------------------------------------------------`
37			`library work;`
38			`use work.JPEG_PKG.all;`
39			`-------------------------------------------------------------------------------`
40			`-------------------------------------------------------------------------------`
41			`----------------------------------- ENTITY ------------------------------------`
42			`-------------------------------------------------------------------------------`
43			`-------------------------------------------------------------------------------`
44			`entity JpegEnc is`
45			`port`
46			`(`
47			`CLK : in std_logic;`
48			`RST : in std_logic;`
49
50			`-- OPB`
51			`OPB_ABus : in std_logic_vector(31 downto 0);`
52			`OPB_BE : in std_logic_vector(3 downto 0);`
53			`OPB_DBus_in : in std_logic_vector(31 downto 0);`
54			`OPB_RNW : in std_logic;`
55			`OPB_select : in std_logic;`
56			`OPB_DBus_out : out std_logic_vector(31 downto 0);`
57			`OPB_XferAck : out std_logic;`
58			`OPB_retry : out std_logic;`
59			`OPB_toutSup : out std_logic;`
60			`OPB_errAck : out std_logic;`
61
62			`-- IMAGE RAM`
63			`iram_wdata : in std_logic_vector(23 downto 0);`
64			`iram_wren : in std_logic;`
65			`iram_fifo_afull : out std_logic;`
66
67			`-- OUT RAM`
68			`ram_byte : out std_logic_vector(7 downto 0);`
69			`ram_wren : out std_logic;`
70	42	mikel262	`ram_wraddr : out std_logic_vector(23 downto 0);`
71			`outif_almost_full : in std_logic`
72	25	mikel262	`);`
73			`end entity JpegEnc;`
74
75			`-------------------------------------------------------------------------------`
76			`-------------------------------------------------------------------------------`
77			`----------------------------------- ARCHITECTURE ------------------------------`
78			`-------------------------------------------------------------------------------`
79			`-------------------------------------------------------------------------------`
80			`architecture RTL of JpegEnc is`
81
82			`signal qdata : std_logic_vector(7 downto 0);`
83	32	mikel262	`signal qaddr : std_logic_vector(6 downto 0);`
84	25	mikel262	`signal qwren : std_logic;`
85			`signal jpeg_ready : std_logic;`
86			`signal jpeg_busy : std_logic;`
87			`signal outram_base_addr : std_logic_vector(9 downto 0);`
88			`signal num_enc_bytes : std_logic_vector(23 downto 0);`
89			`signal img_size_x : std_logic_vector(15 downto 0);`
90			`signal img_size_y : std_logic_vector(15 downto 0);`
91			`signal sof : std_logic;`
92			`signal jpg_iram_rden : std_logic;`
93			`signal jpg_iram_rdaddr : std_logic_vector(31 downto 0);`
94			`signal jpg_iram_rdata : std_logic_vector(23 downto 0);`
95			`signal fdct_start : std_logic;`
96			`signal fdct_ready : std_logic;`
97			`signal zig_start : std_logic;`
98			`signal zig_ready : std_logic;`
99	34	mikel262	`signal qua_start : std_logic;`
100			`signal qua_ready : std_logic;`
101	25	mikel262	`signal rle_start : std_logic;`
102			`signal rle_ready : std_logic;`
103			`signal huf_start : std_logic;`
104			`signal huf_ready : std_logic;`
105			`signal bs_start : std_logic;`
106			`signal bs_ready : std_logic;`
107			`signal zz_buf_sel : std_logic;`
108			`signal zz_rd_addr : std_logic_vector(5 downto 0);`
109			`signal zz_data : std_logic_vector(11 downto 0);`
110			`signal rle_buf_sel : std_logic;`
111			`signal rle_rdaddr : std_logic_vector(5 downto 0);`
112			`signal rle_data : std_logic_vector(11 downto 0);`
113	34	mikel262	`signal qua_buf_sel : std_logic;`
114			`signal qua_rdaddr : std_logic_vector(5 downto 0);`
115			`signal qua_data : std_logic_vector(11 downto 0);`
116	25	mikel262	`signal huf_buf_sel : std_logic;`
117			`signal huf_rdaddr : std_logic_vector(5 downto 0);`
118			`signal huf_rden : std_logic;`
119			`signal huf_runlength : std_logic_vector(3 downto 0);`
120			`signal huf_size : std_logic_vector(3 downto 0);`
121			`signal huf_amplitude : std_logic_vector(11 downto 0);`
122			`signal huf_dval : std_logic;`
123			`signal bs_buf_sel : std_logic;`
124			`signal bs_fifo_empty : std_logic;`
125			`signal bs_rd_req : std_logic;`
126			`signal bs_packed_byte : std_logic_vector(7 downto 0);`
127			`signal huf_fifo_empty : std_logic;`
128			`signal zz_rden : std_logic;`
129			`signal fdct_sm_settings : T_SM_SETTINGS;`
130			`signal zig_sm_settings : T_SM_SETTINGS;`
131	34	mikel262	`signal qua_sm_settings : T_SM_SETTINGS;`
132	25	mikel262	`signal rle_sm_settings : T_SM_SETTINGS;`
133			`signal huf_sm_settings : T_SM_SETTINGS;`
134			`signal bs_sm_settings : T_SM_SETTINGS;`
135			`signal cmp_max : std_logic_vector(1 downto 0);`
136			`signal image_size_reg : std_logic_vector(31 downto 0);`
137			`signal jfif_ram_byte : std_logic_vector(7 downto 0);`
138			`signal jfif_ram_wren : std_logic;`
139			`signal jfif_ram_wraddr : std_logic_vector(23 downto 0);`
140			`signal out_mux_ctrl : std_logic;`
141			`signal img_size_wr : std_logic;`
142			`signal jfif_start : std_logic;`
143			`signal jfif_ready : std_logic;`
144			`signal bs_ram_byte : std_logic_vector(7 downto 0);`
145			`signal bs_ram_wren : std_logic;`
146			`signal bs_ram_wraddr : std_logic_vector(23 downto 0);`
147			`signal jfif_eoi : std_logic;`
148			`signal fdct_block_cnt : std_logic_vector(12 downto 0);`
149			`signal fdct_fifo_rd : std_logic;`
150			`signal fdct_fifo_empty : std_logic;`
151			`signal fdct_fifo_q : std_logic_vector(23 downto 0);`
152			`signal fdct_fifo_hf_full : std_logic;`
153
154			`-------------------------------------------------------------------------------`
155			`-- Architecture: begin`
156			`-------------------------------------------------------------------------------`
157			`begin`
158
159			`-------------------------------------------------------------------`
160			`-- Host Interface`
161			`-------------------------------------------------------------------`
162			`U_HostIF : entity work.HostIF`
163			`port map`
164			`(`
165			`CLK => CLK,`
166			`RST => RST,`
167			`-- OPB`
168			`OPB_ABus => OPB_ABus,`
169			`OPB_BE => OPB_BE,`
170			`OPB_DBus_in => OPB_DBus_in,`
171			`OPB_RNW => OPB_RNW,`
172			`OPB_select => OPB_select,`
173			`OPB_DBus_out => OPB_DBus_out,`
174			`OPB_XferAck => OPB_XferAck,`
175			`OPB_retry => OPB_retry,`
176			`OPB_toutSup => OPB_toutSup,`
177			`OPB_errAck => OPB_errAck,`
178
179			`-- Quantizer RAM`
180			`qdata => qdata,`
181			`qaddr => qaddr,`
182			`qwren => qwren,`
183
184			`-- CTRL`
185			`jpeg_ready => jpeg_ready,`
186			`jpeg_busy => jpeg_busy,`
187
188			`-- ByteStuffer`
189			`outram_base_addr => outram_base_addr,`
190			`num_enc_bytes => num_enc_bytes,`
191
192			`-- global`
193			`img_size_x => img_size_x,`
194			`img_size_y => img_size_y,`
195			`img_size_wr => img_size_wr,`
196			`sof => sof,`
197			`cmp_max => cmp_max`
198			`);`
199
200			`-------------------------------------------------------------------`
201			`-- BUF_FIFO`
202			`-------------------------------------------------------------------`
203			`U_BUF_FIFO : entity work.BUF_FIFO`
204			`port map`
205			`(`
206			`CLK => CLK,`
207			`RST => RST,`
208			`-- HOST PROG`
209			`img_size_x => img_size_x,`
210			`img_size_y => img_size_y,`
211			`sof => sof,`
212
213			`-- HOST DATA`
214			`iram_wren => iram_wren,`
215			`iram_wdata => iram_wdata,`
216			`fifo_almost_full => iram_fifo_afull,`
217
218			`-- FDCT`
219			`fdct_block_cnt => fdct_block_cnt,`
220			`fdct_fifo_rd => fdct_fifo_rd,`
221			`fdct_fifo_empty => fdct_fifo_empty,`
222			`fdct_fifo_q => fdct_fifo_q,`
223			`fdct_fifo_hf_full => fdct_fifo_hf_full`
224			`);`
225
226			`-------------------------------------------------------------------`
227			`-- Controller`
228			`-------------------------------------------------------------------`
229			`U_CtrlSM : entity work.CtrlSM`
230			`port map`
231			`(`
232			`CLK => CLK,`
233			`RST => RST,`
234	42	mikel262
235			`-- output IF`
236			`outif_almost_full => outif_almost_full,`
237	25	mikel262
238			`-- HOST IF`
239			`sof => sof,`
240			`img_size_x => img_size_x,`
241			`img_size_y => img_size_y,`
242			`jpeg_ready => jpeg_ready,`
243			`jpeg_busy => jpeg_busy,`
244			`cmp_max => cmp_max,`
245
246			`-- FDCT`
247			`fdct_start => fdct_start,`
248			`fdct_ready => fdct_ready,`
249			`fdct_sm_settings => fdct_sm_settings,`
250
251			`-- ZIGZAG`
252			`zig_start => zig_start,`
253			`zig_ready => zig_ready,`
254			`zig_sm_settings => zig_sm_settings,`
255	34	mikel262
256			`-- Quantizer`
257			`qua_start => qua_start,`
258			`qua_ready => qua_ready,`
259			`qua_sm_settings => qua_sm_settings,`
260	25	mikel262
261			`-- RLE`
262			`rle_start => rle_start,`
263			`rle_ready => rle_ready,`
264			`rle_sm_settings => rle_sm_settings,`
265
266			`-- Huffman`
267			`huf_start => huf_start,`
268			`huf_ready => huf_ready,`
269			`huf_sm_settings => huf_sm_settings,`
270
271			`-- ByteStuffdr`
272			`bs_start => bs_start,`
273			`bs_ready => bs_ready,`
274			`bs_sm_settings => bs_sm_settings,`
275
276			`-- JFIF GEN`
277			`jfif_start => jfif_start,`
278			`jfif_ready => jfif_ready,`
279			`jfif_eoi => jfif_eoi,`
280
281			`-- OUT MUX`
282			`out_mux_ctrl => out_mux_ctrl`
283			`);`
284
285			`-------------------------------------------------------------------`
286			`-- FDCT`
287			`-------------------------------------------------------------------`
288			`U_FDCT : entity work.FDCT`
289			`port map`
290			`(`
291			`CLK => CLK,`
292			`RST => RST,`
293			`-- CTRL`
294			`start_pb => fdct_start,`
295			`ready_pb => fdct_ready,`
296			`fdct_sm_settings => fdct_sm_settings,`
297
298			`-- BUF_FIFO`
299			`bf_block_cnt => fdct_block_cnt,`
300			`bf_fifo_rd => fdct_fifo_rd,`
301			`bf_fifo_empty => fdct_fifo_empty,`
302			`bf_fifo_q => fdct_fifo_q,`
303			`bf_fifo_hf_full => fdct_fifo_hf_full,`
304
305			`-- ZIG ZAG`
306			`zz_buf_sel => zz_buf_sel,`
307			`zz_rd_addr => zz_rd_addr,`
308			`zz_data => zz_data,`
309			`zz_rden => zz_rden,`
310
311			`-- HOST`
312			`img_size_x => img_size_x,`
313			`img_size_y => img_size_y,`
314			`sof => sof`
315			`);`
316
317			`-------------------------------------------------------------------`
318			`-- ZigZag top level`
319			`-------------------------------------------------------------------`
320			`U_ZZ_TOP : entity work.ZZ_TOP`
321			`port map`
322			`(`
323			`CLK => CLK,`
324			`RST => RST,`
325			`-- CTRL`
326			`start_pb => zig_start,`
327			`ready_pb => zig_ready,`
328	32	mikel262	`zig_sm_settings => zig_sm_settings,`
329	25	mikel262
330	34	mikel262	`-- Quantizer`
331			`qua_buf_sel => qua_buf_sel,`
332			`qua_rdaddr => qua_rdaddr,`
333			`qua_data => qua_data,`
334	25	mikel262
335			`-- FDCT`
336			`fdct_buf_sel => zz_buf_sel,`
337			`fdct_rd_addr => zz_rd_addr,`
338			`fdct_data => zz_data,`
339	34	mikel262	`fdct_rden => zz_rden`
340			`);`
341
342			`-------------------------------------------------------------------`
343			`-- Quantizer top level`
344			`-------------------------------------------------------------------`
345			`U_QUANT_TOP : entity work.QUANT_TOP`
346			`port map`
347			`(`
348			`CLK => CLK,`
349			`RST => RST,`
350			`-- CTRL`
351			`start_pb => qua_start,`
352			`ready_pb => qua_ready,`
353			`qua_sm_settings => qua_sm_settings,`
354	25	mikel262
355	34	mikel262	`-- RLE`
356			`rle_buf_sel => rle_buf_sel,`
357			`rle_rdaddr => rle_rdaddr,`
358			`rle_data => rle_data,`
359
360			`-- ZIGZAG`
361			`zig_buf_sel => qua_buf_sel,`
362			`zig_rd_addr => qua_rdaddr,`
363			`zig_data => qua_data,`
364
365	25	mikel262	`-- HOST`
366			`qdata => qdata,`
367			`qaddr => qaddr,`
368			`qwren => qwren`
369	34	mikel262	`);`
370
371	25	mikel262	`-------------------------------------------------------------------`
372			`-- RLE TOP`
373			`-------------------------------------------------------------------`
374			`U_RLE_TOP : entity work.RLE_TOP`
375			`port map`
376			`(`
377			`CLK => CLK,`
378			`RST => RST,`
379			`-- CTRL`
380			`start_pb => rle_start,`
381			`ready_pb => rle_ready,`
382			`rle_sm_settings => rle_sm_settings,`
383
384			`-- HUFFMAN`
385			`huf_buf_sel => huf_buf_sel,`
386			`huf_rden => huf_rden,`
387			`huf_runlength => huf_runlength,`
388			`huf_size => huf_size,`
389			`huf_amplitude => huf_amplitude,`
390			`huf_dval => huf_dval,`
391			`huf_fifo_empty => huf_fifo_empty,`
392
393	34	mikel262	`-- Quantizer`
394			`qua_buf_sel => rle_buf_sel,`
395			`qua_rd_addr => rle_rdaddr,`
396			`qua_data => rle_data,`
397	25	mikel262
398			`-- HostIF`
399			`sof => sof`
400			`);`
401
402			`-------------------------------------------------------------------`
403			`-- Huffman Encoder`
404			`-------------------------------------------------------------------`
405			`U_Huffman : entity work.Huffman`
406			`port map`
407			`(`
408			`CLK => CLK,`
409			`RST => RST,`
410			`-- CTRL`
411			`start_pb => huf_start,`
412			`ready_pb => huf_ready,`
413	36	mikel262	`huf_sm_settings => huf_sm_settings,`
414	25	mikel262
415			`-- HOST IF`
416			`sof => sof,`
417			`img_size_x => img_size_x,`
418			`img_size_y => img_size_y,`
419			`cmp_max => cmp_max,`
420
421			`-- RLE`
422			`rle_buf_sel => huf_buf_sel,`
423			`rd_en => huf_rden,`
424			`runlength => huf_runlength,`
425			`VLI_size => huf_size,`
426			`VLI => huf_amplitude,`
427			`d_val => huf_dval,`
428			`rle_fifo_empty => huf_fifo_empty,`
429
430			`-- Byte Stuffer`
431			`bs_buf_sel => bs_buf_sel,`
432			`bs_fifo_empty => bs_fifo_empty,`
433			`bs_rd_req => bs_rd_req,`
434			`bs_packed_byte => bs_packed_byte`
435			`);`
436
437
438			`-------------------------------------------------------------------`
439			`-- Byte Stuffer`
440			`-------------------------------------------------------------------`
441			`U_ByteStuffer : entity work.ByteStuffer`
442			`port map`
443			`(`
444			`CLK => CLK,`
445			`RST => RST,`
446			`-- CTRL`
447			`start_pb => bs_start,`
448			`ready_pb => bs_ready,`
449
450			`-- HOST IF`
451			`sof => sof,`
452			`num_enc_bytes => num_enc_bytes,`
453			`outram_base_addr => outram_base_addr,`
454
455			`-- Huffman`
456			`huf_buf_sel => bs_buf_sel,`
457			`huf_fifo_empty => bs_fifo_empty,`
458			`huf_rd_req => bs_rd_req,`
459			`huf_packed_byte => bs_packed_byte,`
460
461			`-- OUT RAM`
462			`ram_byte => bs_ram_byte,`
463			`ram_wren => bs_ram_wren,`
464			`ram_wraddr => bs_ram_wraddr`
465			`);`
466
467			`-------------------------------------------------------------------`
468			`-- JFIF Generator`
469			`-------------------------------------------------------------------`
470			`U_JFIFGen : entity work.JFIFGen`
471			`port map`
472			`(`
473			`CLK => CLK,`
474			`RST => RST,`
475			`-- CTRL`
476			`start => jfif_start,`
477			`ready => jfif_ready,`
478			`eoi => jfif_eoi,`
479
480			`-- ByteStuffer`
481			`num_enc_bytes => num_enc_bytes,`
482
483			`-- HOST IF`
484			`qwren => qwren,`
485			`qwaddr => qaddr,`
486			`qwdata => qdata,`
487			`image_size_reg => image_size_reg,`
488			`image_size_reg_wr => img_size_wr,`
489
490			`-- OUT RAM`
491			`ram_byte => jfif_ram_byte,`
492			`ram_wren => jfif_ram_wren,`
493			`ram_wraddr => jfif_ram_wraddr`
494			`);`
495
496			`image_size_reg <= img_size_x & img_size_y;`
497
498			`-------------------------------------------------------------------`
499			`-- OutMux`
500			`-------------------------------------------------------------------`

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