URL https://opencores.org/ocsvn/mkjpeg/mkjpeg/trunk

Subversion Repositories mkjpeg

[/] [mkjpeg/] [trunk/] [design/] [top/] [JpegEnc.vhd] - Blame information for rev 46

Go to most recent revision | Details | Compare with Previous | View Log


-------------------------------------------------------------------------------
-- File Name : JpegEnc.vhd
--
-- Project   : JPEG_ENC
--
-- Module    : JpegEnc
--
-- Content   : JPEG Encoder Top Level
--
-- Description : 
--
-- Spec.     : 
--
-- Author    : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
 
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
  use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JpegEnc is
  port
  (
        CLK                : in  std_logic;
        RST                : in  std_logic;
 
        -- OPB
        OPB_ABus           : in  std_logic_vector(31 downto 0);
        OPB_BE             : in  std_logic_vector(3 downto 0);
        OPB_DBus_in        : in  std_logic_vector(31 downto 0);
        OPB_RNW            : in  std_logic;
        OPB_select         : in  std_logic;
        OPB_DBus_out       : out std_logic_vector(31 downto 0);
        OPB_XferAck        : out std_logic;
        OPB_retry          : out std_logic;
        OPB_toutSup        : out std_logic;
        OPB_errAck         : out std_logic;
 
        -- IMAGE RAM
        iram_wdata         : in  std_logic_vector(23 downto 0);
        iram_wren          : in  std_logic;
        iram_fifo_afull    : out std_logic;
 
        -- OUT RAM
        ram_byte           : out std_logic_vector(7 downto 0);
        ram_wren           : out std_logic;
        ram_wraddr         : out std_logic_vector(23 downto 0);
        outif_almost_full  : in  std_logic
   );
end entity JpegEnc;
 
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JpegEnc is
 
  signal qdata              : std_logic_vector(7 downto 0);
  signal qaddr              : std_logic_vector(6 downto 0);
  signal qwren              : std_logic;
  signal jpeg_ready         : std_logic;
  signal jpeg_busy          : std_logic;
  signal outram_base_addr   : std_logic_vector(9 downto 0);
  signal num_enc_bytes      : std_logic_vector(23 downto 0);
  signal img_size_x         : std_logic_vector(15 downto 0);
  signal img_size_y         : std_logic_vector(15 downto 0);
  signal sof                : std_logic;
  signal jpg_iram_rden      : std_logic;
  signal jpg_iram_rdaddr    : std_logic_vector(31 downto 0);
  signal jpg_iram_rdata     : std_logic_vector(23 downto 0);
  signal fdct_start         : std_logic;
  signal fdct_ready         : std_logic;
  signal zig_start          : std_logic;
  signal zig_ready          : std_logic;
  signal qua_start          : std_logic;
  signal qua_ready          : std_logic;
  signal rle_start          : std_logic;
  signal rle_ready          : std_logic;
  signal huf_start          : std_logic;
  signal huf_ready          : std_logic;
  signal bs_start           : std_logic;
  signal bs_ready           : std_logic;
  signal zz_buf_sel         : std_logic;
  signal zz_rd_addr         : std_logic_vector(5 downto 0);
  signal zz_data            : std_logic_vector(11 downto 0);
  signal rle_buf_sel        : std_logic;
  signal rle_rdaddr         : std_logic_vector(5 downto 0);
  signal rle_data           : std_logic_vector(11 downto 0);
  signal qua_buf_sel        : std_logic;
  signal qua_rdaddr         : std_logic_vector(5 downto 0);
  signal qua_data           : std_logic_vector(11 downto 0);
  signal huf_buf_sel        : std_logic;
  signal huf_rdaddr         : std_logic_vector(5 downto 0);
  signal huf_rden           : std_logic;
  signal huf_runlength      : std_logic_vector(3 downto 0);
  signal huf_size           : std_logic_vector(3 downto 0);
  signal huf_amplitude      : std_logic_vector(11 downto 0);
  signal huf_dval           : std_logic;
  signal bs_buf_sel         : std_logic;
  signal bs_fifo_empty      : std_logic;
  signal bs_rd_req          : std_logic;
  signal bs_packed_byte     : std_logic_vector(7 downto 0);
  signal huf_fifo_empty     : std_logic;
  signal zz_rden            : std_logic;
  signal fdct_sm_settings   : T_SM_SETTINGS;
  signal zig_sm_settings    : T_SM_SETTINGS;
  signal qua_sm_settings    : T_SM_SETTINGS;
  signal rle_sm_settings    : T_SM_SETTINGS;
  signal huf_sm_settings    : T_SM_SETTINGS;
  signal bs_sm_settings     : T_SM_SETTINGS;
  signal cmp_max            : std_logic_vector(1 downto 0);
  signal image_size_reg     : std_logic_vector(31 downto 0);
  signal jfif_ram_byte      : std_logic_vector(7 downto 0);
  signal jfif_ram_wren      : std_logic;
  signal jfif_ram_wraddr    : std_logic_vector(23 downto 0);
  signal out_mux_ctrl       : std_logic;
  signal img_size_wr        : std_logic;
  signal jfif_start         : std_logic;
  signal jfif_ready         : std_logic;
  signal bs_ram_byte        : std_logic_vector(7 downto 0);
  signal bs_ram_wren        : std_logic;
  signal bs_ram_wraddr      : std_logic_vector(23 downto 0);
  signal jfif_eoi           : std_logic;
  signal fdct_block_cnt     : std_logic_vector(12 downto 0);
  signal fdct_fifo_rd       : std_logic;
  signal fdct_fifo_empty    : std_logic;
  signal fdct_fifo_q        : std_logic_vector(23 downto 0);
  signal fdct_fifo_hf_full  : std_logic;
 
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
 
  -------------------------------------------------------------------
  -- Host Interface
  -------------------------------------------------------------------
  U_HostIF : entity work.HostIF
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- OPB
        OPB_ABus           => OPB_ABus,
        OPB_BE             => OPB_BE,
        OPB_DBus_in        => OPB_DBus_in,
        OPB_RNW            => OPB_RNW,
        OPB_select         => OPB_select,
        OPB_DBus_out       => OPB_DBus_out,
        OPB_XferAck        => OPB_XferAck,
        OPB_retry          => OPB_retry,
        OPB_toutSup        => OPB_toutSup,
        OPB_errAck         => OPB_errAck,
 
        -- Quantizer RAM
        qdata              => qdata,
        qaddr              => qaddr,
        qwren              => qwren,
 
        -- CTRL
        jpeg_ready         => jpeg_ready,
        jpeg_busy          => jpeg_busy,
 
        -- ByteStuffer
        outram_base_addr   => outram_base_addr,
        num_enc_bytes      => num_enc_bytes,
 
        -- global
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        img_size_wr        => img_size_wr,
        sof                => sof,
        cmp_max            => cmp_max
    );
 
  -------------------------------------------------------------------
  -- BUF_FIFO
  -------------------------------------------------------------------
  U_BUF_FIFO : entity work.BUF_FIFO
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- HOST PROG
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        sof                => sof,
 
        -- HOST DATA
        iram_wren          => iram_wren,
        iram_wdata         => iram_wdata,
        fifo_almost_full   => iram_fifo_afull,
 
        -- FDCT
        fdct_block_cnt     => fdct_block_cnt,
        fdct_fifo_rd       => fdct_fifo_rd,
        fdct_fifo_empty    => fdct_fifo_empty,
        fdct_fifo_q        => fdct_fifo_q,
        fdct_fifo_hf_full  => fdct_fifo_hf_full
    );
 
  -------------------------------------------------------------------
  -- Controller
  -------------------------------------------------------------------
  U_CtrlSM : entity work.CtrlSM
  port map
  (
        CLK                => CLK,
        RST                => RST,
 
        -- output IF
        outif_almost_full  => outif_almost_full,
 
        -- HOST IF
        sof                => sof,
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        jpeg_ready         => jpeg_ready,
        jpeg_busy          => jpeg_busy,
        cmp_max            => cmp_max,
 
        -- FDCT
        fdct_start         => fdct_start,
        fdct_ready         => fdct_ready,
        fdct_sm_settings   => fdct_sm_settings,
 
        -- ZIGZAG
        zig_start          => zig_start,
        zig_ready          => zig_ready,
        zig_sm_settings    => zig_sm_settings,
 
        -- Quantizer
        qua_start          => qua_start,
        qua_ready          => qua_ready,
        qua_sm_settings    => qua_sm_settings,
 
        -- RLE
        rle_start          => rle_start,
        rle_ready          => rle_ready,
        rle_sm_settings    => rle_sm_settings,
 
        -- Huffman
        huf_start          => huf_start,
        huf_ready          => huf_ready,
        huf_sm_settings    => huf_sm_settings,
 
        -- ByteStuffdr
        bs_start           => bs_start,
        bs_ready           => bs_ready,
        bs_sm_settings     => bs_sm_settings,
 
        -- JFIF GEN
        jfif_start         => jfif_start,
        jfif_ready         => jfif_ready,
        jfif_eoi           => jfif_eoi,
 
        -- OUT MUX         
        out_mux_ctrl       => out_mux_ctrl
    );
 
  -------------------------------------------------------------------
  -- FDCT
  -------------------------------------------------------------------
  U_FDCT : entity work.FDCT
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => fdct_start,
        ready_pb           => fdct_ready,
        fdct_sm_settings   => fdct_sm_settings,
 
        -- BUF_FIFO
        bf_block_cnt       => fdct_block_cnt,
        bf_fifo_rd         => fdct_fifo_rd,
        bf_fifo_empty      => fdct_fifo_empty,
        bf_fifo_q          => fdct_fifo_q,
        bf_fifo_hf_full    => fdct_fifo_hf_full,
 
        -- ZIG ZAG
        zz_buf_sel         => zz_buf_sel,
        zz_rd_addr         => zz_rd_addr,
        zz_data            => zz_data,
        zz_rden            => zz_rden,
 
        -- HOST
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        sof                => sof
    );
 
  -------------------------------------------------------------------
  -- ZigZag top level
  -------------------------------------------------------------------
  U_ZZ_TOP : entity work.ZZ_TOP
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => zig_start,
        ready_pb           => zig_ready,
        zig_sm_settings    => zig_sm_settings,
 
        -- Quantizer
        qua_buf_sel        => qua_buf_sel,
        qua_rdaddr         => qua_rdaddr,
        qua_data           => qua_data,
 
        -- FDCT
        fdct_buf_sel       => zz_buf_sel,
        fdct_rd_addr       => zz_rd_addr,
        fdct_data          => zz_data,
        fdct_rden          => zz_rden
    );
 
  -------------------------------------------------------------------
  -- Quantizer top level
  -------------------------------------------------------------------
  U_QUANT_TOP : entity work.QUANT_TOP
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => qua_start,
        ready_pb           => qua_ready,
        qua_sm_settings    => qua_sm_settings,
 
        -- RLE
        rle_buf_sel        => rle_buf_sel,
        rle_rdaddr         => rle_rdaddr,
        rle_data           => rle_data,
 
        -- ZIGZAG
        zig_buf_sel        => qua_buf_sel,
        zig_rd_addr        => qua_rdaddr,
        zig_data           => qua_data,
 
        -- HOST
        qdata              => qdata,
        qaddr              => qaddr,
        qwren              => qwren
    );
 
  -------------------------------------------------------------------
  -- RLE TOP
  -------------------------------------------------------------------
  U_RLE_TOP : entity work.RLE_TOP
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => rle_start,
        ready_pb           => rle_ready,
        rle_sm_settings    => rle_sm_settings,
 
        -- HUFFMAN
        huf_buf_sel        => huf_buf_sel,
        huf_rden           => huf_rden,
        huf_runlength      => huf_runlength,
        huf_size           => huf_size,
        huf_amplitude      => huf_amplitude,
        huf_dval           => huf_dval,
        huf_fifo_empty     => huf_fifo_empty,
 
        -- Quantizer
        qua_buf_sel        => rle_buf_sel,
        qua_rd_addr        => rle_rdaddr,
        qua_data           => rle_data,
 
        -- HostIF
        sof                => sof
    );
 
  -------------------------------------------------------------------
  -- Huffman Encoder
  -------------------------------------------------------------------
  U_Huffman : entity work.Huffman
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => huf_start,
        ready_pb           => huf_ready,
        huf_sm_settings    => huf_sm_settings,
 
        -- HOST IF
        sof                => sof,
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        cmp_max            => cmp_max,
 
        -- RLE
        rle_buf_sel        => huf_buf_sel,
        rd_en              => huf_rden,
        runlength          => huf_runlength,
        VLI_size           => huf_size,
        VLI                => huf_amplitude,
        d_val              => huf_dval,
        rle_fifo_empty     => huf_fifo_empty,
 
        -- Byte Stuffer
        bs_buf_sel         => bs_buf_sel,
        bs_fifo_empty      => bs_fifo_empty,
        bs_rd_req          => bs_rd_req,
        bs_packed_byte     => bs_packed_byte
    );
 
 
  -------------------------------------------------------------------
  -- Byte Stuffer
  -------------------------------------------------------------------
  U_ByteStuffer : entity work.ByteStuffer
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => bs_start,
        ready_pb           => bs_ready,
 
        -- HOST IF
        sof                => sof,
        num_enc_bytes      => num_enc_bytes,
        outram_base_addr   => outram_base_addr,
 
        -- Huffman
        huf_buf_sel        => bs_buf_sel,
        huf_fifo_empty     => bs_fifo_empty,
        huf_rd_req         => bs_rd_req,
        huf_packed_byte    => bs_packed_byte,
 
        -- OUT RAM
        ram_byte           => bs_ram_byte,
        ram_wren           => bs_ram_wren,
        ram_wraddr         => bs_ram_wraddr
    );
 
  -------------------------------------------------------------------
  -- JFIF Generator
  -------------------------------------------------------------------
  U_JFIFGen : entity work.JFIFGen
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start              => jfif_start,
        ready              => jfif_ready,
        eoi                => jfif_eoi,
 
        -- ByteStuffer
        num_enc_bytes         => num_enc_bytes,
 
        -- HOST IF
        qwren              => qwren,
        qwaddr             => qaddr,
        qwdata             => qdata,
        image_size_reg     => image_size_reg,
        image_size_reg_wr  => img_size_wr,
 
        -- OUT RAM
        ram_byte           => jfif_ram_byte,
        ram_wren           => jfif_ram_wren,
        ram_wraddr         => jfif_ram_wraddr
    );
 
  image_size_reg <= img_size_x & img_size_y;
 
  -------------------------------------------------------------------
  -- OutMux
  -------------------------------------------------------------------
  U_OutMux : entity work.OutMux
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        out_mux_ctrl       => out_mux_ctrl,
 
        -- ByteStuffer
        bs_ram_byte        => bs_ram_byte,
        bs_ram_wren        => bs_ram_wren,
        bs_ram_wraddr      => bs_ram_wraddr,
        -- ByteStuffer
        jfif_ram_byte      => jfif_ram_byte,
        jfif_ram_wren      => jfif_ram_wren,
        jfif_ram_wraddr    => jfif_ram_wraddr,
 
        -- OUT RAM
        ram_byte           => ram_byte,
        ram_wren           => ram_wren,
        ram_wraddr         => ram_wraddr
    );
 
 
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------

Line No.	Rev	Author	Line
1	25	mikel262	`-------------------------------------------------------------------------------`
2			`-- File Name : JpegEnc.vhd`
3			`--`
4			`-- Project : JPEG_ENC`
5			`--`
6			`-- Module : JpegEnc`
7			`--`
8			`-- Content : JPEG Encoder Top Level`
9			`--`
10			`-- Description :`
11			`--`
12			`-- Spec. :`
13			`--`
14			`-- Author : Michal Krepa`
15			`--`
16			`-------------------------------------------------------------------------------`
17			`-- History :`
18			`-- 20090301: (MK): Initial Creation.`
19			`-------------------------------------------------------------------------------`
20
21			`-------------------------------------------------------------------------------`
22			`-------------------------------------------------------------------------------`
23			`----------------------------------- LIBRARY/PACKAGE ---------------------------`
24			`-------------------------------------------------------------------------------`
25			`-------------------------------------------------------------------------------`
26
27			`-------------------------------------------------------------------------------`
28			`-- generic packages/libraries:`
29			`-------------------------------------------------------------------------------`
30			`library ieee;`
31			`use ieee.std_logic_1164.all;`
32			`use ieee.numeric_std.all;`
33
34			`-------------------------------------------------------------------------------`
35			`-- user packages/libraries:`
36			`-------------------------------------------------------------------------------`
37			`library work;`
38			`use work.JPEG_PKG.all;`
39			`-------------------------------------------------------------------------------`
40			`-------------------------------------------------------------------------------`
41			`----------------------------------- ENTITY ------------------------------------`
42			`-------------------------------------------------------------------------------`
43			`-------------------------------------------------------------------------------`
44			`entity JpegEnc is`
45			`port`
46			`(`
47			`CLK : in std_logic;`
48			`RST : in std_logic;`
49
50			`-- OPB`
51			`OPB_ABus : in std_logic_vector(31 downto 0);`
52			`OPB_BE : in std_logic_vector(3 downto 0);`
53			`OPB_DBus_in : in std_logic_vector(31 downto 0);`
54			`OPB_RNW : in std_logic;`
55			`OPB_select : in std_logic;`
56			`OPB_DBus_out : out std_logic_vector(31 downto 0);`
57			`OPB_XferAck : out std_logic;`
58			`OPB_retry : out std_logic;`
59			`OPB_toutSup : out std_logic;`
60			`OPB_errAck : out std_logic;`
61
62			`-- IMAGE RAM`
63			`iram_wdata : in std_logic_vector(23 downto 0);`
64			`iram_wren : in std_logic;`
65			`iram_fifo_afull : out std_logic;`
66
67			`-- OUT RAM`
68			`ram_byte : out std_logic_vector(7 downto 0);`
69			`ram_wren : out std_logic;`
70	42	mikel262	`ram_wraddr : out std_logic_vector(23 downto 0);`
71			`outif_almost_full : in std_logic`
72	46	mikel262	`);`
73	25	mikel262	`end entity JpegEnc;`
74
75	43	mikel262
76	25	mikel262	`-------------------------------------------------------------------------------`
77			`-------------------------------------------------------------------------------`
78			`----------------------------------- ARCHITECTURE ------------------------------`
79			`-------------------------------------------------------------------------------`
80			`-------------------------------------------------------------------------------`
81			`architecture RTL of JpegEnc is`
82
83			`signal qdata : std_logic_vector(7 downto 0);`
84	32	mikel262	`signal qaddr : std_logic_vector(6 downto 0);`
85	25	mikel262	`signal qwren : std_logic;`
86			`signal jpeg_ready : std_logic;`
87			`signal jpeg_busy : std_logic;`
88			`signal outram_base_addr : std_logic_vector(9 downto 0);`
89			`signal num_enc_bytes : std_logic_vector(23 downto 0);`
90			`signal img_size_x : std_logic_vector(15 downto 0);`
91			`signal img_size_y : std_logic_vector(15 downto 0);`
92			`signal sof : std_logic;`
93			`signal jpg_iram_rden : std_logic;`
94			`signal jpg_iram_rdaddr : std_logic_vector(31 downto 0);`
95			`signal jpg_iram_rdata : std_logic_vector(23 downto 0);`
96			`signal fdct_start : std_logic;`
97			`signal fdct_ready : std_logic;`
98			`signal zig_start : std_logic;`
99			`signal zig_ready : std_logic;`
100	34	mikel262	`signal qua_start : std_logic;`
101			`signal qua_ready : std_logic;`
102	25	mikel262	`signal rle_start : std_logic;`
103			`signal rle_ready : std_logic;`
104			`signal huf_start : std_logic;`
105			`signal huf_ready : std_logic;`
106			`signal bs_start : std_logic;`
107			`signal bs_ready : std_logic;`
108			`signal zz_buf_sel : std_logic;`
109			`signal zz_rd_addr : std_logic_vector(5 downto 0);`
110			`signal zz_data : std_logic_vector(11 downto 0);`
111			`signal rle_buf_sel : std_logic;`
112			`signal rle_rdaddr : std_logic_vector(5 downto 0);`
113			`signal rle_data : std_logic_vector(11 downto 0);`
114	34	mikel262	`signal qua_buf_sel : std_logic;`
115			`signal qua_rdaddr : std_logic_vector(5 downto 0);`
116			`signal qua_data : std_logic_vector(11 downto 0);`
117	25	mikel262	`signal huf_buf_sel : std_logic;`
118			`signal huf_rdaddr : std_logic_vector(5 downto 0);`
119			`signal huf_rden : std_logic;`
120			`signal huf_runlength : std_logic_vector(3 downto 0);`
121			`signal huf_size : std_logic_vector(3 downto 0);`
122			`signal huf_amplitude : std_logic_vector(11 downto 0);`
123			`signal huf_dval : std_logic;`
124			`signal bs_buf_sel : std_logic;`
125			`signal bs_fifo_empty : std_logic;`
126			`signal bs_rd_req : std_logic;`
127			`signal bs_packed_byte : std_logic_vector(7 downto 0);`
128			`signal huf_fifo_empty : std_logic;`
129			`signal zz_rden : std_logic;`
130			`signal fdct_sm_settings : T_SM_SETTINGS;`
131			`signal zig_sm_settings : T_SM_SETTINGS;`
132	34	mikel262	`signal qua_sm_settings : T_SM_SETTINGS;`
133	25	mikel262	`signal rle_sm_settings : T_SM_SETTINGS;`
134			`signal huf_sm_settings : T_SM_SETTINGS;`
135			`signal bs_sm_settings : T_SM_SETTINGS;`
136			`signal cmp_max : std_logic_vector(1 downto 0);`
137			`signal image_size_reg : std_logic_vector(31 downto 0);`
138			`signal jfif_ram_byte : std_logic_vector(7 downto 0);`
139			`signal jfif_ram_wren : std_logic;`
140			`signal jfif_ram_wraddr : std_logic_vector(23 downto 0);`
141			`signal out_mux_ctrl : std_logic;`
142			`signal img_size_wr : std_logic;`
143			`signal jfif_start : std_logic;`
144			`signal jfif_ready : std_logic;`
145			`signal bs_ram_byte : std_logic_vector(7 downto 0);`
146			`signal bs_ram_wren : std_logic;`
147			`signal bs_ram_wraddr : std_logic_vector(23 downto 0);`
148			`signal jfif_eoi : std_logic;`
149			`signal fdct_block_cnt : std_logic_vector(12 downto 0);`
150			`signal fdct_fifo_rd : std_logic;`
151			`signal fdct_fifo_empty : std_logic;`
152			`signal fdct_fifo_q : std_logic_vector(23 downto 0);`
153			`signal fdct_fifo_hf_full : std_logic;`
154
155			`-------------------------------------------------------------------------------`
156			`-- Architecture: begin`
157			`-------------------------------------------------------------------------------`
158			`begin`
159
160			`-------------------------------------------------------------------`
161			`-- Host Interface`
162			`-------------------------------------------------------------------`
163			`U_HostIF : entity work.HostIF`
164			`port map`
165			`(`
166			`CLK => CLK,`
167			`RST => RST,`
168			`-- OPB`
169			`OPB_ABus => OPB_ABus,`
170			`OPB_BE => OPB_BE,`
171			`OPB_DBus_in => OPB_DBus_in,`
172			`OPB_RNW => OPB_RNW,`
173			`OPB_select => OPB_select,`
174			`OPB_DBus_out => OPB_DBus_out,`
175			`OPB_XferAck => OPB_XferAck,`
176			`OPB_retry => OPB_retry,`
177			`OPB_toutSup => OPB_toutSup,`
178			`OPB_errAck => OPB_errAck,`
179
180			`-- Quantizer RAM`
181			`qdata => qdata,`
182			`qaddr => qaddr,`
183			`qwren => qwren,`
184
185			`-- CTRL`
186			`jpeg_ready => jpeg_ready,`
187			`jpeg_busy => jpeg_busy,`
188
189			`-- ByteStuffer`
190			`outram_base_addr => outram_base_addr,`
191			`num_enc_bytes => num_enc_bytes,`
192
193			`-- global`
194			`img_size_x => img_size_x,`
195			`img_size_y => img_size_y,`
196			`img_size_wr => img_size_wr,`
197			`sof => sof,`
198			`cmp_max => cmp_max`
199			`);`
200
201			`-------------------------------------------------------------------`
202			`-- BUF_FIFO`
203			`-------------------------------------------------------------------`
204			`U_BUF_FIFO : entity work.BUF_FIFO`
205			`port map`
206			`(`
207			`CLK => CLK,`
208			`RST => RST,`
209			`-- HOST PROG`
210			`img_size_x => img_size_x,`
211			`img_size_y => img_size_y,`
212			`sof => sof,`
213
214			`-- HOST DATA`
215			`iram_wren => iram_wren,`
216			`iram_wdata => iram_wdata,`
217			`fifo_almost_full => iram_fifo_afull,`
218
219			`-- FDCT`
220			`fdct_block_cnt => fdct_block_cnt,`
221			`fdct_fifo_rd => fdct_fifo_rd,`
222			`fdct_fifo_empty => fdct_fifo_empty,`
223			`fdct_fifo_q => fdct_fifo_q,`
224			`fdct_fifo_hf_full => fdct_fifo_hf_full`
225			`);`
226
227			`-------------------------------------------------------------------`
228			`-- Controller`
229			`-------------------------------------------------------------------`
230			`U_CtrlSM : entity work.CtrlSM`
231			`port map`
232			`(`
233			`CLK => CLK,`
234			`RST => RST,`
235	42	mikel262
236			`-- output IF`
237			`outif_almost_full => outif_almost_full,`
238	25	mikel262
239			`-- HOST IF`
240			`sof => sof,`
241			`img_size_x => img_size_x,`
242			`img_size_y => img_size_y,`
243			`jpeg_ready => jpeg_ready,`
244			`jpeg_busy => jpeg_busy,`
245			`cmp_max => cmp_max,`
246
247			`-- FDCT`
248			`fdct_start => fdct_start,`
249			`fdct_ready => fdct_ready,`
250			`fdct_sm_settings => fdct_sm_settings,`
251
252			`-- ZIGZAG`
253			`zig_start => zig_start,`
254			`zig_ready => zig_ready,`
255			`zig_sm_settings => zig_sm_settings,`
256	34	mikel262
257			`-- Quantizer`
258			`qua_start => qua_start,`
259			`qua_ready => qua_ready,`
260			`qua_sm_settings => qua_sm_settings,`
261	25	mikel262
262			`-- RLE`
263			`rle_start => rle_start,`
264			`rle_ready => rle_ready,`
265			`rle_sm_settings => rle_sm_settings,`
266
267			`-- Huffman`
268			`huf_start => huf_start,`
269			`huf_ready => huf_ready,`
270			`huf_sm_settings => huf_sm_settings,`
271
272			`-- ByteStuffdr`
273			`bs_start => bs_start,`
274			`bs_ready => bs_ready,`
275			`bs_sm_settings => bs_sm_settings,`
276
277			`-- JFIF GEN`
278			`jfif_start => jfif_start,`
279			`jfif_ready => jfif_ready,`
280			`jfif_eoi => jfif_eoi,`
281
282			`-- OUT MUX`
283			`out_mux_ctrl => out_mux_ctrl`
284			`);`
285
286			`-------------------------------------------------------------------`
287			`-- FDCT`
288			`-------------------------------------------------------------------`
289			`U_FDCT : entity work.FDCT`
290			`port map`
291			`(`
292			`CLK => CLK,`
293			`RST => RST,`
294			`-- CTRL`
295			`start_pb => fdct_start,`
296			`ready_pb => fdct_ready,`
297			`fdct_sm_settings => fdct_sm_settings,`
298
299			`-- BUF_FIFO`
300			`bf_block_cnt => fdct_block_cnt,`
301			`bf_fifo_rd => fdct_fifo_rd,`
302			`bf_fifo_empty => fdct_fifo_empty,`
303			`bf_fifo_q => fdct_fifo_q,`
304			`bf_fifo_hf_full => fdct_fifo_hf_full,`
305
306			`-- ZIG ZAG`
307			`zz_buf_sel => zz_buf_sel,`
308			`zz_rd_addr => zz_rd_addr,`
309			`zz_data => zz_data,`
310			`zz_rden => zz_rden,`
311
312			`-- HOST`
313			`img_size_x => img_size_x,`
314			`img_size_y => img_size_y,`
315			`sof => sof`
316			`);`
317
318			`-------------------------------------------------------------------`
319			`-- ZigZag top level`
320			`-------------------------------------------------------------------`
321			`U_ZZ_TOP : entity work.ZZ_TOP`
322			`port map`
323			`(`
324			`CLK => CLK,`
325			`RST => RST,`
326			`-- CTRL`
327			`start_pb => zig_start,`
328			`ready_pb => zig_ready,`
329	32	mikel262	`zig_sm_settings => zig_sm_settings,`
330	25	mikel262
331	34	mikel262	`-- Quantizer`
332			`qua_buf_sel => qua_buf_sel,`
333			`qua_rdaddr => qua_rdaddr,`
334			`qua_data => qua_data,`
335	25	mikel262
336			`-- FDCT`
337			`fdct_buf_sel => zz_buf_sel,`
338			`fdct_rd_addr => zz_rd_addr,`
339			`fdct_data => zz_data,`
340	34	mikel262	`fdct_rden => zz_rden`
341			`);`
342
343			`-------------------------------------------------------------------`
344			`-- Quantizer top level`
345			`-------------------------------------------------------------------`
346			`U_QUANT_TOP : entity work.QUANT_TOP`
347			`port map`
348			`(`
349			`CLK => CLK,`
350			`RST => RST,`
351			`-- CTRL`
352			`start_pb => qua_start,`
353			`ready_pb => qua_ready,`
354			`qua_sm_settings => qua_sm_settings,`
355	25	mikel262
356	34	mikel262	`-- RLE`
357			`rle_buf_sel => rle_buf_sel,`
358			`rle_rdaddr => rle_rdaddr,`
359			`rle_data => rle_data,`
360
361			`-- ZIGZAG`
362			`zig_buf_sel => qua_buf_sel,`
363			`zig_rd_addr => qua_rdaddr,`
364			`zig_data => qua_data,`
365
366	25	mikel262	`-- HOST`
367			`qdata => qdata,`
368			`qaddr => qaddr,`
369			`qwren => qwren`
370	34	mikel262	`);`
371
372	25	mikel262	`-------------------------------------------------------------------`
373			`-- RLE TOP`
374			`-------------------------------------------------------------------`
375			`U_RLE_TOP : entity work.RLE_TOP`
376			`port map`
377			`(`
378			`CLK => CLK,`
379			`RST => RST,`
380			`-- CTRL`
381			`start_pb => rle_start,`
382			`ready_pb => rle_ready,`
383			`rle_sm_settings => rle_sm_settings,`
384
385			`-- HUFFMAN`
386			`huf_buf_sel => huf_buf_sel,`
387			`huf_rden => huf_rden,`
388			`huf_runlength => huf_runlength,`
389			`huf_size => huf_size,`
390			`huf_amplitude => huf_amplitude,`
391			`huf_dval => huf_dval,`
392			`huf_fifo_empty => huf_fifo_empty,`
393
394	34	mikel262	`-- Quantizer`
395			`qua_buf_sel => rle_buf_sel,`
396			`qua_rd_addr => rle_rdaddr,`
397			`qua_data => rle_data,`
398	25	mikel262
399			`-- HostIF`
400			`sof => sof`
401			`);`
402
403			`-------------------------------------------------------------------`
404			`-- Huffman Encoder`
405			`-------------------------------------------------------------------`
406			`U_Huffman : entity work.Huffman`
407			`port map`
408			`(`
409			`CLK => CLK,`
410			`RST => RST,`
411			`-- CTRL`
412			`start_pb => huf_start,`
413			`ready_pb => huf_ready,`
414	36	mikel262	`huf_sm_settings => huf_sm_settings,`
415	25	mikel262
416			`-- HOST IF`
417			`sof => sof,`
418			`img_size_x => img_size_x,`
419			`img_size_y => img_size_y,`
420			`cmp_max => cmp_max,`
421
422			`-- RLE`
423			`rle_buf_sel => huf_buf_sel,`
424			`rd_en => huf_rden,`
425			`runlength => huf_runlength,`
426			`VLI_size => huf_size,`
427			`VLI => huf_amplitude,`
428			`d_val => huf_dval,`
429			`rle_fifo_empty => huf_fifo_empty,`
430
431			`-- Byte Stuffer`
432			`bs_buf_sel => bs_buf_sel,`
433			`bs_fifo_empty => bs_fifo_empty,`
434			`bs_rd_req => bs_rd_req,`
435			`bs_packed_byte => bs_packed_byte`
436			`);`
437
438
439			`-------------------------------------------------------------------`
440			`-- Byte Stuffer`
441			`-------------------------------------------------------------------`
442			`U_ByteStuffer : entity work.ByteStuffer`
443			`port map`
444			`(`
445			`CLK => CLK,`
446			`RST => RST,`
447			`-- CTRL`
448			`start_pb => bs_start,`
449			`ready_pb => bs_ready,`
450
451			`-- HOST IF`
452			`sof => sof,`
453			`num_enc_bytes => num_enc_bytes,`
454			`outram_base_addr => outram_base_addr,`
455
456			`-- Huffman`
457			`huf_buf_sel => bs_buf_sel,`
458			`huf_fifo_empty => bs_fifo_empty,`
459			`huf_rd_req => bs_rd_req,`
460			`huf_packed_byte => bs_packed_byte,`
461
462			`-- OUT RAM`
463			`ram_byte => bs_ram_byte,`
464			`ram_wren => bs_ram_wren,`
465			`ram_wraddr => bs_ram_wraddr`
466			`);`
467
468			`-------------------------------------------------------------------`
469			`-- JFIF Generator`
470			`-------------------------------------------------------------------`
471			`U_JFIFGen : entity work.JFIFGen`
472			`port map`
473			`(`
474			`CLK => CLK,`
475			`RST => RST,`
476			`-- CTRL`
477			`start => jfif_start,`
478			`ready => jfif_ready,`
479			`eoi => jfif_eoi,`
480
481			`-- ByteStuffer`
482			`num_enc_bytes => num_enc_bytes,`
483
484			`-- HOST IF`
485			`qwren => qwren,`
486			`qwaddr => qaddr,`
487			`qwdata => qdata,`
488			`image_size_reg => image_size_reg,`
489			`image_size_reg_wr => img_size_wr,`
490
491			`-- OUT RAM`
492			`ram_byte => jfif_ram_byte,`
493			`ram_wren => jfif_ram_wren,`
494			`ram_wraddr => jfif_ram_wraddr`
495			`);`
496
497			`image_size_reg <= img_size_x & img_size_y;`
498
499			`-------------------------------------------------------------------`
500			`-- OutMux`

Browse

Tools

Subversion Repositories mkjpeg

[/] [mkjpeg/] [trunk/] [design/] [top/] [JpegEnc.vhd] - Blame information for rev 46