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-------------------------------------------------------------------------------
-- File Name : JpegEnc.vhd
--
-- Project   : JPEG_ENC
--
-- Module    : JpegEnc
--
-- Content   : JPEG Encoder Top Level
--
-- Description : 
--
-- Spec.     : 
--
-- Author    : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all;
 
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
library work;
  use work.JPEG_PKG.all;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity JpegEnc is
  port
  (
        CLK                : in  std_logic;
        RST                : in  std_logic;
 
        -- OPB
        OPB_ABus           : in  std_logic_vector(31 downto 0);
        OPB_BE             : in  std_logic_vector(3 downto 0);
        OPB_DBus_in        : in  std_logic_vector(31 downto 0);
        OPB_RNW            : in  std_logic;
        OPB_select         : in  std_logic;
        OPB_DBus_out       : out std_logic_vector(31 downto 0);
        OPB_XferAck        : out std_logic;
        OPB_retry          : out std_logic;
        OPB_toutSup        : out std_logic;
        OPB_errAck         : out std_logic;
 
        -- IMAGE RAM
        iram_wdata         : in  std_logic_vector(C_PIXEL_BITS-1 downto 0);
        iram_wren          : in  std_logic;
        iram_fifo_afull    : out std_logic;
 
        -- OUT RAM
        ram_byte           : out std_logic_vector(7 downto 0);
        ram_wren           : out std_logic;
        ram_wraddr         : out std_logic_vector(23 downto 0);
        outif_almost_full  : in  std_logic
   );
end entity JpegEnc;
 
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of JpegEnc is
 
  signal qdata              : std_logic_vector(7 downto 0);
  signal qaddr              : std_logic_vector(6 downto 0);
  signal qwren              : std_logic;
  signal jpeg_ready         : std_logic;
  signal jpeg_busy          : std_logic;
  signal outram_base_addr   : std_logic_vector(9 downto 0);
  signal num_enc_bytes      : std_logic_vector(23 downto 0);
  signal img_size_x         : std_logic_vector(15 downto 0);
  signal img_size_y         : std_logic_vector(15 downto 0);
  signal sof                : std_logic;
  signal jpg_iram_rden      : std_logic;
  signal jpg_iram_rdaddr    : std_logic_vector(31 downto 0);
  signal jpg_iram_rdata     : std_logic_vector(23 downto 0);
  signal fdct_start         : std_logic;
  signal fdct_ready         : std_logic;
  signal zig_start          : std_logic;
  signal zig_ready          : std_logic;
  signal qua_start          : std_logic;
  signal qua_ready          : std_logic;
  signal rle_start          : std_logic;
  signal rle_ready          : std_logic;
  signal huf_start          : std_logic;
  signal huf_ready          : std_logic;
  signal bs_start           : std_logic;
  signal bs_ready           : std_logic;
  signal zz_buf_sel         : std_logic;
  signal zz_rd_addr         : std_logic_vector(5 downto 0);
  signal zz_data            : std_logic_vector(11 downto 0);
  signal rle_buf_sel        : std_logic;
  signal rle_rdaddr         : std_logic_vector(5 downto 0);
  signal rle_data           : std_logic_vector(11 downto 0);
  signal qua_buf_sel        : std_logic;
  signal qua_rdaddr         : std_logic_vector(5 downto 0);
  signal qua_data           : std_logic_vector(11 downto 0);
  signal huf_buf_sel        : std_logic;
  signal huf_rdaddr         : std_logic_vector(5 downto 0);
  signal huf_rden           : std_logic;
  signal huf_runlength      : std_logic_vector(3 downto 0);
  signal huf_size           : std_logic_vector(3 downto 0);
  signal huf_amplitude      : std_logic_vector(11 downto 0);
  signal huf_dval           : std_logic;
  signal bs_buf_sel         : std_logic;
  signal bs_fifo_empty      : std_logic;
  signal bs_rd_req          : std_logic;
  signal bs_packed_byte     : std_logic_vector(7 downto 0);
  signal huf_fifo_empty     : std_logic;
  signal zz_rden            : std_logic;
  signal fdct_sm_settings   : T_SM_SETTINGS;
  signal zig_sm_settings    : T_SM_SETTINGS;
  signal qua_sm_settings    : T_SM_SETTINGS;
  signal rle_sm_settings    : T_SM_SETTINGS;
  signal huf_sm_settings    : T_SM_SETTINGS;
  signal bs_sm_settings     : T_SM_SETTINGS;
  signal cmp_max            : std_logic_vector(1 downto 0);
  signal image_size_reg     : std_logic_vector(31 downto 0);
  signal jfif_ram_byte      : std_logic_vector(7 downto 0);
  signal jfif_ram_wren      : std_logic;
  signal jfif_ram_wraddr    : std_logic_vector(23 downto 0);
  signal out_mux_ctrl       : std_logic;
  signal img_size_wr        : std_logic;
  signal jfif_start         : std_logic;
  signal jfif_ready         : std_logic;
  signal bs_ram_byte        : std_logic_vector(7 downto 0);
  signal bs_ram_wren        : std_logic;
  signal bs_ram_wraddr      : std_logic_vector(23 downto 0);
  signal jfif_eoi           : std_logic;
  signal fdct_fifo_rd       : std_logic;
  signal fdct_fifo_q        : std_logic_vector(23 downto 0);
  signal fdct_fifo_hf_full  : std_logic;
 
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
 
  -------------------------------------------------------------------
  -- Host Interface
  -------------------------------------------------------------------
  U_HostIF : entity work.HostIF
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- OPB
        OPB_ABus           => OPB_ABus,
        OPB_BE             => OPB_BE,
        OPB_DBus_in        => OPB_DBus_in,
        OPB_RNW            => OPB_RNW,
        OPB_select         => OPB_select,
        OPB_DBus_out       => OPB_DBus_out,
        OPB_XferAck        => OPB_XferAck,
        OPB_retry          => OPB_retry,
        OPB_toutSup        => OPB_toutSup,
        OPB_errAck         => OPB_errAck,
 
        -- Quantizer RAM
        qdata              => qdata,
        qaddr              => qaddr,
        qwren              => qwren,
 
        -- CTRL
        jpeg_ready         => jpeg_ready,
        jpeg_busy          => jpeg_busy,
 
        -- ByteStuffer
        outram_base_addr   => outram_base_addr,
        num_enc_bytes      => num_enc_bytes,
 
        -- global
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        img_size_wr        => img_size_wr,
        sof                => sof,
        cmp_max            => cmp_max
    );
 
  -------------------------------------------------------------------
  -- BUF_FIFO
  -------------------------------------------------------------------
  U_BUF_FIFO : entity work.BUF_FIFO
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- HOST PROG
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        sof                => sof,
 
        -- HOST DATA
        iram_wren          => iram_wren,
        iram_wdata         => iram_wdata,
        fifo_almost_full   => iram_fifo_afull,
 
        -- FDCT
        fdct_fifo_rd       => fdct_fifo_rd,
        fdct_fifo_q        => fdct_fifo_q,
        fdct_fifo_hf_full  => fdct_fifo_hf_full
    );
 
  -------------------------------------------------------------------
  -- Controller
  -------------------------------------------------------------------
  U_CtrlSM : entity work.CtrlSM
  port map
  (
        CLK                => CLK,
        RST                => RST,
 
        -- output IF
        outif_almost_full  => outif_almost_full,
 
        -- HOST IF
        sof                => sof,
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        jpeg_ready         => jpeg_ready,
        jpeg_busy          => jpeg_busy,
        cmp_max            => cmp_max,
 
        -- FDCT
        fdct_start         => fdct_start,
        fdct_ready         => fdct_ready,
        fdct_sm_settings   => fdct_sm_settings,
 
        -- ZIGZAG
        zig_start          => zig_start,
        zig_ready          => zig_ready,
        zig_sm_settings    => zig_sm_settings,
 
        -- Quantizer
        qua_start          => qua_start,
        qua_ready          => qua_ready,
        qua_sm_settings    => qua_sm_settings,
 
        -- RLE
        rle_start          => rle_start,
        rle_ready          => rle_ready,
        rle_sm_settings    => rle_sm_settings,
 
        -- Huffman
        huf_start          => huf_start,
        huf_ready          => huf_ready,
        huf_sm_settings    => huf_sm_settings,
 
        -- ByteStuffdr
        bs_start           => bs_start,
        bs_ready           => bs_ready,
        bs_sm_settings     => bs_sm_settings,
 
        -- JFIF GEN
        jfif_start         => jfif_start,
        jfif_ready         => jfif_ready,
        jfif_eoi           => jfif_eoi,
 
        -- OUT MUX         
        out_mux_ctrl       => out_mux_ctrl
    );
 
  -------------------------------------------------------------------
  -- FDCT
  -------------------------------------------------------------------
  U_FDCT : entity work.FDCT
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => fdct_start,
        ready_pb           => fdct_ready,
        fdct_sm_settings   => fdct_sm_settings,
 
        -- BUF_FIFO
        bf_fifo_rd         => fdct_fifo_rd,
        bf_fifo_q          => fdct_fifo_q,
        bf_fifo_hf_full    => fdct_fifo_hf_full,
 
        -- ZIG ZAG
        zz_buf_sel         => zz_buf_sel,
        zz_rd_addr         => zz_rd_addr,
        zz_data            => zz_data,
        zz_rden            => zz_rden,
 
        -- HOST
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        sof                => sof
    );
 
  -------------------------------------------------------------------
  -- ZigZag top level
  -------------------------------------------------------------------
  U_ZZ_TOP : entity work.ZZ_TOP
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => zig_start,
        ready_pb           => zig_ready,
        zig_sm_settings    => zig_sm_settings,
 
        -- Quantizer
        qua_buf_sel        => qua_buf_sel,
        qua_rdaddr         => qua_rdaddr,
        qua_data           => qua_data,
 
        -- FDCT
        fdct_buf_sel       => zz_buf_sel,
        fdct_rd_addr       => zz_rd_addr,
        fdct_data          => zz_data,
        fdct_rden          => zz_rden
    );
 
  -------------------------------------------------------------------
  -- Quantizer top level
  -------------------------------------------------------------------
  U_QUANT_TOP : entity work.QUANT_TOP
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => qua_start,
        ready_pb           => qua_ready,
        qua_sm_settings    => qua_sm_settings,
 
        -- RLE
        rle_buf_sel        => rle_buf_sel,
        rle_rdaddr         => rle_rdaddr,
        rle_data           => rle_data,
 
        -- ZIGZAG
        zig_buf_sel        => qua_buf_sel,
        zig_rd_addr        => qua_rdaddr,
        zig_data           => qua_data,
 
        -- HOST
        qdata              => qdata,
        qaddr              => qaddr,
        qwren              => qwren
    );
 
  -------------------------------------------------------------------
  -- RLE TOP
  -------------------------------------------------------------------
  U_RLE_TOP : entity work.RLE_TOP
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => rle_start,
        ready_pb           => rle_ready,
        rle_sm_settings    => rle_sm_settings,
 
        -- HUFFMAN
        huf_buf_sel        => huf_buf_sel,
        huf_rden           => huf_rden,
        huf_runlength      => huf_runlength,
        huf_size           => huf_size,
        huf_amplitude      => huf_amplitude,
        huf_dval           => huf_dval,
        huf_fifo_empty     => huf_fifo_empty,
 
        -- Quantizer
        qua_buf_sel        => rle_buf_sel,
        qua_rd_addr        => rle_rdaddr,
        qua_data           => rle_data,
 
        -- HostIF
        sof                => sof
    );
 
  -------------------------------------------------------------------
  -- Huffman Encoder
  -------------------------------------------------------------------
  U_Huffman : entity work.Huffman
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => huf_start,
        ready_pb           => huf_ready,
        huf_sm_settings    => huf_sm_settings,
 
        -- HOST IF
        sof                => sof,
        img_size_x         => img_size_x,
        img_size_y         => img_size_y,
        cmp_max            => cmp_max,
 
        -- RLE
        rle_buf_sel        => huf_buf_sel,
        rd_en              => huf_rden,
        runlength          => huf_runlength,
        VLI_size           => huf_size,
        VLI                => huf_amplitude,
        d_val              => huf_dval,
        rle_fifo_empty     => huf_fifo_empty,
 
        -- Byte Stuffer
        bs_buf_sel         => bs_buf_sel,
        bs_fifo_empty      => bs_fifo_empty,
        bs_rd_req          => bs_rd_req,
        bs_packed_byte     => bs_packed_byte
    );
 
 
  -------------------------------------------------------------------
  -- Byte Stuffer
  -------------------------------------------------------------------
  U_ByteStuffer : entity work.ByteStuffer
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start_pb           => bs_start,
        ready_pb           => bs_ready,
 
        -- HOST IF
        sof                => sof,
        num_enc_bytes      => num_enc_bytes,
        outram_base_addr   => outram_base_addr,
 
        -- Huffman
        huf_buf_sel        => bs_buf_sel,
        huf_fifo_empty     => bs_fifo_empty,
        huf_rd_req         => bs_rd_req,
        huf_packed_byte    => bs_packed_byte,
 
        -- OUT RAM
        ram_byte           => bs_ram_byte,
        ram_wren           => bs_ram_wren,
        ram_wraddr         => bs_ram_wraddr
    );
 
  -------------------------------------------------------------------
  -- JFIF Generator
  -------------------------------------------------------------------
  U_JFIFGen : entity work.JFIFGen
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        start              => jfif_start,
        ready              => jfif_ready,
        eoi                => jfif_eoi,
 
        -- ByteStuffer
        num_enc_bytes         => num_enc_bytes,
 
        -- HOST IF
        qwren              => qwren,
        qwaddr             => qaddr,
        qwdata             => qdata,
        image_size_reg     => image_size_reg,
        image_size_reg_wr  => img_size_wr,
 
        -- OUT RAM
        ram_byte           => jfif_ram_byte,
        ram_wren           => jfif_ram_wren,
        ram_wraddr         => jfif_ram_wraddr
    );
 
  image_size_reg <= img_size_x & img_size_y;
 
  -------------------------------------------------------------------
  -- OutMux
  -------------------------------------------------------------------
  U_OutMux : entity work.OutMux
  port map
  (
        CLK                => CLK,
        RST                => RST,
        -- CTRL
        out_mux_ctrl       => out_mux_ctrl,
 
        -- ByteStuffer
        bs_ram_byte        => bs_ram_byte,
        bs_ram_wren        => bs_ram_wren,
        bs_ram_wraddr      => bs_ram_wraddr,
        -- ByteStuffer
        jfif_ram_byte      => jfif_ram_byte,
        jfif_ram_wren      => jfif_ram_wren,
        jfif_ram_wraddr    => jfif_ram_wraddr,
 
        -- OUT RAM
        ram_byte           => ram_byte,
        ram_wren           => ram_wren,
        ram_wraddr         => ram_wraddr
    );
 
 
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
-------------------------------------------------------------------------------

Line No.	Rev	Author	Line
1	25	mikel262	`-------------------------------------------------------------------------------`
2			`-- File Name : JpegEnc.vhd`
3			`--`
4			`-- Project : JPEG_ENC`
5			`--`
6			`-- Module : JpegEnc`
7			`--`
8			`-- Content : JPEG Encoder Top Level`
9			`--`
10			`-- Description :`
11			`--`
12			`-- Spec. :`
13			`--`
14			`-- Author : Michal Krepa`
15			`--`
16			`-------------------------------------------------------------------------------`
17			`-- History :`
18			`-- 20090301: (MK): Initial Creation.`
19			`-------------------------------------------------------------------------------`
20
21			`-------------------------------------------------------------------------------`
22			`-------------------------------------------------------------------------------`
23			`----------------------------------- LIBRARY/PACKAGE ---------------------------`
24			`-------------------------------------------------------------------------------`
25			`-------------------------------------------------------------------------------`
26
27			`-------------------------------------------------------------------------------`
28			`-- generic packages/libraries:`
29			`-------------------------------------------------------------------------------`
30			`library ieee;`
31			`use ieee.std_logic_1164.all;`
32			`use ieee.numeric_std.all;`
33
34			`-------------------------------------------------------------------------------`
35			`-- user packages/libraries:`
36			`-------------------------------------------------------------------------------`
37			`library work;`
38			`use work.JPEG_PKG.all;`
39			`-------------------------------------------------------------------------------`
40			`-------------------------------------------------------------------------------`
41			`----------------------------------- ENTITY ------------------------------------`
42			`-------------------------------------------------------------------------------`
43			`-------------------------------------------------------------------------------`
44			`entity JpegEnc is`
45			`port`
46			`(`
47			`CLK : in std_logic;`
48			`RST : in std_logic;`
49
50			`-- OPB`
51			`OPB_ABus : in std_logic_vector(31 downto 0);`
52			`OPB_BE : in std_logic_vector(3 downto 0);`
53			`OPB_DBus_in : in std_logic_vector(31 downto 0);`
54			`OPB_RNW : in std_logic;`
55			`OPB_select : in std_logic;`
56			`OPB_DBus_out : out std_logic_vector(31 downto 0);`
57			`OPB_XferAck : out std_logic;`
58			`OPB_retry : out std_logic;`
59			`OPB_toutSup : out std_logic;`
60			`OPB_errAck : out std_logic;`
61
62			`-- IMAGE RAM`
63	49	mikel262	`iram_wdata : in std_logic_vector(C_PIXEL_BITS-1 downto 0);`
64	25	mikel262	`iram_wren : in std_logic;`
65			`iram_fifo_afull : out std_logic;`
66
67			`-- OUT RAM`
68			`ram_byte : out std_logic_vector(7 downto 0);`
69			`ram_wren : out std_logic;`
70	42	mikel262	`ram_wraddr : out std_logic_vector(23 downto 0);`
71			`outif_almost_full : in std_logic`
72	46	mikel262	`);`
73	25	mikel262	`end entity JpegEnc;`
74
75	43	mikel262
76	25	mikel262	`-------------------------------------------------------------------------------`
77			`-------------------------------------------------------------------------------`
78			`----------------------------------- ARCHITECTURE ------------------------------`
79			`-------------------------------------------------------------------------------`
80			`-------------------------------------------------------------------------------`
81			`architecture RTL of JpegEnc is`
82
83			`signal qdata : std_logic_vector(7 downto 0);`
84	32	mikel262	`signal qaddr : std_logic_vector(6 downto 0);`
85	25	mikel262	`signal qwren : std_logic;`
86			`signal jpeg_ready : std_logic;`
87			`signal jpeg_busy : std_logic;`
88			`signal outram_base_addr : std_logic_vector(9 downto 0);`
89			`signal num_enc_bytes : std_logic_vector(23 downto 0);`
90			`signal img_size_x : std_logic_vector(15 downto 0);`
91			`signal img_size_y : std_logic_vector(15 downto 0);`
92			`signal sof : std_logic;`
93			`signal jpg_iram_rden : std_logic;`
94			`signal jpg_iram_rdaddr : std_logic_vector(31 downto 0);`
95			`signal jpg_iram_rdata : std_logic_vector(23 downto 0);`
96			`signal fdct_start : std_logic;`
97			`signal fdct_ready : std_logic;`
98			`signal zig_start : std_logic;`
99			`signal zig_ready : std_logic;`
100	34	mikel262	`signal qua_start : std_logic;`
101			`signal qua_ready : std_logic;`
102	25	mikel262	`signal rle_start : std_logic;`
103			`signal rle_ready : std_logic;`
104			`signal huf_start : std_logic;`
105			`signal huf_ready : std_logic;`
106			`signal bs_start : std_logic;`
107			`signal bs_ready : std_logic;`
108			`signal zz_buf_sel : std_logic;`
109			`signal zz_rd_addr : std_logic_vector(5 downto 0);`
110			`signal zz_data : std_logic_vector(11 downto 0);`
111			`signal rle_buf_sel : std_logic;`
112			`signal rle_rdaddr : std_logic_vector(5 downto 0);`
113			`signal rle_data : std_logic_vector(11 downto 0);`
114	34	mikel262	`signal qua_buf_sel : std_logic;`
115			`signal qua_rdaddr : std_logic_vector(5 downto 0);`
116			`signal qua_data : std_logic_vector(11 downto 0);`
117	25	mikel262	`signal huf_buf_sel : std_logic;`
118			`signal huf_rdaddr : std_logic_vector(5 downto 0);`
119			`signal huf_rden : std_logic;`
120			`signal huf_runlength : std_logic_vector(3 downto 0);`
121			`signal huf_size : std_logic_vector(3 downto 0);`
122			`signal huf_amplitude : std_logic_vector(11 downto 0);`
123			`signal huf_dval : std_logic;`
124			`signal bs_buf_sel : std_logic;`
125			`signal bs_fifo_empty : std_logic;`
126			`signal bs_rd_req : std_logic;`
127			`signal bs_packed_byte : std_logic_vector(7 downto 0);`
128			`signal huf_fifo_empty : std_logic;`
129			`signal zz_rden : std_logic;`
130			`signal fdct_sm_settings : T_SM_SETTINGS;`
131			`signal zig_sm_settings : T_SM_SETTINGS;`
132	34	mikel262	`signal qua_sm_settings : T_SM_SETTINGS;`
133	25	mikel262	`signal rle_sm_settings : T_SM_SETTINGS;`
134			`signal huf_sm_settings : T_SM_SETTINGS;`
135			`signal bs_sm_settings : T_SM_SETTINGS;`
136			`signal cmp_max : std_logic_vector(1 downto 0);`
137			`signal image_size_reg : std_logic_vector(31 downto 0);`
138			`signal jfif_ram_byte : std_logic_vector(7 downto 0);`
139			`signal jfif_ram_wren : std_logic;`
140			`signal jfif_ram_wraddr : std_logic_vector(23 downto 0);`
141			`signal out_mux_ctrl : std_logic;`
142			`signal img_size_wr : std_logic;`
143			`signal jfif_start : std_logic;`
144			`signal jfif_ready : std_logic;`
145			`signal bs_ram_byte : std_logic_vector(7 downto 0);`
146			`signal bs_ram_wren : std_logic;`
147			`signal bs_ram_wraddr : std_logic_vector(23 downto 0);`
148			`signal jfif_eoi : std_logic;`
149			`signal fdct_fifo_rd : std_logic;`
150			`signal fdct_fifo_q : std_logic_vector(23 downto 0);`
151			`signal fdct_fifo_hf_full : std_logic;`
152
153			`-------------------------------------------------------------------------------`
154			`-- Architecture: begin`
155			`-------------------------------------------------------------------------------`
156			`begin`
157
158			`-------------------------------------------------------------------`
159			`-- Host Interface`
160			`-------------------------------------------------------------------`
161			`U_HostIF : entity work.HostIF`
162			`port map`
163			`(`
164			`CLK => CLK,`
165			`RST => RST,`
166			`-- OPB`
167			`OPB_ABus => OPB_ABus,`
168			`OPB_BE => OPB_BE,`
169			`OPB_DBus_in => OPB_DBus_in,`
170			`OPB_RNW => OPB_RNW,`
171			`OPB_select => OPB_select,`
172			`OPB_DBus_out => OPB_DBus_out,`
173			`OPB_XferAck => OPB_XferAck,`
174			`OPB_retry => OPB_retry,`
175			`OPB_toutSup => OPB_toutSup,`
176			`OPB_errAck => OPB_errAck,`
177
178			`-- Quantizer RAM`
179			`qdata => qdata,`
180			`qaddr => qaddr,`
181			`qwren => qwren,`
182
183			`-- CTRL`
184			`jpeg_ready => jpeg_ready,`
185			`jpeg_busy => jpeg_busy,`
186
187			`-- ByteStuffer`
188			`outram_base_addr => outram_base_addr,`
189			`num_enc_bytes => num_enc_bytes,`
190
191			`-- global`
192			`img_size_x => img_size_x,`
193			`img_size_y => img_size_y,`
194			`img_size_wr => img_size_wr,`
195			`sof => sof,`
196			`cmp_max => cmp_max`
197			`);`
198
199			`-------------------------------------------------------------------`
200			`-- BUF_FIFO`
201			`-------------------------------------------------------------------`
202			`U_BUF_FIFO : entity work.BUF_FIFO`
203			`port map`
204			`(`
205			`CLK => CLK,`
206			`RST => RST,`
207			`-- HOST PROG`
208			`img_size_x => img_size_x,`
209			`img_size_y => img_size_y,`
210			`sof => sof,`
211
212			`-- HOST DATA`
213			`iram_wren => iram_wren,`
214			`iram_wdata => iram_wdata,`
215			`fifo_almost_full => iram_fifo_afull,`
216
217			`-- FDCT`
218			`fdct_fifo_rd => fdct_fifo_rd,`
219			`fdct_fifo_q => fdct_fifo_q,`
220			`fdct_fifo_hf_full => fdct_fifo_hf_full`
221			`);`
222
223			`-------------------------------------------------------------------`
224			`-- Controller`
225			`-------------------------------------------------------------------`
226			`U_CtrlSM : entity work.CtrlSM`
227			`port map`
228			`(`
229			`CLK => CLK,`
230			`RST => RST,`
231	42	mikel262
232			`-- output IF`
233			`outif_almost_full => outif_almost_full,`
234	25	mikel262
235			`-- HOST IF`
236			`sof => sof,`
237			`img_size_x => img_size_x,`
238			`img_size_y => img_size_y,`
239			`jpeg_ready => jpeg_ready,`
240			`jpeg_busy => jpeg_busy,`
241			`cmp_max => cmp_max,`
242
243			`-- FDCT`
244			`fdct_start => fdct_start,`
245			`fdct_ready => fdct_ready,`
246			`fdct_sm_settings => fdct_sm_settings,`
247
248			`-- ZIGZAG`
249			`zig_start => zig_start,`
250			`zig_ready => zig_ready,`
251			`zig_sm_settings => zig_sm_settings,`
252	34	mikel262
253			`-- Quantizer`
254			`qua_start => qua_start,`
255			`qua_ready => qua_ready,`
256			`qua_sm_settings => qua_sm_settings,`
257	25	mikel262
258			`-- RLE`
259			`rle_start => rle_start,`
260			`rle_ready => rle_ready,`
261			`rle_sm_settings => rle_sm_settings,`
262
263			`-- Huffman`
264			`huf_start => huf_start,`
265			`huf_ready => huf_ready,`
266			`huf_sm_settings => huf_sm_settings,`
267
268			`-- ByteStuffdr`
269			`bs_start => bs_start,`
270			`bs_ready => bs_ready,`
271			`bs_sm_settings => bs_sm_settings,`
272
273			`-- JFIF GEN`
274			`jfif_start => jfif_start,`
275			`jfif_ready => jfif_ready,`
276			`jfif_eoi => jfif_eoi,`
277
278			`-- OUT MUX`
279			`out_mux_ctrl => out_mux_ctrl`
280			`);`
281
282			`-------------------------------------------------------------------`
283			`-- FDCT`
284			`-------------------------------------------------------------------`
285			`U_FDCT : entity work.FDCT`
286			`port map`
287			`(`
288			`CLK => CLK,`
289			`RST => RST,`
290			`-- CTRL`
291			`start_pb => fdct_start,`
292			`ready_pb => fdct_ready,`
293			`fdct_sm_settings => fdct_sm_settings,`
294
295			`-- BUF_FIFO`
296			`bf_fifo_rd => fdct_fifo_rd,`
297			`bf_fifo_q => fdct_fifo_q,`
298			`bf_fifo_hf_full => fdct_fifo_hf_full,`
299
300			`-- ZIG ZAG`
301			`zz_buf_sel => zz_buf_sel,`
302			`zz_rd_addr => zz_rd_addr,`
303			`zz_data => zz_data,`
304			`zz_rden => zz_rden,`
305
306			`-- HOST`
307			`img_size_x => img_size_x,`
308			`img_size_y => img_size_y,`
309			`sof => sof`
310			`);`
311
312			`-------------------------------------------------------------------`
313			`-- ZigZag top level`
314			`-------------------------------------------------------------------`
315			`U_ZZ_TOP : entity work.ZZ_TOP`
316			`port map`
317			`(`
318			`CLK => CLK,`
319			`RST => RST,`
320			`-- CTRL`
321			`start_pb => zig_start,`
322			`ready_pb => zig_ready,`
323	32	mikel262	`zig_sm_settings => zig_sm_settings,`
324	25	mikel262
325	34	mikel262	`-- Quantizer`
326			`qua_buf_sel => qua_buf_sel,`
327			`qua_rdaddr => qua_rdaddr,`
328			`qua_data => qua_data,`
329	25	mikel262
330			`-- FDCT`
331			`fdct_buf_sel => zz_buf_sel,`
332			`fdct_rd_addr => zz_rd_addr,`
333			`fdct_data => zz_data,`
334	34	mikel262	`fdct_rden => zz_rden`
335			`);`
336
337			`-------------------------------------------------------------------`
338			`-- Quantizer top level`
339			`-------------------------------------------------------------------`
340			`U_QUANT_TOP : entity work.QUANT_TOP`
341			`port map`
342			`(`
343			`CLK => CLK,`
344			`RST => RST,`
345			`-- CTRL`
346			`start_pb => qua_start,`
347			`ready_pb => qua_ready,`
348			`qua_sm_settings => qua_sm_settings,`
349	25	mikel262
350	34	mikel262	`-- RLE`
351			`rle_buf_sel => rle_buf_sel,`
352			`rle_rdaddr => rle_rdaddr,`
353			`rle_data => rle_data,`
354
355			`-- ZIGZAG`
356			`zig_buf_sel => qua_buf_sel,`
357			`zig_rd_addr => qua_rdaddr,`
358			`zig_data => qua_data,`
359
360	25	mikel262	`-- HOST`
361			`qdata => qdata,`
362			`qaddr => qaddr,`
363			`qwren => qwren`
364	34	mikel262	`);`
365
366	25	mikel262	`-------------------------------------------------------------------`
367			`-- RLE TOP`
368			`-------------------------------------------------------------------`
369			`U_RLE_TOP : entity work.RLE_TOP`
370			`port map`
371			`(`
372			`CLK => CLK,`
373			`RST => RST,`
374			`-- CTRL`
375			`start_pb => rle_start,`
376			`ready_pb => rle_ready,`
377			`rle_sm_settings => rle_sm_settings,`
378
379			`-- HUFFMAN`
380			`huf_buf_sel => huf_buf_sel,`
381			`huf_rden => huf_rden,`
382			`huf_runlength => huf_runlength,`
383			`huf_size => huf_size,`
384			`huf_amplitude => huf_amplitude,`
385			`huf_dval => huf_dval,`
386			`huf_fifo_empty => huf_fifo_empty,`
387
388	34	mikel262	`-- Quantizer`
389			`qua_buf_sel => rle_buf_sel,`
390			`qua_rd_addr => rle_rdaddr,`
391			`qua_data => rle_data,`
392	25	mikel262
393			`-- HostIF`
394			`sof => sof`
395			`);`
396
397			`-------------------------------------------------------------------`
398			`-- Huffman Encoder`
399			`-------------------------------------------------------------------`
400			`U_Huffman : entity work.Huffman`
401			`port map`
402			`(`
403			`CLK => CLK,`
404			`RST => RST,`
405			`-- CTRL`
406			`start_pb => huf_start,`
407			`ready_pb => huf_ready,`
408	36	mikel262	`huf_sm_settings => huf_sm_settings,`
409	25	mikel262
410			`-- HOST IF`
411			`sof => sof,`
412			`img_size_x => img_size_x,`
413			`img_size_y => img_size_y,`
414			`cmp_max => cmp_max,`
415
416			`-- RLE`
417			`rle_buf_sel => huf_buf_sel,`
418			`rd_en => huf_rden,`
419			`runlength => huf_runlength,`
420			`VLI_size => huf_size,`
421			`VLI => huf_amplitude,`
422			`d_val => huf_dval,`
423			`rle_fifo_empty => huf_fifo_empty,`
424
425			`-- Byte Stuffer`
426			`bs_buf_sel => bs_buf_sel,`
427			`bs_fifo_empty => bs_fifo_empty,`
428			`bs_rd_req => bs_rd_req,`
429			`bs_packed_byte => bs_packed_byte`
430			`);`
431
432
433			`-------------------------------------------------------------------`
434			`-- Byte Stuffer`
435			`-------------------------------------------------------------------`
436			`U_ByteStuffer : entity work.ByteStuffer`
437			`port map`
438			`(`
439			`CLK => CLK,`
440			`RST => RST,`
441			`-- CTRL`
442			`start_pb => bs_start,`
443			`ready_pb => bs_ready,`
444
445			`-- HOST IF`
446			`sof => sof,`
447			`num_enc_bytes => num_enc_bytes,`
448			`outram_base_addr => outram_base_addr,`
449
450			`-- Huffman`
451			`huf_buf_sel => bs_buf_sel,`
452			`huf_fifo_empty => bs_fifo_empty,`
453			`huf_rd_req => bs_rd_req,`
454			`huf_packed_byte => bs_packed_byte,`
455
456			`-- OUT RAM`
457			`ram_byte => bs_ram_byte,`
458			`ram_wren => bs_ram_wren,`
459			`ram_wraddr => bs_ram_wraddr`
460			`);`
461
462			`-------------------------------------------------------------------`
463			`-- JFIF Generator`
464			`-------------------------------------------------------------------`
465			`U_JFIFGen : entity work.JFIFGen`
466			`port map`
467			`(`
468			`CLK => CLK,`
469			`RST => RST,`
470			`-- CTRL`
471			`start => jfif_start,`
472			`ready => jfif_ready,`
473			`eoi => jfif_eoi,`
474
475			`-- ByteStuffer`
476			`num_enc_bytes => num_enc_bytes,`
477
478			`-- HOST IF`
479			`qwren => qwren,`
480			`qwaddr => qaddr,`
481			`qwdata => qdata,`
482			`image_size_reg => image_size_reg,`
483			`image_size_reg_wr => img_size_wr,`
484
485			`-- OUT RAM`
486			`ram_byte => jfif_ram_byte,`
487			`ram_wren => jfif_ram_wren,`
488			`ram_wraddr => jfif_ram_wraddr`
489			`);`
490
491			`image_size_reg <= img_size_x & img_size_y;`
492
493			`-------------------------------------------------------------------`
494			`-- OutMux`
495			`-------------------------------------------------------------------`
496			`U_OutMux : entity work.OutMux`
497			`port map`
498			`(`
499			`CLK => CLK,`
500			`RST => RST,`

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