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[/] [mkjpeg/] [trunk/] [design/] [zigzag/] [ZIGZAG.VHD] - Blame information for rev 67

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1 25 mikel262 
--------------------------------------------------------------------------------
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--                                                                            --
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--                          V H D L    F I L E                                --
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--                          COPYRIGHT (C) 2006                                --
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--                                                                            --
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--------------------------------------------------------------------------------
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--                                                                            --
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-- Title       : ZIGZAG                                                       --
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-- Design      : MDCT CORE                                                    --
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-- Author      : Michal Krepa                                                 --
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--                                                                            --
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--------------------------------------------------------------------------------
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--                                                                            --
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-- File        : ZIGZAG.VHD                                                   --
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-- Created     : Sun Sep 3 2006                                               --
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--                                                                            --
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--------------------------------------------------------------------------------
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--                                                                            --
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--  Description : Zig-Zag scan                                                --
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--                                                                            --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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library IEEE;
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  use IEEE.STD_LOGIC_1164.All;
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  use IEEE.NUMERIC_STD.all;
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entity zigzag is
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  generic
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    (
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      RAMADDR_W     : INTEGER := 6;
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      RAMDATA_W     : INTEGER := 12
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    );
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  port
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    (
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      rst        : in  STD_LOGIC;
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      clk        : in  STD_LOGIC;
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      di         : in  STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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      divalid    : in  STD_LOGIC;
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      rd_addr    : in  unsigned(5 downto 0);
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      fifo_rden  : in  std_logic;
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      fifo_empty : out std_logic;
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      dout       : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
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      dovalid    : out std_logic;
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      zz_rd_addr : out STD_LOGIC_VECTOR(5 downto 0)
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    );
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end zigzag;
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architecture rtl of zigzag is
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  type ZIGZAG_TYPE is   array (0 to 2**RAMADDR_W-1) of INTEGER range 0 to 2**RAMADDR_W-1;
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  constant ZIGZAG_ARRAY : ZIGZAG_TYPE :=
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                      (
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                       0,1,8,16,9,2,3,10,
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                       17,24,32,25,18,11,4,5,
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                       12,19,26,33,40,48,41,34,
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                       27,20,13,6,7,14,21,28,
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                       35,42,49,56,57,50,43,36,
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                       29,22,15,23,30,37,44,51,
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                       58,59,52,45,38,31,39,46,
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                       53,60,61,54,47,55,62,63
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                      );
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  signal fifo_wr      : std_logic;
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  signal fifo_q       : std_logic_vector(11 downto 0);
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  signal fifo_full    : std_logic;
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  signal fifo_count   : std_logic_vector(6 downto 0);
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  signal fifo_data_in : std_logic_vector(11 downto 0);
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  signal fifo_empty_s : std_logic;
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begin
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  dout <= fifo_q;
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  fifo_empty <= fifo_empty_s;
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  -------------------------------------------------------------------
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  -- FIFO (show ahead)
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  -------------------------------------------------------------------
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  U_FIFO : entity work.FIFO
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  generic map
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  (
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        DATA_WIDTH        => 12,
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        ADDR_WIDTH        => 6
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  )
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  port map
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  (
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        rst               => RST,
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        clk               => CLK,
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        rinc              => fifo_rden,
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        winc              => fifo_wr,
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        datai             => fifo_data_in,
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        datao             => fifo_q,
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        fullo             => fifo_full,
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        emptyo            => fifo_empty_s,
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        count             => fifo_count
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  );
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  fifo_wr      <= divalid;
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  fifo_data_in <= di;
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  process(clk)
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  begin
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    if clk = '1' and clk'event then
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      if rst = '1' then
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        zz_rd_addr <= (others => '0');
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        dovalid    <= '0';
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      else
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        zz_rd_addr <= std_logic_vector(
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                      to_unsigned((ZIGZAG_ARRAY(to_integer(rd_addr))),6));
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        dovalid    <= fifo_rden and not fifo_empty_s;
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      end if;
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    end if;
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  end process;
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end rtl;
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