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[/] [mkjpeg/] [trunk/] [tb/] [modelsim.ini] - Blame information for rev 41

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1 25 mikel262
; Copyright 1991-2008 Mentor Graphics Corporation
2
;
3
; All Rights Reserved.
4
;
5
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
6
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
7
;
8
 
9
[Library]
10
others = $MODEL_TECH/../modelsim.ini
11
;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers       // Source files only for this release
12
;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
13
 
14
work = work
15
[vcom]
16
; VHDL93 variable selects language version as the default.
17
; Default is VHDL-2002.
18
; Value of 0 or 1987 for VHDL-1987.
19
; Value of 1 or 1993 for VHDL-1993.
20
; Default or value of 2 or 2002 for VHDL-2002.
21
VHDL93 = 2002
22
 
23
; Show source line containing error. Default is off.
24
; Show_source = 1
25
 
26
; Turn off unbound-component warnings. Default is on.
27
; Show_Warning1 = 0
28
 
29
; Turn off process-without-a-wait-statement warnings. Default is on.
30
; Show_Warning2 = 0
31
 
32
; Turn off null-range warnings. Default is on.
33
; Show_Warning3 = 0
34
 
35
; Turn off no-space-in-time-literal warnings. Default is on.
36
; Show_Warning4 = 0
37
 
38
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
39
; Show_Warning5 = 0
40
 
41
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
42
; Optimize_1164 = 0
43
 
44
; Turn on resolving of ambiguous function overloading in favor of the
45
; "explicit" function declaration (not the one automatically created by
46
; the compiler for each type declaration). Default is off.
47
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
48
; will match the behavior of synthesis tools.
49
Explicit = 1
50
 
51
; Turn off acceleration of the VITAL packages. Default is to accelerate.
52
; NoVital = 1
53
 
54
; Turn off VITAL compliance checking. Default is checking on.
55
; NoVitalCheck = 1
56
 
57
; Ignore VITAL compliance checking errors. Default is to not ignore.
58
; IgnoreVitalErrors = 1
59
 
60
; Turn off VITAL compliance checking warnings. Default is to show warnings.
61
; Show_VitalChecksWarnings = 0
62
 
63
; Turn off PSL assertion warning messages. Default is to show warnings.
64
; Show_PslChecksWarnings = 0
65
 
66
; Enable parsing of embedded PSL assertions. Default is enabled.
67
; EmbeddedPsl = 0
68
 
69
; Keep silent about case statement static warnings.
70
; Default is to give a warning.
71
; NoCaseStaticError = 1
72
 
73
; Keep silent about warnings caused by aggregates that are not locally static.
74
; Default is to give a warning.
75
; NoOthersStaticError = 1
76
 
77
; Treat as errors:
78
;   case statement static warnings
79
;   warnings caused by aggregates that are not locally static
80
; Overrides NoCaseStaticError, NoOthersStaticError settings.
81
; PedanticErrors = 1
82
 
83
; Turn off inclusion of debugging info within design units.
84
; Default is to include debugging info.
85
; NoDebug = 1
86
 
87
; Turn off "Loading..." messages. Default is messages on.
88
; Quiet = 1
89
 
90
; Turn on some limited synthesis rule compliance checking. Checks only:
91
;    -- signals used (read) by a process must be in the sensitivity list
92
; CheckSynthesis = 1
93
 
94
; Activate optimizations on expressions that do not involve signals,
95
; waits, or function/procedure/task invocations. Default is off.
96
; ScalarOpts = 1
97
 
98
; Turns on lint-style checking.
99
; Show_Lint = 1
100
 
101
; Require the user to specify a configuration for all bindings,
102
; and do not generate a compile time default binding for the
103
; component. This will result in an elaboration error of
104
; 'component not bound' if the user fails to do so. Avoids the rare
105
; issue of a false dependency upon the unused default binding.
106
; RequireConfigForAllDefaultBinding = 1
107
 
108
; Perform default binding at compile time.
109
; Default is to do default binding at load time.
110
; BindAtCompile=1;
111
 
112
; Inhibit range checking on subscripts of arrays. Range checking on
113
; scalars defined with subtypes is inhibited by default.
114
; NoIndexCheck = 1
115
 
116
; Inhibit range checks on all (implicit and explicit) assignments to
117
; scalar objects defined with subtypes.
118
; NoRangeCheck = 1
119
 
120
; Run the 0in tools from within the simulator.
121
; Default value set to 0. Please set it to 1 to invoke 0in.
122
; VcomZeroIn = 1
123
 
124
; Set the options to be passed to the 0in tools.
125
; Default value set to "". Please set it to appropriate options needed.
126
; VcomZeroInOptions = ""
127
 
128
; Turn on code coverage in VHDL design units. Default is off.
129
; Coverage = sbceft
130
 
131
; Turn off code coverage in VHDL subprograms. Default is on.
132
; CoverageNoSub = 0
133
 
134
; Automatically exclude VHDL case statement default branches.
135
; Default is to not exclude.
136
; CoverExcludeDefault = 1
137
 
138
; Turn on code coverage in VHDL generate blocks. Default is on.
139
CoverGenerate = 1
140
 
141
; Inform code coverage optimizations to respect VHDL 'H' and 'L'
142
; values on signals in conditions and expressions, and to not automatically
143
; convert them to '1' and '0'. Default is to not convert.
144
; CoverRespectHandL = 0
145
 
146
; Use this directory for compiler temporary files instead of "work/_temp"
147
; CompilerTempDir = /tmp
148
 
149
; Add VHDL-AMS declarations to package STANDARD
150
; Default is not to add
151
; AmsStandard = 1
152
 
153
; Range and length checking will be performed on array indices and discrete
154
; ranges, and when violations are found within subprograms, errors will be
155
; reported. Default is to issue warnings for violations, because subprograms
156
; may not be invoked.
157
; NoDeferSubpgmCheck = 0
158
 
159
[vlog]
160
 
161
; Turn off inclusion of debugging info within design units.
162
; Default is to include debugging info.
163
; NoDebug = 1
164
 
165
; Turn on `protect compiler directive processing.
166
; Default is to ignore `protect directives.
167
; Protect = 1
168
 
169
; Turn off "Loading..." messages. Default is messages on.
170
; Quiet = 1
171
 
172
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
173
; Default is off.
174
; Hazard = 1
175
 
176
; Turn on converting regular Verilog identifiers to uppercase. Allows case
177
; insensitivity for module names. Default is no conversion.
178
; UpCase = 1
179
 
180
; Activate optimizations on expressions that do not involve signals,
181
; waits, or function/procedure/task invocations. Default is off.
182
; ScalarOpts = 1
183
 
184
; Turns on lint-style checking.
185
; Show_Lint = 1
186
 
187
; Show source line containing error. Default is off.
188
; Show_source = 1
189
 
190
; Turn on bad option warning. Default is off.
191
; Show_BadOptionWarning = 1
192
 
193
; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
194
vlog95compat = 0
195
 
196
; Turn off PSL warning messages. Default is to show warnings.
197
; Show_PslChecksWarnings = 0
198
 
199
; Enable parsing of embedded PSL assertions. Default is enabled.
200
; EmbeddedPsl = 0
201
 
202
; Set the threshold for automatically identifying sparse Verilog memories.
203
; A memory with depth equal to or more than the sparse memory threshold gets
204
; marked as sparse automatically, unless specified otherwise in source code
205
; or by +nosparse commandline option of vlog or vopt.
206
; The default is 1M.  (i.e. memories with depth equal to or more than 1M are
207
; marked as sparse)
208
SparseMemThreshold = 1048576
209
 
210
; Set the maximum number of iterations permitted for a generate loop.
211
; Restricting this permits the implementation to recognize infinite
212
; generate loops.
213
; GenerateLoopIterationMax = 100000
214
 
215
; Set the maximum depth permitted for a recursive generate instantiation.
216
; Restricting this permits the implementation to recognize infinite
217
; recursions.
218
; GenerateRecursionDepthMax = 200
219
 
220
; Run the 0in tools from within the simulator.
221
; Default value set to 0. Please set it to 1 to invoke 0in.
222
; VlogZeroIn = 1
223
 
224
; Set the options to be passed to the 0in tools.
225
; Default value set to "". Please set it to appropriate options needed.
226
; VlogZeroInOptions = ""
227
 
228
; Run the 0in tools from within the simulator.
229
; Default value set to 0. Please set it to 1 to invoke 0in.
230
; VoptZeroIn = 1
231
 
232
; Set the options to be passed to the 0in tools.
233
; Default value set to "". Please set it to appropriate options needed.
234
; VoptZeroInOptions = ""
235
 
236
; Set the option to treat all files specified in a vlog invocation as a
237
; single compilation unit. The default value is set to 0 which will treat
238
; each file as a separate compilation unit as specified in the P1800 draft standard.
239
; MultiFileCompilationUnit = 1
240
 
241
; Turn on code coverage in Verilog design units. Default is off.
242
; Coverage = sbceft
243
 
244
; Automatically exclude Verilog case statement default branches.
245
; Default is to not exclude.
246
; CoverExcludeDefault = 1
247
 
248
; Turn on code coverage in VLOG generate blocks. Default is on.
249
CoverGenerate = 1
250
 
251
; Turn on code coverage in VLOG `celldefine modules and modules included
252
; using vlog -v and -y. Default is on.
253
CoverCells = 0
254
 
255
; Control compiler and VOPT optimizations that are allowed when
256
; code coverage is on. This is a number from 1 to 4, with the following
257
; meanings (the default is 3):
258
;    1 -- Turn off all optimizations that affect coverage reports.
259
;    2 -- Allow optimizations that allow large performance improvements
260
;         by invoking sequential processes only when the data changes.
261
;         Allow VHDL FF recognition. This may make major reductions in
262
;         coverage counts.
263
;    3 -- In addition, allow optimizations that may change expressions or
264
;         remove some statements. Allow constant propagation.
265
;    4 -- In addition, allow optimizations that may remove major regions of
266
;         code by changing assignments to built-ins or removing unused
267
;         signals. Allow VHDL subprogram inlining. Change Verilog gates to
268
;         continuous assignments.
269
CoverOpt = 3
270
 
271
; Specify the override for the default value of "cross_num_print_missing"
272
; option for the Cross in Covergroups. If not specified then LRM default
273
; value of 0 (zero) is used. This is a compile time option.
274
; SVCrossNumPrintMissingDefault = 0
275
 
276
; Setting following to 1 would cause creation of variables which
277
; would represent the value of Coverpoint expressions. This is used
278
; in conjunction with "SVCoverpointExprVariablePrefix" option
279
; in the modelsim.ini
280
; EnableSVCoverpointExprVariable = 0
281
 
282
; Specify the override for the prefix used in forming the variable names
283
; which represent the Coverpoint expressions. This is used in conjunction with
284
; "EnableSVCoverpointExprVariable" option of the modelsim.ini
285
; The default prefix is "expr".
286
; The variable name is
287
;    variable name => _
288
; SVCoverpointExprVariablePrefix = expr
289
 
290
; Override for the default value of the SystemVerilog covergroup,
291
; coverpoint, and cross option.goal (defined to be 100 in the LRM).
292
; NOTE: It does not override specific assignments in SystemVerilog
293
; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
294
; can override this value.
295
; SVCovergroupGoalDefault = 100
296
 
297
; Override for the default value of the SystemVerilog covergroup,
298
; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
299
; NOTE: It does not override specific assignments in SystemVerilog
300
; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
301
; can override this value.
302
; SVCovergroupTypeGoalDefault = 100
303
 
304
; Specify the override for the default value of "strobe" option for the
305
; Covergroup Type. This is a compile time option which forces "strobe" to
306
; a user specified default value and supersedes SystemVerilog specified
307
; default value of '0'(zero). NOTE: This can be overriden by a runtime
308
; modelsim.ini variable "SVCovergroupStrobeDefault".
309
; SVCovergroupStrobeDefault = 0
310
 
311
; Specify the override for the default value of "per_instance" option for the
312
; Covergroup variables. This is a compile time option which forces "per_instance"
313
; to a user specified default value and supersedes SystemVerilog specified
314
; default value of '0'(zero). NOTE: This can be overriden by a runtime
315
; modelsim.ini variable "SVCovergroupPerInstanceDefault".
316
; SVCovergroupPerInstanceDefault = 0
317
 
318
;
319
; A space separated list of resource libraries that contain precompiled
320
; packages.  The behavior is identical to using the "-L" switch.
321
;
322
; LibrarySearchPath =  [ ...]
323
LibrarySearchPath = mtiAvm
324
 
325
; The behavior is identical to the "-mixedansiports" switch.  Default is off.
326
; MixedAnsiPorts = 1
327
 
328
; Enable SystemVerilog 3.1a $typeof() function. Default is off.
329
; EnableTypeOf = 1
330
 
331
; Only allow lower case pragmas. Default is disabled.
332
; AcceptLowerCasePragmaOnly = 1
333
 
334
; Set the maximum depth permitted for a recursive include file nesting.
335
; IncludeRecursionDepthMax = 5
336
 
337
[sccom]
338
; Enable use of SCV include files and library.  Default is off.
339
; UseScv = 1
340
 
341
; Add C++ compiler options to the sccom command line by using this variable.
342
; CppOptions = -g
343
 
344
; Use custom C++ compiler located at this path rather than the default path.
345
; The path should point directly at a compiler executable.
346
; CppPath = /usr/bin/g++
347
 
348
; Enable verbose messages from sccom.  Default is off.
349
; SccomVerbose = 1
350
 
351
; sccom logfile.  Default is no logfile.
352
; SccomLogfile = sccom.log
353
 
354
; Enable use of SC_MS include files and library.  Default is off.
355
; UseScMs = 1
356
 
357
[vsim]
358
 
359
; vopt flow
360
; Set to turn on automatic optimization of a design.
361
; Default is on
362
VoptFlow = 1
363
 
364
; vopt automatic SDF
365
; If automatic design optimization is on, enables automatic compilation
366
; of SDF files.
367
; Default is on, uncomment to turn off.
368
; VoptAutoSDFCompile = 0
369
 
370
; Simulator resolution
371
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
372
Resolution = ns
373
 
374
; Enables certain code coverage exclusions automatically. Set AutoExclusions = none to disable.
375
AutoExclusions = fsm
376
 
377
; User time unit for run commands
378
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
379
; unit specified for Resolution. For example, if Resolution is 100ps,
380
; then UserTimeUnit defaults to ps.
381
; Should generally be set to default.
382
UserTimeUnit = default
383
 
384
; Default run length
385
RunLength = 100
386
 
387
; Maximum iterations that can be run without advancing simulation time
388
IterationLimit = 5000
389
 
390
; Control PSL and Verilog Assume directives during simulation
391
; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
392
; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
393
; SimulateAssumeDirectives = 1
394
 
395
; Control the simulation of PSL and SVA
396
; These switches can be overridden by the vsim command line switches:
397
;    -psl, -nopsl, -sva, -nosva.
398
; Set SimulatePSL = 0 to disable PSL simulation
399
; Set SimulatePSL = 1 to enable PSL simulation (default)
400
; SimulatePSL = 1
401
; Set SimulateSVA = 0 to disable SVA simulation
402
; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
403
; SimulateSVA = 1
404
 
405
; Directives to license manager can be set either as single value or as
406
; space separated multi-values:
407
; vhdl          Immediately reserve a VHDL license
408
; vlog          Immediately reserve a Verilog license
409
; plus          Immediately reserve a VHDL and Verilog license
410
; nomgc         Do not look for Mentor Graphics Licenses
411
; nomti         Do not look for Model Technology Licenses
412
; noqueue       Do not wait in the license queue when a license is not available
413
; viewsim       Try for viewer license but accept simulator license(s) instead
414
;               of queuing for viewer license (PE ONLY)
415
; noviewer      Disable checkout of msimviewer and vsim-viewer license
416
;               features (PE ONLY)
417
; noslvhdl      Disable checkout of qhsimvh and vsim license features
418
; noslvlog      Disable checkout of qhsimvl and vsimvlog license features
419
; nomix         Disable checkout of msimhdlmix and hdlmix license features
420
; nolnl         Disable checkout of msimhdlsim and hdlsim license features
421
; mixedonly     Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
422
;               features
423
; lnlonly       Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
424
;               hdlmix license features
425
; Single value:
426
; License = plus
427
; Multi-value:
428
; License = noqueue plus
429
 
430
; Stop the simulator after a VHDL/Verilog immediate assertion message
431
; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
432
BreakOnAssertion = 3
433
 
434
; VHDL assertion Message Format
435
; %S - Severity Level
436
; %R - Report Message
437
; %T - Time of assertion
438
; %D - Delta
439
; %I - Instance or Region pathname (if available)
440
; %i - Instance pathname with process
441
; %O - Process name
442
; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
443
; %P - Instance or Region path without leaf process
444
; %F - File
445
; %L - Line number of assertion or, if assertion is in a subprogram, line
446
;      from which the call is made
447
; %% - Print '%' character
448
; If specific format for assertion level is defined, use its format.
449
; If specific format is not defined for assertion level:
450
; - and if failure occurs during elaboration, use MessageFormatBreakLine;
451
; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
452
;   level), use MessageFormatBreak;
453
; - otherwise, use MessageFormat.
454
; MessageFormatBreakLine = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F Line: %L\n"
455
; MessageFormatBreak     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
456
; MessageFormat          = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
457
; MessageFormatNote      = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
458
; MessageFormatWarning   = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
459
; MessageFormatError     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
460
; MessageFormatFail      = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
461
; MessageFormatFatal     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
462
 
463
; Error File - alternate file for storing error messages
464
; ErrorFile = error.log
465
 
466
 
467
; Simulation Breakpoint messages
468
; This flag controls the display of function names when reporting the location
469
; where the simulator stops do to a breakpoint or fatal error.
470
; Example w/function name:  # Break in Process ctr at counter.vhd line 44
471
; Example wo/function name: # Break at counter.vhd line 44
472
ShowFunctions = 1
473
 
474
 
475
; Default radix for all windows and commands.
476
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
477
DefaultRadix = symbolic
478
 
479
; VSIM Startup command
480
; Startup = do startup.do
481
 
482
; File for saving command transcript
483
TranscriptFile = transcript
484
 
485
; File for saving command history
486
; CommandHistory = cmdhist.log
487
 
488
; Specify whether paths in simulator commands should be described
489
; in VHDL or Verilog format.
490
; For VHDL, PathSeparator = /
491
; For Verilog, PathSeparator = .
492
; Must not be the same character as DatasetSeparator.
493
PathSeparator = /
494
 
495
; Specify the dataset separator for fully rooted contexts.
496
; The default is ':'. For example: sim:/top
497
; Must not be the same character as PathSeparator.
498
DatasetSeparator = :
499
 
500
; Specify a unique path separator for the Signal Spy set of functions.
501
; The default will be to use the PathSeparator variable.
502
; Must not be the same character as DatasetSeparator.
503
; SignalSpyPathSeparator = /
504
 
505
; Used to control parsing of HDL identifiers input to the tool.
506
; This includes CLI commands, vsim/vopt/vlog/vcom options,
507
; string arguments to FLI/VPI/DPI calls, etc.
508
; If set to 1, accept either Verilog escaped Id syntax or
509
; VHDL extended id syntax, regardless of source language.
510
; If set to 0, the syntax of the source language must be used.
511
; Each identifier in a hierarchical name may need different syntax,
512
; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
513
;       "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
514
; GenerousIdentifierParsing = 1
515
 
516
; Disable VHDL assertion messages
517
; IgnoreNote = 1
518
; IgnoreWarning = 1
519
; IgnoreError = 1
520
; IgnoreFailure = 1
521
 
522
; Disable System Verilog assertion messages
523
; Info and Warning are disabled by default
524
; IgnoreSVAInfo = 0
525
; IgnoreSVAWarning = 0
526
; IgnoreSVAError = 1
527
; IgnoreSVAFatal = 1
528
 
529
; Default force kind. May be freeze, drive, deposit, or default
530
; or in other terms, fixed, wired, or charged.
531
; A value of "default" will use the signal kind to determine the
532
; force kind, drive for resolved signals, freeze for unresolved signals
533
; DefaultForceKind = freeze
534
 
535
; If zero, open files when elaborated; otherwise, open files on
536
; first read or write.  Default is 0.
537
; DelayFileOpen = 1
538
 
539
; Control VHDL files opened for write.
540
;   0 = Buffered, 1 = Unbuffered
541
UnbufferedOutput = 0
542
 
543
; Control the number of VHDL files open concurrently.
544
; This number should always be less than the current ulimit
545
; setting for max file descriptors.
546
;   0 = unlimited
547
ConcurrentFileLimit = 40
548
 
549
; Control the number of hierarchical regions displayed as
550
; part of a signal name shown in the Wave window.
551
; A value of zero tells VSIM to display the full name.
552
; The default is 0.
553
; WaveSignalNameWidth = 0
554
 
555
; Turn off warnings when changing VHDL constants and generics
556
; Default is 1 to generate warning messages
557
; WarnConstantChange = 0
558
 
559
; Turn off warnings from the std_logic_arith, std_logic_unsigned
560
; and std_logic_signed packages.
561
; StdArithNoWarnings = 1
562
 
563
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
564
; NumericStdNoWarnings = 1
565
 
566
; Control the format of the (VHDL) FOR generate statement label
567
; for each iteration.  Do not quote it.
568
; The format string here must contain the conversion codes %s and %d,
569
; in that order, and no other conversion codes.  The %s represents
570
; the generate_label; the %d represents the generate parameter value
571
; at a particular generate iteration (this is the position number if
572
; the generate parameter is of an enumeration type).  Embedded whitespace
573
; is allowed (but discouraged); leading and trailing whitespace is ignored.
574
; Application of the format must result in a unique scope name over all
575
; such names in the design so that name lookup can function properly.
576
; GenerateFormat = %s__%d
577
 
578
; Specify whether checkpoint files should be compressed.
579
; The default is 1 (compressed).
580
; CheckpointCompressMode = 0
581
 
582
; Specify whether to enable SystemVerilog DPI out-of-the-blue call.
583
; Out-of-the-blue call refers to a SystemVerilog export function call
584
; directly from a C function that don't have the proper context setup
585
; as done in DPI-C import C functions. When this is enabled, one can
586
; call a DPI export function (but not task) from any C code.
587
; The default is 0 (disabled).
588
; DpiOutOfTheBlue = 1
589
 
590
; List of dynamically loaded objects for Verilog PLI applications
591
; Veriuser = veriuser.sl
592
 
593
 
594
; Should the tool conform to the 2001 or 2005 VPI object model
595
; Note that System Verilog objects are only available in the 2005 object model
596
; The tool default is the latest available LRM behavior
597
; Options here are: 2001 2005 latest
598
; PliCompatDefault = 2005
599
 
600
; Specify default options for the restart command. Options can be one
601
; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
602
; DefaultRestartOptions = -force
603
 
604
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
605
; (> 500 megabyte memory footprint). Default is disabled.
606
; Specify number of megabytes to lock.
607
; LockedMemory = 1000
608
 
609
; HP-UX 11.00 ONLY - Use /usr/lib/libCsup_v2.sl for shared object loading.
610
; This is necessary when C++ files have been compiled with aCC's -AA option.
611
; The default behavior is to use /usr/lib/libCsup.sl.
612
; UseCsupV2 = 1
613
 
614
; Turn on (1) or off (0) WLF file compression.
615
; The default is 1 (compress WLF file).
616
; WLFCompress = 0
617
 
618
; Specify whether to save all design hierarchy (1) in the WLF file
619
; or only regions containing logged signals (0).
620
; The default is 0 (save only regions with logged signals).
621
; WLFSaveAllRegions = 1
622
 
623
; WLF file time limit.  Limit WLF file by time, as closely as possible,
624
; to the specified amount of simulation time.  When the limit is exceeded
625
; the earliest times get truncated from the file.
626
; If both time and size limits are specified the most restrictive is used.
627
; UserTimeUnits are used if time units are not specified.
628
; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
629
; WLFTimeLimit = 0
630
 
631
; WLF file size limit.  Limit WLF file size, as closely as possible,
632
; to the specified number of megabytes.  If both time and size limits
633
; are specified then the most restrictive is used.
634
; The default is 0 (no limit).
635
; WLFSizeLimit = 1000
636
 
637
; Specify whether or not a WLF file should be deleted when the
638
; simulation ends.  A value of 1 will cause the WLF file to be deleted.
639
; The default is 0 (do not delete WLF file when simulation ends).
640
; WLFDeleteOnQuit = 1
641
 
642
; Specify whether or not a WLF file should be optimized during
643
; simulation.  If set to 0, the WLF file will not be optimized.
644
; The default is 1, optimize the WLF file.
645
; WLFOptimize = 0
646
 
647
; Specify the name of the WLF file.
648
; The default is vsim.wlf
649
; WLFFilename = vsim.wlf
650
 
651
; Specify the WLF reader cache size limit for each open WLF file.
652
; The size is giving in megabytes.  A value of 0 turns off the
653
; WLF cache.
654
; WLFSimCacheSize allows a different cache size to be set for
655
; simulation WLF file independent of post-simulation WLF file
656
; viewing.  If WLFSimCacheSize is not set it defaults to the
657
; WLFCacheSize setting.
658
; The default WLFCacheSize setting is enabled to 256M per open WLF file.
659
; WLFCacheSize = 2000
660
; WLFSimCacheSize = 500
661
 
662
; Specify the WLF file event collapse mode.
663
; 0 = Preserve all events and event order. (same as -wlfnocollapse)
664
; 1 = Only record values of logged objects at the end of a simulator iteration.
665
;     (same as -wlfcollapsedelta)
666
; 2 = Only record values of logged objects at the end of a simulator time step.
667
;     (same as -wlfcollapsetime)
668
; The default is 1.
669
; WLFCollapseMode = 0
670
 
671
; Specify whether WLF file logging can use threads on multi-processor machines
672
; if 0, no threads will be used, if 1, threads will be used if the system has
673
; more than one processor
674
; WLFUseThreads = 1
675
 
676
; Turn on/off undebuggable SystemC type warnings. Default is on.
677
; ShowUndebuggableScTypeWarning = 0
678
 
679
; Turn on/off unassociated SystemC name warnings. Default is off.
680
; ShowUnassociatedScNameWarning = 1
681
 
682
; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
683
; ScShowIeeeDeprecationWarnings = 1
684
 
685
; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
686
; ScEnableScSignalWriteCheck = 1
687
 
688
; Set SystemC default time unit.
689
; Set to fs, ps, ns, us, ms, or sec with optional
690
; prefix of 1, 10, or 100.  The default is 1 ns.
691
; The ScTimeUnit value is honored if it is coarser than Resolution.
692
; If ScTimeUnit is finer than Resolution, it is set to the value
693
; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
694
; then the default time unit will be 1 ns.  However if Resolution
695
; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
696
ScTimeUnit = ns
697
 
698
; Set SystemC sc_main stack size. The stack size is set as an integer
699
; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
700
; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
701
; on the amount of data on the sc_main() stack and the memory required
702
; to succesfully execute the longest function call chain of sc_main().
703
ScMainStackSize = 10 Mb
704
 
705
; Turn on/off execution of remainder of sc_main upon quitting the current
706
; simulation session. If the cumulative length of sc_main() in terms of
707
; simulation time units is less than the length of the current simulation
708
; run upon quit or restart, sc_main() will be in the middle of execution.
709
; This switch gives the option to execute the remainder of sc_main upon
710
; quitting simulation. The drawback of not running sc_main till the end
711
; is memory leaks for objects created by sc_main. If on, the remainder of
712
; sc_main will be executed ignoring all delays. This may cause the simulator
713
; to crash if the code in sc_main is dependent on some simulation state.
714
; Default is on.
715
ScMainFinishOnQuit = 1
716
 
717
; Set the SCV relationship name that will be used to identify phase
718
; relations.  If the name given to a transactor relation matches this
719
; name, the transactions involved will be treated as phase transactions
720
ScvPhaseRelationName = mti_phase
721
 
722
; Customize the vsim kernel shutdown behavior at the end of the simulation.
723
; Some common causes of the end of simulation are $finish (implicit or explicit),
724
; sc_stop(), tf_dofinish(), and assertion failures.
725
; This should be set to "ask", "exit", or "stop". The default is "ask".
726
; "ask"  -- In batch mode, the vsim kernel will abruptly exit.
727
;           In GUI mode, a dialog box will pop up and ask for user confirmation
728
;           whether or not to quit the simulation.
729
; "stop" -- Cause the simulation to stay loaded in memory. This can make some
730
;           post-simulation tasks easier.
731
; "exit" -- The simulation will abruptly exit without asking for any confirmation.
732
; Note: these ini variables can be overriden by the vsim command
733
;       line switch "-onfinish ".
734
OnFinish = ask
735
 
736
; Print "simstats" result at the end of simulation before shutdown.
737
; If this is enabled, the simstats result will be printed out before shutdown.
738
; The default is off.
739
; PrintSimStats = 1
740
 
741
; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
742
; AssertFile = assert.log
743
 
744
; Run simulator in assertion debug mode. Default is off.
745
; AssertionDebug = 1
746
 
747
; Turn on/off PSL/SVA concurrent assertion pass enable.
748
; For SVA, Default is on when the assertion has a pass action block or vsim switch -assertdebug is used and the visibility flag "+acc=a" is turned on in vopt.
749
; For PSL, Default is on only when vsim switch "-assertdebug" is used and the visibility flag "+acc=a" is turned on in vopt.
750
; AssertionPassEnable = 0
751
 
752
; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on.
753
; AssertionFailEnable = 0
754
 
755
; Set PSL/SVA concurrent assertion pass limit. Default is -1.
756
; Any positive integer, -1 for infinity.
757
; AssertionPassLimit = 1
758
 
759
; Set PSL/SVA concurrent assertion fail limit. Default is -1.
760
; Any positive integer, -1 for infinity.
761
; AssertionFailLimit = 1
762
 
763
; Turn on/off PSL concurrent assertion pass log. Default is off.
764
; The flag does not affect SVA
765
; AssertionPassLog = 1
766
 
767
; Turn on/off PSL concurrent assertion fail log. Default is on.
768
; The flag does not affect SVA
769
; AssertionFailLog = 0
770
 
771
; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
772
; 0 = Continue  1 = Break  2 = Exit
773
; AssertionFailAction = 1
774
 
775
; Enable the active thread monitor in the waveform display when assertion debug is enabled.
776
; AssertionActiveThreadMonitor = 1
777
 
778
; Control how many waveform rows will be used for displaying the active threads.  Default is 5.
779
; AssertionActiveThreadMonitorLimit = 5
780
 
781
; Control how many thread start times will be preserved for ATV viewing for a given assertion
782
; instance.  Default is -1 (ALL).
783
; ATVStartTimeKeepCount = -1
784
 
785
; Turn on/off code coverage
786
; CodeCoverage = 0
787
 
788
; Count all code coverage condition and expression truth table rows that match.
789
; CoverCountAll = 1
790
 
791
; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
792
; is to include them.
793
; ToggleNoIntegers = 1
794
 
795
; Set the maximum number of values that are collected for toggle coverage of
796
; VHDL integers. Default is 100;
797
; ToggleMaxIntValues = 100
798
 
799
; Turn on automatic inclusion of Verilog integers in toggle coverage, except
800
; for enumeration types. Default is to not include them.
801
; ToggleVlogIntegers = 1
802
 
803
; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
804
; For unlimited width, set to 0.
805
; ToggleWidthLimit = 128
806
 
807
; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
808
; reached this count, further activity on the bit is ignored. Default is 1.
809
; For unlimited counts, set to 0.
810
; ToggleCountLimit = 1
811
 
812
; Turn on/off all PSL/SVA cover directive enables.  Default is on.
813
; CoverEnable = 0
814
 
815
; Turn on/off PSL/SVA cover log.  Default is off.
816
; CoverLog = 1
817
 
818
; Set "at_least" value for all PSL/SVA cover directives.  Default is 1.
819
; CoverAtLeast = 2
820
 
821
; Set "limit" value for all PSL/SVA cover directives.  Default is -1.
822
; Any positive integer, -1 for infinity.
823
; CoverLimit = 1
824
 
825
; Specify the coverage database filename.  Default is "" (i.e. database is NOT automatically saved on close).
826
; UCDBFilename = vsim.ucdb
827
 
828
; Specify the maximum limit for the number of Cross (bin) products reported
829
; in XML and UCDB report against a Cross. A warning is issued if the limit
830
; is crossed.
831
; MaxReportRhsSVCrossProducts = 1000
832
 
833
; Specify the override for the "auto_bin_max" option for the Covergroups.
834
; If not specified then value from Covergroup "option" is used.
835
; SVCoverpointAutoBinMax = 64
836
 
837
; Specify the override for the value of "cross_num_print_missing"
838
; option for the Cross in Covergroups. If not specified then value
839
; specified in the "option.cross_num_print_missing" is used. This
840
; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
841
; value specified by user in source file and any SVCrossNumPrintMissingDefault
842
; specified in modelsim.ini.
843
; SVCrossNumPrintMissing = 0
844
 
845
; Specify whether to use the value of "cross_num_print_missing"
846
; option in report and GUI for the Cross in Covergroups. If not specified then
847
; cross_num_print_missing is ignored for creating reports and displaying
848
; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
849
; UseSVCrossNumPrintMissing = 0
850
 
851
; Specify the override for the value of "strobe" option for the
852
; Covergroup Type. If not specified then value in "type_option.strobe"
853
; will be used. This is runtime option which forces "strobe" to
854
; user specified value and supersedes user specified values in the
855
; SystemVerilog Code. NOTE: This also overrides the compile time
856
; default value override specified using "SVCovergroupStrobeDefault"
857
; SVCovergroupStrobe = 0
858
 
859
; Override for explicit assignments in source code to "option.goal" of
860
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
861
; default value of "option.goal" (defined to be 100 in the SystemVerilog
862
; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
863
; SVCovergroupGoal = 100
864
 
865
; Override for explicit assignments in source code to "type_option.goal" of
866
; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
867
; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
868
; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
869
; SVCovergroupTypeGoal = 100
870
 
871
; Enable or disable generation of more detailed information about the sampling of covergroup,
872
; cross, and coverpoints. It provides the details of the number of times the covergroup
873
; instance and type were sampled, as well as details about why covergroup, cross and
874
; coverpoint were not covered. A non-zero value is to enable this feature. 0 is to
875
; disable this feature. Default is 0;
876
; SVCovergroupSampleInfo = 0
877
 
878
; Specify the maximum number of Coverpoint bins in whole design for
879
; all Covergroups.
880
; MaxSVCoverpointBinsDesign = 2147483648
881
 
882
; Specify maximum number of Coverpoint bins in any instance of a Covergroup
883
; MaxSVCoverpointBinsInst = 2147483648
884
 
885
; Specify the maximum number of Cross bins in whole design for
886
; all Covergroups.
887
; MaxSVCrossBinsDesign = 2147483648
888
 
889
; Specify maximum number of Cross bins in any instance of a Covergroup
890
; MaxSVCrossBinsInst = 2147483648
891
 
892
; Set weight for all PSL/SVA cover directives.  Default is 1.
893
; CoverWeight = 2
894
 
895
; Check vsim plusargs.  Default is 0 (off).
896
; 0 = Don't check plusargs
897
; 1 = Warning on unrecognized plusarg
898
; 2 = Error and exit on unrecognized plusarg
899
; CheckPlusargs = 1
900
 
901
; Load the specified shared objects with the RTLD_GLOBAL flag.
902
; This gives global visibility to all symbols in the shared objects,
903
; meaning that subsequently loaded shared objects can bind to symbols
904
; in the global shared objects.  The list of shared objects should
905
; be whitespace delimited.  This option is not supported on the
906
; Windows or AIX platforms.
907
; GlobalSharedObjectList = example1.so example2.so example3.so
908
 
909
; Run the 0in tools from within the simulator.
910
; Default value set to 0. Please set it to 1 to invoke 0in.
911
; VsimZeroIn = 1
912
 
913
; Set the options to be passed to the 0in tools.
914
; Default value set to "". Please set it to appropriate options needed.
915
; VsimZeroInOptions = ""
916
 
917
; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog).
918
; Sv_Seed = 0
919
 
920
; Maximum size of dynamic arrays that are resized during randomize().
921
; The default is 1000. A value of 0 indicates no limit.
922
; SolveArrayResizeMax = 1000
923
 
924
; Error message severity when randomize() failure is detected (SystemVerilog).
925
; The default is 0 (no error).
926
; 0 = No error  1 = Warning  2 = Error  3 = Failure  4 = Fatal
927
; SolveFailSeverity = 0
928
 
929
; Enable/disable debug information for randomize() failures (SystemVerilog).
930
; The default is 0 (disabled). Set to 1 to enable.
931
; SolveFailDebug = 0
932
 
933
; When SolveFailDebug is enabled, this value specifies the algorithm used to
934
; discover conflicts between constraints for randomize() failures.
935
; The default is "many".
936
;
937
; Valid schemes are:
938
;    "many" = best for determining conflicts due to many related constraints
939
;    "few"  = best for determining conflicts due to few related constraints
940
;
941
; SolveFailDebugScheme = many
942
 
943
; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
944
; specifies the maximum number of constraint subsets that will be tested for
945
; conflicts.
946
; The default is 0 (no limit).
947
; SolveFailDebugLimit = 0
948
 
949
; When SolveFailDebug is enabled and SolveFailDebugScheme is "few", this value
950
; specifies the maximum size of constraint subsets that will be tested for
951
; conflicts.
952
; The default value is 0 (no limit).
953
; SolveFailDebugMaxSet = 0
954
 
955
; Maximum size of the solution graph that may be generated during randomize().
956
; This value can be used to force randomize() to abort if the complexity of
957
; the constraint scenario (both in memory and time spent during evaluation)
958
; exceeds the specified limit. This value is specified in 1000s of nodes.
959
; The default is 10000. A value of 0 indicates no limit.
960
; SolveGraphMaxSize = 10000
961
 
962
; Use SolveFlags to specify options that will guide the behavior of the
963
; constraint solver. These options may improve the performance of the
964
; constraint solver for some testcases, and decrease the performance of
965
; the constraint solver for others.
966
; The default value is "" (no options).
967
;
968
; Valid flags are:
969
;    i = disable bit interleaving for >, >=, <, <= constraints
970
;    n = disable bit interleaving for all constraints
971
;    r = reverse bit interleaving
972
;
973
; SolveFlags =
974
 
975
; Specify random sequence compatiblity with a prior letter release. This
976
; option is used to get the same random sequences during simulation as
977
; as a prior letter release. Only prior letter releases (of the current
978
; number release) are allowed.
979
; Note: To achieve the same random sequences, solver optimizations and/or
980
; bug fixes introduced since the specified release may be disabled -
981
; yielding the performance / behavior of the prior release.
982
; Default value set to "" (random compatibility not required).
983
; SolveRev =
984
 
985
; Environment variable expansion of command line arguments has been depricated
986
; in favor shell level expansion.  Universal environment variable expansion
987
; inside -f files is support and continued support for MGC Location Maps provide
988
; alternative methods for handling flexible pathnames.
989
; The following line may be uncommented and the value set to 1 to re-enable this
990
; deprecated behavior.  The default value is 0.
991
; DeprecatedEnvironmentVariableExpansion = 0
992
 
993
; Turn on/off collapsing of bus ports in VCD dumpports output
994
DumpportsCollapse = 1
995
 
996
StdArithNoWarnings = 1
997
NumericStdNoWarnings = 1
998
[lmc]
999
; The simulator's interface to Logic Modeling's SmartModel SWIFT software
1000
libsm = $MODEL_TECH/libsm.sl
1001
; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
1002
; libsm = $MODEL_TECH/libsm.dll
1003
;  Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
1004
; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
1005
;  Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
1006
; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
1007
;  Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
1008
; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
1009
;  Logic Modeling's SmartModel SWIFT software (Windows NT)
1010
; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
1011
;  Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
1012
; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
1013
;  Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
1014
; libswift = $LMC_HOME/lib/linux.lib/libswift.so
1015
 
1016
; The simulator's interface to Logic Modeling's hardware modeler SFI software
1017
libhm = $MODEL_TECH/libhm.sl
1018
; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
1019
; libhm = $MODEL_TECH/libhm.dll
1020
;  Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
1021
; libsfi = /lib/hp700/libsfi.sl
1022
;  Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
1023
; libsfi = /lib/rs6000/libsfi.a
1024
;  Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
1025
; libsfi = /lib/sun4.solaris/libsfi.so
1026
;  Logic Modeling's hardware modeler SFI software (Windows NT)
1027
; libsfi = /lib/pcnt/lm_sfi.dll
1028
;  Logic Modeling's hardware modeler SFI software (Linux)
1029
; libsfi = /lib/linux/libsfi.so
1030
 
1031
[msg_system]
1032
; Change a message severity or suppress a message.
1033
; The format is:  = [,...]
1034
; Examples:
1035
;   note = 3009
1036
;   warning = 3033
1037
;   error = 3010,3016
1038
;   fatal = 3016,3033
1039
;   suppress = 3009,3016,3043
1040
; The command verror  can be used to get the complete
1041
; description of a message.
1042
 
1043
; Control transcripting of elaboration/runtime messages.
1044
; The default is to have messages appear in the transcript and
1045
; recorded in the wlf file (messages that are recorded in the
1046
; wlf file can be viewed in the MsgViewer).  The other settings
1047
; are to send messages only to the transcript or only to the
1048
; wlf file.  The valid values are
1049
;    both  {default}
1050
;    tran  {transcript only}
1051
;    wlf   {wlf file only}
1052
; msgmode = both
1053
 
1054
; Control transcripting of Verilog display system task messages.
1055
; These system tasks include $display[bho], $strobe[bho],
1056
; Smonitor{bho], and $write[bho].  They also include the analogous
1057
; file I/O tasks that write to STDOUT (i.e. $fwrite or $fdisplay).
1058
; The default is to have messages appear only in the transcript.
1059
; The other settings are to send messages to the wlf file only
1060
; (messages that are recorded in the wlf file can be viewed in the
1061
; MsgViewer) or to both the transcript and the wlf file.  The valid
1062
; values are
1063
;    tran  {transcript only (default)}
1064
;    wlf   {wlf file only}
1065
;    both  {transcript and wlf file}
1066
; displaymsgmode = tran
1067
 

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