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[/] [mkjpeg/] [trunk/] [tb/] [vhdl/] [ClkGen.vhd] - Blame information for rev 61

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Line No. Rev Author Line
1 25 mikel262
 
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- LIBRARY/PACKAGE ---------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- generic packages/libraries:
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-------------------------------------------------------------------------------
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library ieee;
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        use ieee.std_logic_1164.all;
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        use ieee.numeric_std.all;
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-------------------------------------------------------------------------------
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-- user packages/libraries:
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ENTITY ------------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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entity ClkGen is
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        port (
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             CLK                             : out  std_logic;
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             RST                             : out  std_logic
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             );
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end entity ClkGen;
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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----------------------------------- ARCHITECTURE ------------------------------
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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architecture ClkGen_rtl of ClkGen is
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        constant CLOCK_PERIOD : time := 10 ns;
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        signal clk_s : std_logic := '0';
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        signal rst_s : std_logic := '0';
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begin
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  -- Clock generator (50% duty cycle)
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        clk_gen: process
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        begin
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                clk_s <= '0';
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                wait for CLOCK_PERIOD/2;
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                clk_s <= '1';
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                wait for CLOCK_PERIOD/2;
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        end process clk_gen;
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        CLK <= clk_s;
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        reset_gen: process
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        begin
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                wait until rising_edge(clk_s);
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                rst_s <= '0';
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                wait until rising_edge(clk_s);
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                rst_s <= '1';
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                wait until rising_edge(clk_s);
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                rst_s <= '0';
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                wait;
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        end process reset_gen;
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        RST <= rst_s;
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end architecture ClkGen_rtl;

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