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mikel262 |
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-- --
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-- V H D L F I L E --
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-- COPYRIGHT (C) 2006 --
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-- --
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--------------------------------------------------------------------------------
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--
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-- Title : DCT
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-- Design : MDCT Core
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-- Author : Michal Krepa
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--
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--------------------------------------------------------------------------------
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--
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-- File : DCT_TROM.VHD
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-- Created : Sun Aug 27 18:09 2006
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--
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--------------------------------------------------------------------------------
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--
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-- Description : ROM for DCT quantizer matrix
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use ieee.numeric_std.all;
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entity DCT_TROM is
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generic
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(
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ROMADDR_W : INTEGER := 9;
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ROMDATA_W : INTEGER := 8
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);
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port(
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addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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clk : in STD_LOGIC;
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datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
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);
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end DCT_TROM;
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architecture RTL of DCT_TROM is
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type DCT_TROM_TYPE is array (0 to 2**ROMADDR_W-1)
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of INTEGER;
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constant rom : DCT_TROM_TYPE :=
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-- (
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-- 16,11,10,16,24,40,51,61,
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-- 12,12,14,19,26,58,60,55,
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-- 14,13,16,24,40,57,69,56,
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-- 14,17,22,29,51,87,80,62,
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-- 18,22,37,56,68,109,103,77,
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-- 24,35,55,64,81,104,113,92,
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-- 49,64,78,87,103,121,120,101,
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-- 72,92,95,98,112,100,103,99);
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(
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-280, 48, -20, 16, -26, 46, -42, 27,
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45, 12, -34, -31, 11, -1, 16, -44,
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-5, -63, -34, 36, 24, -27, 6, 1,
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-12, 12, -8, 34, 5, 2, -12, 5,
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22, -18, 15, 9, 12, -5, 1, -11,
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1, 10, 6, 12, -15, -11, -5, -10,
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5, -16, -4, 10, -1, -11, -5, -11,
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-9, 11, 5, -3, -14, 4, 0, 0,
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-213, -110, -78, 38, 32, 2, -1, -9,
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28, 62, -7, -7, 22, -11, 5, 7,
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85, -21, 33, -28, -37, 36, -11, 5,
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-34, -18, 2, -24, 8, -12, -11, -8,
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-13, 8, 39, -63, 27, 0, 1, -4,
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-32, -4, -8, 24, -22, 11, 20, -4,
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-12, 8, 43, 41, -16, -12, 4, -10,
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-11, 14, 15, 7, -11, 9, -32, 0,
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-225, 10, 25, 18, -30, 18, -14, 7,
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44, -13, -93, -7, 20, -7, 5, -11,
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-88, -53, 6, 36, 2, 1, 22, 2,
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-46, -10, 17, 23, 16, 32, -7, 8,
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66, 46, -10, -3, -17, 4, -5, -5,
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-51, -18, -9, 6, 37, 15, 23, -4,
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-21, 22, 44, 49, 25, 21, 1, -12,
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25, 12, -5, -2, -19, -8, -15, 0,
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390, -97, -41, -15, 20, 6, 0, 12,
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4, -62, 21, -5, -31, -7, -3, -20,
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-352, 44, 27, 36, 35, 6, 5, 10,
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33, 48, 48, 14, -8, 14, 10, -9,
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-95, 108, 5, 1, -11, -23, -20, 1,
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54, -7, -43, -32, -15, 3, 9, 3,
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-42, 57, -32, -19, -4, 6, 5, -3,
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23, -31, -22, -1, 19, 24, 22, 1,
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-14, 148, 70, 67, 54, 30, 2, -10,
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76, 20, 20, -39, 14, -10, -8, -11,
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-86, -65, -15, -33, -33, -38, -2, 10,
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61, 20, 50, 18, -15, -25, -23, 2,
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11, -3, 12, 12, 15, 8, -18, -5,
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-13, -14, -13, 16, 34, 15, -22, -18,
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-8, -13, -3, 11, 19, 26, 9, -5,
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1, 1, 2, -9, -11, 2, 7, 0,
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-317, -9, 63, 17, 10, -26, 1, -11,
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159, -41, -29, 42, -3, 21, 11, 1,
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-6, -13, -18, 9, -19, 5, 15, 7,
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-8, -9, -11, 16, -4, -1, -12, -3,
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1, 15, -1, 3, -13, -8, 5, -1,
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-9, 3, 2, 5, 7, -6, 12, -11,
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-3, 1, -6, 1, -5, -4, 9, 6,
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3, 7, 7, 3, -3, -5, -2, 0,
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-404, 148, 70, 67, 54, 30, 2, -10,
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76, 20, 20, -39, 14, -10, -8, -11,
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-86, -65, -15, -33, -33, -38, -2, 10,
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61, 20, 50, 18, -15, -25, -23, 2,
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11, -3, 12, 12, 15, 8, -18, -5,
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-13, -14, -13, 16, 34, 15, -22, -18,
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-8, -13, -3, 11, 19, 26, 9, -5,
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1, 1, 2, -9, -11, 2, 7, 0,
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-404, 148, 70, 67, 54, 30, 2, -10,
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76, 20, 20, -39, 14, -10, -8, -11,
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-86, -65, -15, -33, -33, -38, -2, 10,
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61, 20, 50, 18, -15, -25, -23, 2,
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11, -3, 12, 12, 15, 8, -18, -5,
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-13, -14, -13, 16, 34, 15, -22, -18,
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-8, -13, -3, 11, 19, 26, 9, -5,
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1, 1, 2, -9, -11, 2, 7, 0
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);
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signal addr_reg : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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begin
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datao <= STD_LOGIC_VECTOR(TO_SIGNED( rom( TO_INTEGER(UNSIGNED(addr_reg)) ), ROMDATA_W));
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process(clk)
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begin
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if clk = '1' and clk'event then
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addr_reg <= addr;
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end if;
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end process;
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end RTL;
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