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---------------------------------------------------------------------
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-- TITLE: Bus Multiplexer / Signal Router
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 2/8/01
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-- FILENAME: bus_mux.vhd
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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--    Software 'as is' without warranty.  Author liable for nothing.
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-- DESCRIPTION:
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--    This entity is the main signal router.
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--    It multiplexes signals from multiple sources to the correct location.
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--    The outputs are as follows:
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--       a_bus        : goes to the ALU
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--       b_bus        : goes to the ALU
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--       reg_dest_out : goes to the register bank
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--       take_branch  : goes to pc_next
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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entity bus_mux is
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   port(imm_in       : in  std_logic_vector(15 downto 0);
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        reg_source   : in  std_logic_vector(31 downto 0);
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        a_mux        : in  a_source_type;
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        a_out        : out std_logic_vector(31 downto 0);
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        reg_target   : in  std_logic_vector(31 downto 0);
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        b_mux        : in  b_source_type;
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        b_out        : out std_logic_vector(31 downto 0);
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        c_bus        : in  std_logic_vector(31 downto 0);
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        c_memory     : in  std_logic_vector(31 downto 0);
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        c_pc         : in  std_logic_vector(31 downto 2);
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        c_pc_plus4   : in  std_logic_vector(31 downto 2);
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        c_mux        : in  c_source_type;
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        reg_dest_out : out std_logic_vector(31 downto 0);
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        branch_func  : in  branch_function_type;
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        take_branch  : out std_logic);
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end; --entity bus_mux
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architecture logic of bus_mux is
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begin
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--Determine value of a_bus
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amux: process(reg_source, imm_in, a_mux, c_pc)
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begin
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   case a_mux is
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   when A_FROM_REG_SOURCE =>
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      a_out <= reg_source;
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   when A_FROM_IMM10_6 =>
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      a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
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   when A_FROM_PC =>
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      a_out <= c_pc & "00";
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   when others =>
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      a_out <= c_pc & "00";
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   end case;
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end process;
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--Determine value of b_bus
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bmux: process(reg_target, imm_in, b_mux)
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begin
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   case b_mux is
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   when B_FROM_REG_TARGET =>
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      b_out <= reg_target;
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   when B_FROM_IMM =>
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      b_out <= ZERO(31 downto 16) & imm_in;
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   when B_FROM_SIGNED_IMM =>
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      if imm_in(15) = '0' then
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         b_out(31 downto 16) <= ZERO(31 downto 16);
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      else
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         b_out(31 downto 16) <= "1111111111111111";
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      end if;
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      b_out(15 downto 0) <= imm_in;
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   when B_FROM_IMMX4 =>
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      if imm_in(15) = '0' then
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         b_out(31 downto 18) <= "00000000000000";
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      else
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         b_out(31 downto 18) <= "11111111111111";
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      end if;
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      b_out(17 downto 0) <= imm_in & "00";
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   when others =>
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      b_out <= reg_target;
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   end case;
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end process;
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--Determine value of c_bus
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cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
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begin
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   case c_mux is
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   when C_FROM_ALU =>  -- | C_FROM_SHIFT | C_FROM_MULT =>
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      reg_dest_out <= c_bus;
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   when C_FROM_MEMORY =>
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      reg_dest_out <= c_memory;
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   when C_FROM_PC =>
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      reg_dest_out <= c_pc(31 downto 2) & "00";
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   when C_FROM_PC_PLUS4 =>
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      reg_dest_out <= c_pc_plus4 & "00";
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   when C_FROM_IMM_SHIFT16 =>
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      reg_dest_out <= imm_in & ZERO(15 downto 0);
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   when others =>
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      reg_dest_out <= c_bus;
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   end case;
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end process;
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--Determine value of take_branch
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pc_mux: process(branch_func, reg_source, reg_target)
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   variable is_equal : std_logic;
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begin
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   if reg_source = reg_target then
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      is_equal := '1';
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   else
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      is_equal := '0';
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   end if;
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   case branch_func is
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   when BRANCH_LTZ =>
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      take_branch <= reg_source(31);
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   when BRANCH_LEZ =>
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      take_branch <= reg_source(31) or is_equal;
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   when BRANCH_EQ =>
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      take_branch <= is_equal;
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   when BRANCH_NE =>
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      take_branch <= not is_equal;
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   when BRANCH_GEZ =>
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      take_branch <= not reg_source(31);
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   when BRANCH_GTZ =>
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      take_branch <= not reg_source(31) and not is_equal;
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   when BRANCH_YES =>
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      take_branch <= '1';
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   when others =>
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      take_branch <= '0';
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   end case;
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end process;
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end; --architecture logic

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