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[/] [mlite/] [trunk/] [vhdl/] [mem_ctrl.vhd] - Blame information for rev 350

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---------------------------------------------------------------------
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-- TITLE: Memory Controller
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 1/31/01
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-- FILENAME: mem_ctrl.vhd
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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--    Software 'as is' without warranty.  Author liable for nothing.
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-- DESCRIPTION:
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--    Memory controller for the Plasma CPU.
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--    Supports Big or Little Endian mode.
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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entity mem_ctrl is
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   port(clk          : in std_logic;
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        reset_in     : in std_logic;
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        pause_in     : in std_logic;
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        nullify_op   : in std_logic;
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        address_pc   : in std_logic_vector(31 downto 2);
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        opcode_out   : out std_logic_vector(31 downto 0);
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        address_in   : in std_logic_vector(31 downto 0);
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        mem_source   : in mem_source_type;
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        data_write   : in std_logic_vector(31 downto 0);
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        data_read    : out std_logic_vector(31 downto 0);
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        pause_out    : out std_logic;
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        address_next : out std_logic_vector(31 downto 2);
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        byte_we_next : out std_logic_vector(3 downto 0);
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        address      : out std_logic_vector(31 downto 2);
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        byte_we      : out std_logic_vector(3 downto 0);
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        data_w       : out std_logic_vector(31 downto 0);
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        data_r       : in std_logic_vector(31 downto 0));
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end; --entity mem_ctrl
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architecture logic of mem_ctrl is
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   --"00" = big_endian; "11" = little_endian
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   constant ENDIAN_MODE   : std_logic_vector(1 downto 0) := "00";
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   signal opcode_reg      : std_logic_vector(31 downto 0);
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   signal next_opcode_reg : std_logic_vector(31 downto 0);
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   signal address_reg     : std_logic_vector(31 downto 2);
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   signal byte_we_reg     : std_logic_vector(3 downto 0);
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   signal mem_state_reg   : std_logic;
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   constant STATE_ADDR    : std_logic := '0';
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   constant STATE_ACCESS  : std_logic := '1';
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begin
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mem_proc: process(clk, reset_in, pause_in, nullify_op,
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                  address_pc, address_in, mem_source, data_write,
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                  data_r, opcode_reg, next_opcode_reg, mem_state_reg,
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                  address_reg, byte_we_reg)
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   variable address_var    : std_logic_vector(31 downto 2);
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   variable data_read_var  : std_logic_vector(31 downto 0);
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   variable data_write_var : std_logic_vector(31 downto 0);
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   variable opcode_next    : std_logic_vector(31 downto 0);
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   variable byte_we_var    : std_logic_vector(3 downto 0);
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   variable mem_state_next : std_logic;
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   variable pause_var      : std_logic;
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   variable bits           : std_logic_vector(1 downto 0);
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begin
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   byte_we_var := "0000";
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   pause_var := '0';
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   data_read_var := ZERO;
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   data_write_var := ZERO;
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   mem_state_next := mem_state_reg;
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   opcode_next := opcode_reg;
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   case mem_source is
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   when MEM_READ32 =>
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      data_read_var := data_r;
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   when MEM_READ16 | MEM_READ16S =>
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      if address_in(1) = ENDIAN_MODE(1) then
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         data_read_var(15 downto 0) := data_r(31 downto 16);
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      else
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         data_read_var(15 downto 0) := data_r(15 downto 0);
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      end if;
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      if mem_source = MEM_READ16 or data_read_var(15) = '0' then
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         data_read_var(31 downto 16) := ZERO(31 downto 16);
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      else
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         data_read_var(31 downto 16) := ONES(31 downto 16);
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      end if;
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   when MEM_READ8 | MEM_READ8S =>
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      bits := address_in(1 downto 0) xor ENDIAN_MODE;
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      case bits is
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      when "00" => data_read_var(7 downto 0) := data_r(31 downto 24);
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      when "01" => data_read_var(7 downto 0) := data_r(23 downto 16);
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      when "10" => data_read_var(7 downto 0) := data_r(15 downto 8);
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      when others => data_read_var(7 downto 0) := data_r(7 downto 0);
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      end case;
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      if mem_source = MEM_READ8 or data_read_var(7) = '0' then
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         data_read_var(31 downto 8) := ZERO(31 downto 8);
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      else
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         data_read_var(31 downto 8) := ONES(31 downto 8);
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      end if;
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   when MEM_WRITE32 =>
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      data_write_var := data_write;
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      byte_we_var := "1111";
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   when MEM_WRITE16 =>
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      data_write_var := data_write(15 downto 0) & data_write(15 downto 0);
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      if address_in(1) = ENDIAN_MODE(1) then
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         byte_we_var := "1100";
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      else
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         byte_we_var := "0011";
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      end if;
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   when MEM_WRITE8 =>
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      data_write_var := data_write(7 downto 0) & data_write(7 downto 0) &
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                  data_write(7 downto 0) & data_write(7 downto 0);
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      bits := address_in(1 downto 0) xor ENDIAN_MODE;
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      case bits is
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      when "00" =>
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         byte_we_var := "1000";
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      when "01" =>
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         byte_we_var := "0100";
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      when "10" =>
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         byte_we_var := "0010";
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      when others =>
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         byte_we_var := "0001";
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      end case;
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   when others =>
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   end case;
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   if mem_source = MEM_FETCH then --opcode fetch
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      address_var := address_pc;
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      opcode_next := data_r;
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      mem_state_next := STATE_ADDR;
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   else
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      if mem_state_reg = STATE_ADDR then
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         if pause_in = '0' then
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            address_var := address_in(31 downto 2);
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            mem_state_next := STATE_ACCESS;
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            pause_var := '1';
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         else
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            address_var := address_pc;
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            byte_we_var := "0000";
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         end if;
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      else  --STATE_ACCESS
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         if pause_in = '0' then
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            address_var := address_pc;
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            opcode_next := next_opcode_reg;
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            mem_state_next := STATE_ADDR;
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            byte_we_var := "0000";
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         else
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            address_var := address_in(31 downto 2);
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            byte_we_var := "0000";
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         end if;
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      end if;
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   end if;
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   if nullify_op = '1' and pause_in = '0' then
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      opcode_next := ZERO;  --NOP after beql
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   end if;
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   if reset_in = '1' then
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      mem_state_reg <= STATE_ADDR;
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      opcode_reg <= ZERO;
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      next_opcode_reg <= ZERO;
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      address_reg <= ZERO(31 downto 2);
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      byte_we_reg <= "0000";
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   elsif rising_edge(clk) then
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      if pause_in = '0' then
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         address_reg <= address_var;
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         byte_we_reg <= byte_we_var;
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         mem_state_reg <= mem_state_next;
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         opcode_reg <= opcode_next;
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         if mem_state_reg = STATE_ADDR then
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            next_opcode_reg <= data_r;
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         end if;
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      end if;
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   end if;
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   opcode_out <= opcode_reg;
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   data_read <= data_read_var;
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   pause_out <= pause_var;
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   address_next <= address_var;
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   byte_we_next <= byte_we_var;
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   address <= address_reg;
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   byte_we <= byte_we_reg;
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   data_w <= data_write_var;
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end process; --data_proc
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end; --architecture logic

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