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---------------------------------------------------------------------
-- TITLE: Multiplication and Division Unit
-- AUTHORS: Steve Rhoads (rhoadss@yahoo.com)
--          Matthias Gruenewald
-- DATE CREATED: 1/31/01
-- FILENAME: mult.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
--    Software 'as is' without warranty.  Author liable for nothing.
-- DESCRIPTION:
--    Implements the multiplication and division unit.
--    Division takes 32 clock cycles.
--    Multiplication normally takes 16 clock cycles.
--    if b <= 0xffff then mult in 8 cycles. 
--    if b <= 0xff then mult in 4 cycles. 
--
-- For multiplication set reg_b = 0x00000000 & b.  The 64-bit result
-- will be in reg_b.  The lower bits of reg_b contain the upper 
-- bits of b that have not yet been multiplied.  For 16 clock cycles
-- shift reg_b two bits to the right.  Use the lowest two bits of reg_b 
-- to multiply by two bits at a time and add the result to the upper
-- 32-bits of reg_b (using C syntax):
--    reg_b = (reg_b >> 2) + (((reg_b & 3) * reg_a) << 32);
--
-- For division set reg_b = '0' & b & 30_ZEROS.  The answer will be
-- in answer_reg and the remainder in reg_a.  For 32 clock cycles
-- (using C syntax):
--    answer_reg = (answer_reg << 1);
--    if (reg_a >= reg_b) {
--       answer_reg += 1;
--       reg_a -= reg_b;
--    }
--    reg_b = reg_b >> 1;
---------------------------------------------------------------------
--library ieee, MLITE_LIB;
--use MLITE_LIB.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.mlite_pack.all;
 
entity mult is
   generic(adder_type : string := "GENERIC";
           mult_type  : string := "GENERIC");
   port(clk       : in std_logic;
        reset_in  : in std_logic;
        a, b      : in std_logic_vector(31 downto 0);
        mult_func : in mult_function_type;
        c_mult    : out std_logic_vector(31 downto 0);
        pause_out : out std_logic);
end; --entity mult
 
architecture logic of mult is
 
   signal do_mult_reg   : std_logic;
   signal do_signed_reg : std_logic;
   signal count_reg     : std_logic_vector(5 downto 0);
   signal reg_a         : std_logic_vector(31 downto 0);
   signal reg_b         : std_logic_vector(63 downto 0);
   signal answer_reg    : std_logic_vector(31 downto 0);
   signal aa, bb        : std_logic_vector(33 downto 0);
   signal sum           : std_logic_vector(33 downto 0);
   signal reg_a_times3  : std_logic_vector(33 downto 0);
   signal sign_extend_sig : std_logic;
   signal a_neg_sig     : std_logic_vector(31 downto 0);
   signal b_neg_sig     : std_logic_vector(31 downto 0);
 
   --Used in Xilinx tri-state area optimizated version
   signal a_temp_sig    : std_logic_vector(31 downto 0);
   signal b_temp_sig    : std_logic_vector(63 downto 0);
   signal a_msb, b_msb  : std_logic;
   signal answer_temp_sig : std_logic_vector(31 downto 0);
   signal aa_select     : std_logic_vector(3 downto 0);
   signal bb_select     : std_logic_vector(1 downto 0);
   signal a_select      : std_logic_vector(4 downto 0);
   signal b_select      : std_logic_vector(11 downto 0);
   signal answer_select : std_logic_vector(2 downto 0);
 
begin
 
   --sum = aa + bb
   generic_adder: if adder_type = "GENERIC" generate
      sum <= (aa + bb) when do_mult_reg = '1' else
             (aa - bb);
   end generate; --generic_adder
 
   --For Altera: sum = aa + bb
   lpm_adder: if adder_type = "ALTERA" generate
      lpm_add_sub_component : lpm_add_sub
        GENERIC MAP (
          lpm_width => 34,
          lpm_direction => "UNUSED",
          lpm_type => "LPM_ADD_SUB",
          lpm_hint => "ONE_INPUT_IS_CONSTANT=NO"
          )
        PORT MAP (
          dataa   => aa,
          add_sub => do_mult_reg,
          datab   => bb,
          result  => sum
          );
   end generate; --lpm_adder
 
   -- Negate signals
   a_neg_sig <= bv_negate(a);
   b_neg_sig <= bv_negate(b);
   sign_extend_sig <= do_signed_reg and do_mult_reg;
 
   -- Result
   c_mult <= reg_b(31 downto 0)  when mult_func = MULT_READ_LO else
             reg_b(63 downto 32) when mult_func = MULT_READ_HI else
             ZERO;
 
 
   GENERIC_MULT: if MULT_TYPE = "GENERIC" generate
 
   --multiplication/division unit
   mult_proc: process(clk, reset_in, a, b, mult_func,
                      do_mult_reg, do_signed_reg, count_reg,
                      reg_a, reg_b, answer_reg, sum, reg_a_times3)
      variable do_mult_temp   : std_logic;
      variable do_signed_temp : std_logic;
      variable count_temp     : std_logic_vector(5 downto 0);
      variable a_temp         : std_logic_vector(31 downto 0);
      variable b_temp         : std_logic_vector(63 downto 0);
      variable answer_temp    : std_logic_vector(31 downto 0);
      variable start          : std_logic;
      variable do_write       : std_logic;
      variable do_hi          : std_logic;
      variable sign_extend    : std_logic;
 
   begin
      do_mult_temp   := do_mult_reg;
      do_signed_temp := do_signed_reg;
      count_temp     := count_reg;
      a_temp         := reg_a;
      b_temp         := reg_b;
      answer_temp    := answer_reg;
      sign_extend    := do_signed_reg and do_mult_reg;
      start          := '0';
      do_write       := '0';
      do_hi          := '0';
 
      case mult_func is
         when MULT_READ_LO =>
         when MULT_READ_HI =>
            do_hi := '1';
         when MULT_WRITE_LO =>
            do_write := '1';
         when MULT_WRITE_HI =>
            do_write := '1';
            do_hi := '1';
         when MULT_MULT =>
            start := '1';
            do_mult_temp := '1';
            do_signed_temp := '0';
         when MULT_SIGNED_MULT =>
            start := '1';
            do_mult_temp := '1';
            do_signed_temp := '1';
         when MULT_DIVIDE =>
            start := '1';
            do_mult_temp := '0';
            do_signed_temp := '0';
         when MULT_SIGNED_DIVIDE =>
            start := '1';
            do_mult_temp := '0';
            do_signed_temp := a(31) xor b(31);
         when others =>
      end case;
 
      if start = '1' then
         count_temp := "000000";
         answer_temp := ZERO;
         if do_mult_temp = '0' then
            b_temp(63) := '0';
            if mult_func /= MULT_SIGNED_DIVIDE or a(31) = '0' then
               a_temp := a;
            else
               a_temp := a_neg_sig;
            end if;
            if mult_func /= MULT_SIGNED_DIVIDE or b(31) = '0' then
               b_temp(62 downto 31) := b;
            else
               b_temp(62 downto 31) := b_neg_sig;
            end if;
            b_temp(30 downto 0) := ZERO(30 downto 0);
         else --multiply
            if do_signed_temp = '0' or b(31) = '0' then
               a_temp := a;
               b_temp(31 downto 0) := b;
            else
               a_temp := a_neg_sig;
               b_temp(31 downto 0) := b_neg_sig;
            end if;
            b_temp(63 downto 32) := ZERO;
         end if;
      elsif do_write = '1' then
         if do_hi = '0' then
            b_temp(31 downto 0) := a;
         else
            b_temp(63 downto 32) := a;
         end if;
      end if;
 
      if do_mult_reg = '0' then  --division
         aa <= (reg_a(31) and sign_extend) & (reg_a(31) and sign_extend) & reg_a;
         bb <= reg_b(33 downto 0);
      else                       --multiplication two-bits at a time
         case reg_b(1 downto 0) is
            when "00" =>
               aa <= "00" & ZERO;
            when "01" =>
               aa <= (reg_a(31) and sign_extend) & (reg_a(31) and sign_extend) & reg_a;
            when "10" =>
               aa <= (reg_a(31) and sign_extend) & reg_a & '0';
            when others =>
               aa <= reg_a_times3;
         end case;
         bb <= (reg_b(63) and sign_extend) & (reg_b(63) and sign_extend) & reg_b(63 downto 32);
      end if;
 
      if count_reg(5) = '0' and start = '0' then
         count_temp := bv_inc6(count_reg);
         if do_mult_reg = '0' then          --division
            answer_temp(31 downto 1) := answer_reg(30 downto 0);
            if reg_b(63 downto 32) = ZERO and sum(32) = '0' then
               a_temp := sum(31 downto 0);  --aa=aa-bb;
               answer_temp(0) := '1';
            else
               answer_temp(0) := '0';
            end if;
            if count_reg /= "011111" then
               b_temp(62 downto 0) := reg_b(63 downto 1);
            else                            --done with divide
               b_temp(63 downto 32) := a_temp;
               if do_signed_reg = '0' then
                  b_temp(31 downto 0) := answer_temp;
               else
                  b_temp(31 downto 0) := bv_negate(answer_temp);
               end if;
            end if;
         else  -- mult_mode
            b_temp(63 downto 30) := sum;
            b_temp(29 downto 0) := reg_b(31 downto 2);
            if count_reg = "001000" and sign_extend = '0' and   --early stop
               reg_b(15 downto 0) = ZERO(15 downto 0) then
               count_temp := "111111";
               b_temp(31 downto 0) := reg_b(47 downto 16);
            end if;
            if count_reg = "000100" and sign_extend = '0' and   --early stop
               reg_b(23 downto 0) = ZERO(23 downto 0) then
               count_temp := "111111";
               b_temp(31 downto 0) := reg_b(55 downto 24);
            end if;
            count_temp(5) := count_temp(4);
         end if;
      end if;
 
      if reset_in = '1' then
         do_mult_reg <= '0';
         do_signed_reg <= '0';
         count_reg <= "000000";
         reg_a <= ZERO;
         reg_b <= ZERO & ZERO;
         answer_reg <= ZERO;
         reg_a_times3 <= "00" & ZERO;
      elsif rising_edge(clk) then
         do_mult_reg <= do_mult_temp;
         do_signed_reg <= do_signed_temp;
         count_reg <= count_temp;
         reg_a <= a_temp;
         reg_b <= b_temp;
         answer_reg <= answer_temp;
         if start = '1' then
            reg_a_times3 <= ((a_temp(31) and do_signed_temp) & a_temp & '0') +
                            ((a_temp(31) and do_signed_temp) & (a_temp(31) and do_signed_temp) & a_temp);
         end if;
      end if;
 
      if count_reg(5) = '0' and mult_func /= mult_nothing and start = '0' then
         pause_out <= '1';
      else
         pause_out <= '0';
      end if;
 
   end process;
 
   --Only used in Xilinx tri-state area optimizated version
   a_temp_sig    <= ZERO;
   b_temp_sig    <= ZERO & ZERO;
   a_msb         <= '0';
   b_msb         <= '0';
   answer_temp_sig <= ZERO;
   aa_select     <= "0000";
   bb_select     <= "00";
   a_select      <= "00000";
   b_select      <= ZERO(11 downto 0);
   answer_select <= "000";
 
   end generate;
 
 
   AREA_OPTIMIZED_MULT: if MULT_TYPE="AREA_OPTIMIZED" generate
   --Xilinx Tristate size optimization by Matthias Gruenewald
 
   --multiplication/division unit
    mult_proc: process(a, b, clk, count_reg, do_mult_reg, do_signed_reg, mult_func, reg_b, sum)
      variable do_mult_temp   : std_logic;
      variable do_signed_temp : std_logic;
      variable count_temp     : std_logic_vector(5 downto 0);
      variable start          : std_logic;
      variable do_write       : std_logic;
      variable do_hi          : std_logic;
      variable sign_extend    : std_logic;
 
    begin
      do_mult_temp   := do_mult_reg;
      do_signed_temp := do_signed_reg;
      count_temp     := count_reg;
      sign_extend    := do_signed_reg and do_mult_reg;
      sign_extend_sig <= sign_extend;
      start          := '0';
      do_write       := '0';
      do_hi          := '0';
      a_select <= (others => '0');
      b_select <= (others => '0');
      aa_select <= (others => '0');
      bb_select <= (others => '0');
      answer_select <= (others => '0');
 
      case mult_func is
        when MULT_READ_LO =>
        when MULT_READ_HI =>
          do_hi := '1';
        when MULT_WRITE_LO =>
          do_write := '1';
        when MULT_WRITE_HI =>
          do_write := '1';
          do_hi := '1';
        when MULT_MULT =>
          start := '1';
          do_mult_temp := '1';
          do_signed_temp := '0';
        when MULT_SIGNED_MULT =>
          start := '1';
          do_mult_temp := '1';
          do_signed_temp := '1';
        when MULT_DIVIDE =>
          start := '1';
          do_mult_temp := '0';
          do_signed_temp := '0';
        when MULT_SIGNED_DIVIDE =>
          start := '1';
          do_mult_temp := '0';
          do_signed_temp := a(31) xor b(31);
        when others =>
      end case;
 
      if start = '1' then
        count_temp := "000000";
        answer_select(0)<='1';
        --answer_temp := ZERO;
        if do_mult_temp = '0' then
          --b_temp(63) := '0';
          if mult_func /= MULT_SIGNED_DIVIDE or a(31) = '0' then
            a_select(0) <= '1';
            --a_temp := a;
          else
            a_select(1) <= '1';
            --a_temp := a_neg;
          end if;
          if mult_func /= MULT_SIGNED_DIVIDE or b(31) = '0' then
            b_select(0) <= '1';
            --b_temp(62 downto 31) := b;
          else
            b_select(1) <= '1';
            --b_temp(62 downto 31) := b_neg;
          end if;
          --b_temp(30 downto 0) := ZERO(30 downto 0);
        else --multiply
          if do_signed_temp = '0' or b(31) = '0' then
            a_select(2) <= '1';
            --a_temp := a;
            b_select(2) <= '1';
            --b_temp(31 downto 0) := b;
          else
            a_select(3) <= '1';
            --a_temp := a_neg;
            b_select(3) <= '1';
            --b_temp(31 downto 0) := b_neg;
          end if;
          --b_temp(63 downto 32) := ZERO;
        end if;
      elsif do_write = '1' then
        if do_hi = '0' then
          b_select(4) <= '1';
          --b_temp(31 downto 0) := a;
        else
          b_select(5) <= '1';
          --b_temp(63 downto 32) := a;
        end if;
      end if;
 
      if do_mult_reg = '0' then  --division
        aa_select(0) <= '1';
        --aa <= (reg_a(31) and sign_extend) & (reg_a(31) and sign_extend) & reg_a;
        bb_select(0) <= '1';
        --bb <= reg_b(33 downto 0);
      else                       --multiplication two-bits at a time
        case reg_b(1 downto 0) is
          when "00" =>
            aa_select(1) <= '1';
            --aa <= "00" & ZERO;
          when "01" =>
            aa_select(2) <= '1';
            --aa <= (reg_a(31) and sign_extend) & (reg_a(31) and sign_extend) & reg_a;
          when "10" =>
            aa_select(3) <= '1';
            --aa <= (reg_a(31) and sign_extend) & reg_a & '0';
          when others =>
            --aa_select(4) <= '1';
            --aa <= reg_a_times3;
        end case;
        bb_select(1) <= '1';
        --bb <= (reg_b(63) and sign_extend) & (reg_b(63) and sign_extend) & reg_b(63 downto 32);
      end if;
 
      if count_reg(5) = '0' and start = '0' then
        count_temp := bv_inc6(count_reg);
        if do_mult_reg = '0' then          --division          
          --answer_temp(31 downto 1) := answer_reg(30 downto 0);
          if reg_b(63 downto 32) = ZERO and sum(32) = '0' then
            a_select(4) <= '1';
            --a_temp := sum(31 downto 0);  --aa=aa-bb;
            answer_select(1) <= '1';
            --answer_temp(0) := '1';
          else
            answer_select(2) <= '1';
            --answer_temp(0) := '0';
          end if;
          if count_reg /= "011111" then
            --b_temp(62 downto 0) := reg_b(63 downto 1);
            b_select(6) <= '1';
          else                            --done with divide
            --b_temp(63 downto 32) := a_temp;
            if do_signed_reg = '0' then
              b_select(7) <= '1';
              --b_temp(31 downto 0) := answer_temp;
            else
              b_select(8) <= '1';
              --b_temp(31 downto 0) := bv_negate(answer_temp);
            end if;
          end if;
        else  -- mult_mode
          b_select(9) <= '1';
          --b_temp(63 downto 30) := sum;
          --b_temp(29 downto 0) := reg_b(31 downto 2);
          if count_reg = "001000" and sign_extend = '0' and   --early stop
            reg_b(15 downto 0) = ZERO(15 downto 0) then
            count_temp := "111111";
            b_select(10) <= '1';
            --b_temp(31 downto 0) := reg_b(47 downto 16);
          end if;
          if count_reg = "000100" and sign_extend = '0' and   --early stop
            reg_b(23 downto 0) = ZERO(23 downto 0) then
            count_temp := "111111";
            b_select(11) <= '1';
            --b_temp(31 downto 0) := reg_b(55 downto 24);
          end if;
          count_temp(5) := count_temp(4);
        end if;
      end if;
 
      if reset_in = '1' then
         do_mult_reg <= '0';
         do_signed_reg <= '0';
         count_reg <= "000000";
         reg_a <= ZERO;
         reg_b <= ZERO & ZERO;
         answer_reg <= ZERO;
         reg_a_times3 <= "00" & ZERO;
      elsif rising_edge(clk) then
         do_mult_reg <= do_mult_temp;
         do_signed_reg <= do_signed_temp;
         count_reg <= count_temp;
         reg_a <= a_temp_sig;
         reg_b <= b_temp_sig;
         answer_reg <= answer_temp_sig;
         if start = '1' then
            reg_a_times3 <= ((a_temp_sig(31) and do_signed_temp) & a_temp_sig & '0') +
                            ((a_temp_sig(31) and do_signed_temp) & (a_temp_sig(31) and do_signed_temp) & a_temp_sig);
         end if;
      end if;
 
      if count_reg(5) = '0' and mult_func/= mult_nothing and start = '0' then
        pause_out <= '1';
      else
        pause_out <= '0';
      end if;
 
    end process;
 
 
    -- Arguments
    a_msb <= reg_a(31) and sign_extend_sig;
    aa <= a_msb & a_msb & reg_a when aa_select(0)='1' else
          "00" & ZERO           when aa_select(1)='1' else
          a_msb & a_msb & reg_a when aa_select(2)='1' else
          a_msb & reg_a & '0'   when aa_select(3)='1' else
          reg_a_times3;
 
    b_msb <= reg_b(63) and sign_extend_sig;
    bb <= reg_b(33 downto 0)                  when bb_select(0)='1' else (others => 'Z');
    bb <= b_msb & b_msb & reg_b(63 downto 32) when bb_select(1)='1' else (others => 'Z');
 
    -- Divide: Init
    a_temp_sig <= a                                   when a_select(0)='1' else (others => 'Z');
    a_temp_sig <= a_neg_sig                           when a_select(1)='1' else (others => 'Z');
    b_temp_sig <= '0' & b & ZERO(30 downto 0)         when b_select(0)='1' else (others => 'Z');
    b_temp_sig <= '0' & b_neg_sig & ZERO(30 downto 0) when b_select(1)='1' else (others => 'Z');
 
    -- Multiply: Init
    a_temp_sig <= a                when a_select(2)='1' else (others => 'Z');
    b_temp_sig <= ZERO & b         when b_select(2)='1' else (others => 'Z');
    a_temp_sig <= a_neg_sig        when a_select(3)='1' else (others => 'Z');
    b_temp_sig <= ZERO & b_neg_sig when b_select(3)='1' else (others => 'Z');
 
    -- Intermediate results
    b_temp_sig  <= reg_b(63 downto 32) & a when b_select(4)='1' else (others => 'Z');
    b_temp_sig  <= a & reg_b(31 downto 0)  when b_select(5)='1' else (others => 'Z');
 
    -- Divide: Operation
    a_temp_sig <= sum(31 downto 0)                        when a_select(4)='1'      else (others => 'Z');
    b_temp_sig <= reg_b(63) & reg_b(63 downto 1)          when b_select(6)='1'      else (others => 'Z');
    b_temp_sig <= a_temp_sig & answer_temp_sig            when b_select(7)='1'      else (others => 'Z');
    b_temp_sig <= a_temp_sig & bv_negate(answer_temp_sig) when b_select(8)='1'      else (others => 'Z');
 
    -- Multiply: Operation
    b_temp_sig <= sum & reg_b(31 downto 2)               when b_select(9)='1' and b_select(10)='0' and b_select(11)='0' else (others => 'Z');
    b_temp_sig <= sum(33 downto 2) & reg_b(47 downto 16) when b_select(10)='1'                                          else (others => 'Z');
    b_temp_sig <= sum(33 downto 2) & reg_b(55 downto 24) when b_select(11)='1'                                          else (others => 'Z');
 
    -- Default values
    a_temp_sig <= reg_a           when conv_integer(unsigned(a_select))=0 else (others => 'Z');
    b_temp_sig <= reg_b           when conv_integer(unsigned(b_select))=0 else (others => 'Z');
 
    -- Result
    answer_temp_sig <= ZERO                          when answer_select(0)='1' else
                       answer_reg(30 downto 0) & '1' when answer_select(1)='1' else
                       answer_reg(30 downto 0) & '0' when answer_select(2)='1' else
                       answer_reg;
 
  end generate;
 
end; --architecture logic
 

Line No.	Rev	Author	Line
1	2	rhoads	`---------------------------------------------------------------------`
2			`-- TITLE: Multiplication and Division Unit`
3	121	rhoads	`-- AUTHORS: Steve Rhoads (rhoadss@yahoo.com)`
4			`-- Matthias Gruenewald`
5	2	rhoads	`-- DATE CREATED: 1/31/01`
6			`-- FILENAME: mult.vhd`
7	43	rhoads	`-- PROJECT: Plasma CPU core`
8	2	rhoads	`-- COPYRIGHT: Software placed into the public domain by the author.`
9			`-- Software 'as is' without warranty. Author liable for nothing.`
10			`-- DESCRIPTION:`
11			`-- Implements the multiplication and division unit.`
12	90	rhoads	`-- Division takes 32 clock cycles.`
13			`-- Multiplication normally takes 16 clock cycles.`
14			`-- if b <= 0xffff then mult in 8 cycles.`
15			`-- if b <= 0xff then mult in 4 cycles.`
16	97	rhoads	`--`
17			`-- For multiplication set reg_b = 0x00000000 & b. The 64-bit result`
18			`-- will be in reg_b. The lower bits of reg_b contain the upper`
19			`-- bits of b that have not yet been multiplied. For 16 clock cycles`
20			`-- shift reg_b two bits to the right. Use the lowest two bits of reg_b`
21			`-- to multiply by two bits at a time and add the result to the upper`
22			`-- 32-bits of reg_b (using C syntax):`
23			`-- reg_b = (reg_b >> 2) + (((reg_b & 3) * reg_a) << 32);`
24			`--`
25			`-- For division set reg_b = '0' & b & 30_ZEROS. The answer will be`
26			`-- in answer_reg and the remainder in reg_a. For 32 clock cycles`
27			`-- (using C syntax):`
28			`-- answer_reg = (answer_reg << 1);`
29			`-- if (reg_a >= reg_b) {`
30			`-- answer_reg += 1;`
31			`-- reg_a -= reg_b;`
32			`-- }`
33			`-- reg_b = reg_b >> 1;`
34	2	rhoads	`---------------------------------------------------------------------`
35	121	rhoads	`--library ieee, MLITE_LIB;`
36			`--use MLITE_LIB.all;`
37	2	rhoads	`library ieee;`
38			`use ieee.std_logic_1164.all;`
39	90	rhoads	`use ieee.std_logic_unsigned.all;`
40	121	rhoads	`use IEEE.std_logic_arith.all;`
41	39	rhoads	`use work.mlite_pack.all;`
42	2	rhoads
43			`entity mult is`
44	117	rhoads	`generic(adder_type : string := "GENERIC";`
45			`mult_type : string := "GENERIC");`
46	2	rhoads	`port(clk : in std_logic;`
47	128	rhoads	`reset_in : in std_logic;`
48	2	rhoads	`a, b : in std_logic_vector(31 downto 0);`
49			`mult_func : in mult_function_type;`
50			`c_mult : out std_logic_vector(31 downto 0);`
51			`pause_out : out std_logic);`
52			`end; --entity mult`
53
54			`architecture logic of mult is`
55	121	rhoads
56	47	rhoads	`signal do_mult_reg : std_logic;`
57	2	rhoads	`signal do_signed_reg : std_logic;`
58			`signal count_reg : std_logic_vector(5 downto 0);`
59			`signal reg_a : std_logic_vector(31 downto 0);`
60			`signal reg_b : std_logic_vector(63 downto 0);`
61			`signal answer_reg : std_logic_vector(31 downto 0);`
62	90	rhoads	`signal aa, bb : std_logic_vector(33 downto 0);`
63			`signal sum : std_logic_vector(33 downto 0);`
64			`signal reg_a_times3 : std_logic_vector(33 downto 0);`
65	121	rhoads	`signal sign_extend_sig : std_logic;`
66	128	rhoads	`signal a_neg_sig : std_logic_vector(31 downto 0);`
67			`signal b_neg_sig : std_logic_vector(31 downto 0);`
68	121	rhoads
69			`--Used in Xilinx tri-state area optimizated version`
70	128	rhoads	`signal a_temp_sig : std_logic_vector(31 downto 0);`
71	121	rhoads	`signal b_temp_sig : std_logic_vector(63 downto 0);`
72			`signal a_msb, b_msb : std_logic;`
73			`signal answer_temp_sig : std_logic_vector(31 downto 0);`
74			`signal aa_select : std_logic_vector(3 downto 0);`
75			`signal bb_select : std_logic_vector(1 downto 0);`
76			`signal a_select : std_logic_vector(4 downto 0);`
77			`signal b_select : std_logic_vector(11 downto 0);`
78			`signal answer_select : std_logic_vector(2 downto 0);`
79	128	rhoads
80	2	rhoads	`begin`
81	121	rhoads
82			`--sum = aa + bb`
83			`generic_adder: if adder_type = "GENERIC" generate`
84			`sum <= (aa + bb) when do_mult_reg = '1' else`
85			`(aa - bb);`
86			`end generate; --generic_adder`
87	2	rhoads
88	121	rhoads	`--For Altera: sum = aa + bb`
89			`lpm_adder: if adder_type = "ALTERA" generate`
90			`lpm_add_sub_component : lpm_add_sub`
91			`GENERIC MAP (`
92			`lpm_width => 34,`
93			`lpm_direction => "UNUSED",`
94			`lpm_type => "LPM_ADD_SUB",`
95			`lpm_hint => "ONE_INPUT_IS_CONSTANT=NO"`
96			`)`
97			`PORT MAP (`
98			`dataa => aa,`
99			`add_sub => do_mult_reg,`
100			`datab => bb,`
101			`result => sum`
102			`);`
103			`end generate; --lpm_adder`
104	2	rhoads
105	121	rhoads	`-- Negate signals`
106			`a_neg_sig <= bv_negate(a);`
107			`b_neg_sig <= bv_negate(b);`
108			`sign_extend_sig <= do_signed_reg and do_mult_reg;`
109
110			`-- Result`
111	128	rhoads	`c_mult <= reg_b(31 downto 0) when mult_func = MULT_READ_LO else`
112			`reg_b(63 downto 32) when mult_func = MULT_READ_HI else`
113	121	rhoads	`ZERO;`
114	2	rhoads
115
116	128	rhoads	`GENERIC_MULT: if MULT_TYPE = "GENERIC" generate`
117	121	rhoads
118			`--multiplication/division unit`
119	128	rhoads	`mult_proc: process(clk, reset_in, a, b, mult_func,`
120	121	rhoads	`do_mult_reg, do_signed_reg, count_reg,`
121			`reg_a, reg_b, answer_reg, sum, reg_a_times3)`
122			`variable do_mult_temp : std_logic;`
123			`variable do_signed_temp : std_logic;`
124			`variable count_temp : std_logic_vector(5 downto 0);`
125			`variable a_temp : std_logic_vector(31 downto 0);`
126			`variable b_temp : std_logic_vector(63 downto 0);`
127			`variable answer_temp : std_logic_vector(31 downto 0);`
128			`variable start : std_logic;`
129			`variable do_write : std_logic;`
130			`variable do_hi : std_logic;`
131			`variable sign_extend : std_logic;`
132
133			`begin`
134			`do_mult_temp := do_mult_reg;`
135			`do_signed_temp := do_signed_reg;`
136			`count_temp := count_reg;`
137			`a_temp := reg_a;`
138			`b_temp := reg_b;`
139			`answer_temp := answer_reg;`
140			`sign_extend := do_signed_reg and do_mult_reg;`
141			`start := '0';`
142			`do_write := '0';`
143			`do_hi := '0';`
144
145			`case mult_func is`
146	128	rhoads	`when MULT_READ_LO =>`
147			`when MULT_READ_HI =>`
148	121	rhoads	`do_hi := '1';`
149	128	rhoads	`when MULT_WRITE_LO =>`
150	121	rhoads	`do_write := '1';`
151	128	rhoads	`when MULT_WRITE_HI =>`
152	121	rhoads	`do_write := '1';`
153			`do_hi := '1';`
154	128	rhoads	`when MULT_MULT =>`
155	121	rhoads	`start := '1';`
156			`do_mult_temp := '1';`
157			`do_signed_temp := '0';`
158	128	rhoads	`when MULT_SIGNED_MULT =>`
159	121	rhoads	`start := '1';`
160			`do_mult_temp := '1';`
161			`do_signed_temp := '1';`
162	128	rhoads	`when MULT_DIVIDE =>`
163	121	rhoads	`start := '1';`
164			`do_mult_temp := '0';`
165			`do_signed_temp := '0';`
166	128	rhoads	`when MULT_SIGNED_DIVIDE =>`
167	121	rhoads	`start := '1';`
168			`do_mult_temp := '0';`
169			`do_signed_temp := a(31) xor b(31);`
170			`when others =>`
171			`end case;`
172
173			`if start = '1' then`
174			`count_temp := "000000";`
175			`answer_temp := ZERO;`
176			`if do_mult_temp = '0' then`
177			`b_temp(63) := '0';`
178	128	rhoads	`if mult_func /= MULT_SIGNED_DIVIDE or a(31) = '0' then`
179	121	rhoads	`a_temp := a;`
180			`else`
181			`a_temp := a_neg_sig;`
182			`end if;`
183	128	rhoads	`if mult_func /= MULT_SIGNED_DIVIDE or b(31) = '0' then`
184	121	rhoads	`b_temp(62 downto 31) := b;`
185			`else`
186			`b_temp(62 downto 31) := b_neg_sig;`
187			`end if;`
188			`b_temp(30 downto 0) := ZERO(30 downto 0);`
189			`else --multiply`
190			`if do_signed_temp = '0' or b(31) = '0' then`
191			`a_temp := a;`
192			`b_temp(31 downto 0) := b;`
193			`else`
194			`a_temp := a_neg_sig;`
195			`b_temp(31 downto 0) := b_neg_sig;`
196			`end if;`
197			`b_temp(63 downto 32) := ZERO;`
198	99	rhoads	`end if;`
199	121	rhoads	`elsif do_write = '1' then`
200			`if do_hi = '0' then`
201			`b_temp(31 downto 0) := a;`
202	2	rhoads	`else`
203	121	rhoads	`b_temp(63 downto 32) := a;`
204	23	rhoads	`end if;`
205	121	rhoads	`end if;`
206
207			`if do_mult_reg = '0' then --division`
208			`aa <= (reg_a(31) and sign_extend) & (reg_a(31) and sign_extend) & reg_a;`
209			`bb <= reg_b(33 downto 0);`
210			`else --multiplication two-bits at a time`
211			`case reg_b(1 downto 0) is`
212			`when "00" =>`
213			`aa <= "00" & ZERO;`
214			`when "01" =>`
215			`aa <= (reg_a(31) and sign_extend) & (reg_a(31) and sign_extend) & reg_a;`
216			`when "10" =>`
217			`aa <= (reg_a(31) and sign_extend) & reg_a & '0';`
218			`when others =>`
219			`aa <= reg_a_times3;`
220			`end case;`
221			`bb <= (reg_b(63) and sign_extend) & (reg_b(63) and sign_extend) & reg_b(63 downto 32);`
222			`end if;`
223
224			`if count_reg(5) = '0' and start = '0' then`
225			`count_temp := bv_inc6(count_reg);`
226			`if do_mult_reg = '0' then --division`
227			`answer_temp(31 downto 1) := answer_reg(30 downto 0);`
228			`if reg_b(63 downto 32) = ZERO and sum(32) = '0' then`
229			`a_temp := sum(31 downto 0); --aa=aa-bb;`
230			`answer_temp(0) := '1';`
231			`else`
232			`answer_temp(0) := '0';`
233			`end if;`
234			`if count_reg /= "011111" then`
235			`b_temp(62 downto 0) := reg_b(63 downto 1);`
236			`else --done with divide`
237			`b_temp(63 downto 32) := a_temp;`
238			`if do_signed_reg = '0' then`
239			`b_temp(31 downto 0) := answer_temp;`
240			`else`
241			`b_temp(31 downto 0) := bv_negate(answer_temp);`
242			`end if;`
243			`end if;`
244			`else -- mult_mode`
245			`b_temp(63 downto 30) := sum;`
246			`b_temp(29 downto 0) := reg_b(31 downto 2);`
247			`if count_reg = "001000" and sign_extend = '0' and --early stop`
248			`reg_b(15 downto 0) = ZERO(15 downto 0) then`
249			`count_temp := "111111";`
250			`b_temp(31 downto 0) := reg_b(47 downto 16);`
251			`end if;`
252			`if count_reg = "000100" and sign_extend = '0' and --early stop`
253			`reg_b(23 downto 0) = ZERO(23 downto 0) then`
254			`count_temp := "111111";`
255			`b_temp(31 downto 0) := reg_b(55 downto 24);`
256			`end if;`
257			`count_temp(5) := count_temp(4);`
258	2	rhoads	`end if;`
259			`end if;`
260	121	rhoads
261	128	rhoads	`if reset_in = '1' then`
262			`do_mult_reg <= '0';`
263			`do_signed_reg <= '0';`
264			`count_reg <= "000000";`
265			`reg_a <= ZERO;`
266			`reg_b <= ZERO & ZERO;`
267			`answer_reg <= ZERO;`
268			`reg_a_times3 <= "00" & ZERO;`
269			`elsif rising_edge(clk) then`
270	121	rhoads	`do_mult_reg <= do_mult_temp;`
271			`do_signed_reg <= do_signed_temp;`
272			`count_reg <= count_temp;`
273			`reg_a <= a_temp;`
274			`reg_b <= b_temp;`
275			`answer_reg <= answer_temp;`
276			`if start = '1' then`
277			`reg_a_times3 <= ((a_temp(31) and do_signed_temp) & a_temp & '0') +`
278			`((a_temp(31) and do_signed_temp) & (a_temp(31) and do_signed_temp) & a_temp);`
279			`end if;`
280			`end if;`
281
282			`if count_reg(5) = '0' and mult_func /= mult_nothing and start = '0' then`
283			`pause_out <= '1';`
284	2	rhoads	`else`
285	121	rhoads	`pause_out <= '0';`
286	2	rhoads	`end if;`
287	121	rhoads
288			`end process;`
289	2	rhoads
290	128	rhoads	`--Only used in Xilinx tri-state area optimizated version`
291			`a_temp_sig <= ZERO;`
292			`b_temp_sig <= ZERO & ZERO;`
293			`a_msb <= '0';`
294			`b_msb <= '0';`
295			`answer_temp_sig <= ZERO;`
296			`aa_select <= "0000";`
297			`bb_select <= "00";`
298			`a_select <= "00000";`
299			`b_select <= ZERO(11 downto 0);`
300			`answer_select <= "000";`
301
302	121	rhoads	`end generate;`
303
304
305			`AREA_OPTIMIZED_MULT: if MULT_TYPE="AREA_OPTIMIZED" generate`
306			`--Xilinx Tristate size optimization by Matthias Gruenewald`
307
308			`--multiplication/division unit`
309			`mult_proc: process(a, b, clk, count_reg, do_mult_reg, do_signed_reg, mult_func, reg_b, sum)`
310			`variable do_mult_temp : std_logic;`
311			`variable do_signed_temp : std_logic;`
312			`variable count_temp : std_logic_vector(5 downto 0);`
313			`variable start : std_logic;`
314			`variable do_write : std_logic;`
315			`variable do_hi : std_logic;`
316			`variable sign_extend : std_logic;`
317
318			`begin`
319			`do_mult_temp := do_mult_reg;`
320			`do_signed_temp := do_signed_reg;`
321			`count_temp := count_reg;`
322			`sign_extend := do_signed_reg and do_mult_reg;`
323			`sign_extend_sig <= sign_extend;`
324			`start := '0';`
325			`do_write := '0';`
326			`do_hi := '0';`
327			`a_select <= (others => '0');`
328			`b_select <= (others => '0');`
329			`aa_select <= (others => '0');`
330			`bb_select <= (others => '0');`
331			`answer_select <= (others => '0');`
332
333			`case mult_func is`
334	128	rhoads	`when MULT_READ_LO =>`
335			`when MULT_READ_HI =>`
336	121	rhoads	`do_hi := '1';`
337	128	rhoads	`when MULT_WRITE_LO =>`
338	121	rhoads	`do_write := '1';`
339	128	rhoads	`when MULT_WRITE_HI =>`
340	121	rhoads	`do_write := '1';`
341			`do_hi := '1';`
342	128	rhoads	`when MULT_MULT =>`
343	121	rhoads	`start := '1';`
344			`do_mult_temp := '1';`
345			`do_signed_temp := '0';`
346	128	rhoads	`when MULT_SIGNED_MULT =>`
347	121	rhoads	`start := '1';`
348			`do_mult_temp := '1';`
349			`do_signed_temp := '1';`
350	128	rhoads	`when MULT_DIVIDE =>`
351	121	rhoads	`start := '1';`
352			`do_mult_temp := '0';`
353			`do_signed_temp := '0';`
354	128	rhoads	`when MULT_SIGNED_DIVIDE =>`
355	121	rhoads	`start := '1';`
356			`do_mult_temp := '0';`
357			`do_signed_temp := a(31) xor b(31);`
358			`when others =>`
359	90	rhoads	`end case;`
360	2	rhoads
361	121	rhoads	`if start = '1' then`
362			`count_temp := "000000";`
363			`answer_select(0)<='1';`
364			`--answer_temp := ZERO;`
365			`if do_mult_temp = '0' then`
366			`--b_temp(63) := '0';`
367	128	rhoads	`if mult_func /= MULT_SIGNED_DIVIDE or a(31) = '0' then`
368	121	rhoads	`a_select(0) <= '1';`
369			`--a_temp := a;`
370			`else`
371			`a_select(1) <= '1';`
372			`--a_temp := a_neg;`
373			`end if;`
374	128	rhoads	`if mult_func /= MULT_SIGNED_DIVIDE or b(31) = '0' then`
375	121	rhoads	`b_select(0) <= '1';`
376			`--b_temp(62 downto 31) := b;`
377			`else`
378			`b_select(1) <= '1';`
379			`--b_temp(62 downto 31) := b_neg;`
380			`end if;`
381			`--b_temp(30 downto 0) := ZERO(30 downto 0);`
382			`else --multiply`
383			`if do_signed_temp = '0' or b(31) = '0' then`
384			`a_select(2) <= '1';`
385			`--a_temp := a;`
386			`b_select(2) <= '1';`
387			`--b_temp(31 downto 0) := b;`
388			`else`
389			`a_select(3) <= '1';`
390			`--a_temp := a_neg;`
391			`b_select(3) <= '1';`
392			`--b_temp(31 downto 0) := b_neg;`
393			`end if;`
394			`--b_temp(63 downto 32) := ZERO;`
395			`end if;`
396			`elsif do_write = '1' then`
397			`if do_hi = '0' then`
398			`b_select(4) <= '1';`
399			`--b_temp(31 downto 0) := a;`
400			`else`
401			`b_select(5) <= '1';`
402			`--b_temp(63 downto 32) := a;`
403			`end if;`
404			`end if;`
405
406			`if do_mult_reg = '0' then --division`
407			`aa_select(0) <= '1';`
408			`--aa <= (reg_a(31) and sign_extend) & (reg_a(31) and sign_extend) & reg_a;`
409			`bb_select(0) <= '1';`
410			`--bb <= reg_b(33 downto 0);`
411			`else --multiplication two-bits at a time`
412			`case reg_b(1 downto 0) is`
413			`when "00" =>`
414			`aa_select(1) <= '1';`
415			`--aa <= "00" & ZERO;`
416			`when "01" =>`
417			`aa_select(2) <= '1';`
418			`--aa <= (reg_a(31) and sign_extend) & (reg_a(31) and sign_extend) & reg_a;`
419			`when "10" =>`
420			`aa_select(3) <= '1';`
421			`--aa <= (reg_a(31) and sign_extend) & reg_a & '0';`
422			`when others =>`
423			`--aa_select(4) <= '1';`
424			`--aa <= reg_a_times3;`
425			`end case;`
426			`bb_select(1) <= '1';`
427			`--bb <= (reg_b(63) and sign_extend) & (reg_b(63) and sign_extend) & reg_b(63 downto 32);`
428			`end if;`
429
430			`if count_reg(5) = '0' and start = '0' then`
431			`count_temp := bv_inc6(count_reg);`
432			`if do_mult_reg = '0' then --division`
433			`--answer_temp(31 downto 1) := answer_reg(30 downto 0);`
434			`if reg_b(63 downto 32) = ZERO and sum(32) = '0' then`
435			`a_select(4) <= '1';`
436			`--a_temp := sum(31 downto 0); --aa=aa-bb;`
437			`answer_select(1) <= '1';`
438			`--answer_temp(0) := '1';`
439			`else`
440			`answer_select(2) <= '1';`
441			`--answer_temp(0) := '0';`
442			`end if;`
443			`if count_reg /= "011111" then`
444			`--b_temp(62 downto 0) := reg_b(63 downto 1);`
445			`b_select(6) <= '1';`
446			`else --done with divide`
447			`--b_temp(63 downto 32) := a_temp;`
448	23	rhoads	`if do_signed_reg = '0' then`
449	121	rhoads	`b_select(7) <= '1';`
450			`--b_temp(31 downto 0) := answer_temp;`
451	23	rhoads	`else`
452	121	rhoads	`b_select(8) <= '1';`
453			`--b_temp(31 downto 0) := bv_negate(answer_temp);`
454	23	rhoads	`end if;`
455	121	rhoads	`end if;`
456			`else -- mult_mode`
457			`b_select(9) <= '1';`
458			`--b_temp(63 downto 30) := sum;`
459			`--b_temp(29 downto 0) := reg_b(31 downto 2);`
460			`if count_reg = "001000" and sign_extend = '0' and --early stop`
461			`reg_b(15 downto 0) = ZERO(15 downto 0) then`
462	2	rhoads	`count_temp := "111111";`
463	121	rhoads	`b_select(10) <= '1';`
464			`--b_temp(31 downto 0) := reg_b(47 downto 16);`
465			`end if;`
466			`if count_reg = "000100" and sign_extend = '0' and --early stop`
467			`reg_b(23 downto 0) = ZERO(23 downto 0) then`
468	7	rhoads	`count_temp := "111111";`
469	121	rhoads	`b_select(11) <= '1';`
470			`--b_temp(31 downto 0) := reg_b(55 downto 24);`
471			`end if;`
472			`count_temp(5) := count_temp(4);`
473			`end if;`
474	2	rhoads	`end if;`
475
476	128	rhoads	`if reset_in = '1' then`
477			`do_mult_reg <= '0';`
478			`do_signed_reg <= '0';`
479			`count_reg <= "000000";`
480			`reg_a <= ZERO;`
481			`reg_b <= ZERO & ZERO;`
482			`answer_reg <= ZERO;`
483			`reg_a_times3 <= "00" & ZERO;`
484			`elsif rising_edge(clk) then`
485			`do_mult_reg <= do_mult_temp;`
486			`do_signed_reg <= do_signed_temp;`
487			`count_reg <= count_temp;`
488			`reg_a <= a_temp_sig;`
489			`reg_b <= b_temp_sig;`
490			`answer_reg <= answer_temp_sig;`
491			`if start = '1' then`
492			`reg_a_times3 <= ((a_temp_sig(31) and do_signed_temp) & a_temp_sig & '0') +`
493			`((a_temp_sig(31) and do_signed_temp) & (a_temp_sig(31) and do_signed_temp) & a_temp_sig);`
494			`end if;`
495	90	rhoads	`end if;`
496	2	rhoads
497	121	rhoads	`if count_reg(5) = '0' and mult_func/= mult_nothing and start = '0' then`
498			`pause_out <= '1';`
499			`else`
500			`pause_out <= '0';`

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