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[/] [mlite/] [trunk/] [vhdl/] [plasma.vhd] - Blame information for rev 139

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---------------------------------------------------------------------
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-- TITLE: Plasma (CPU core with memory)
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-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
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-- DATE CREATED: 6/4/02
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-- FILENAME: plasma.vhd
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-- PROJECT: Plasma CPU core
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-- COPYRIGHT: Software placed into the public domain by the author.
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--    Software 'as is' without warranty.  Author liable for nothing.
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-- DESCRIPTION:
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--    This entity combines the CPU core with memory and a UART.
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--
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-- Memory Map:
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--   0x00000000 - 0x0000ffff   Internal RAM (16KB)
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--   0x10000000 - 0x000fffff   External RAM (1MB)
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--   Access all Misc registers with 32-bit accesses
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--   0x20000000  Uart Write (will pause CPU if busy)
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--   0x20000000  Uart Read
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--   0x20000010  IRQ Mask
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--   0x20000020  IRQ Status
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--   0x20000030  GPIO0 Out
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--   0x20000050  GPIOA In
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--   0x20000060  Counter
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--   IRQ bits:
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--      7   GPIO31
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--      6   GPIO30
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--      5  ^GPIO31
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--      4  ^GPIO30
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--      3   Counter(18)
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--      2  ^Counter(18)
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--      1  ^UartWriteBusy
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--      0   UartDataAvailable
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---------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use work.mlite_pack.all;
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entity plasma is
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   generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
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           log_file    : string := "UNUSED");
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   port(clk               : in std_logic;
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        reset             : in std_logic;
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        uart_write        : out std_logic;
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        uart_read         : in std_logic;
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        address           : out std_logic_vector(31 downto 2);
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        data_write        : out std_logic_vector(31 downto 0);
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        data_read         : in std_logic_vector(31 downto 0);
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        write_byte_enable : out std_logic_vector(3 downto 0);
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        mem_pause_in      : in std_logic;
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        gpio0_out         : out std_logic_vector(31 downto 0);
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        gpioA_in          : in std_logic_vector(31 downto 0));
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end; --entity plasma
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architecture logic of plasma is
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   signal address_reg         : std_logic_vector(31 downto 2);
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   signal data_write_reg      : std_logic_vector(31 downto 0);
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   signal write_byte_enable_reg : std_logic_vector(3 downto 0);
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   signal mem_address         : std_logic_vector(31 downto 0);
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   signal mem_data_read       : std_logic_vector(31 downto 0);
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   signal mem_data_write      : std_logic_vector(31 downto 0);
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   signal mem_write_byte_enable : std_logic_vector(3 downto 0);
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   signal data_read_ram       : std_logic_vector(31 downto 0);
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   signal data_read_uart      : std_logic_vector(7 downto 0);
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   signal write_enable        : std_logic;
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   signal mem_pause           : std_logic;
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   signal enable_internal_ram : std_logic;
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   signal enable_misc         : std_logic;
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   signal enable_uart         : std_logic;
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   signal enable_uart_read    : std_logic;
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   signal enable_uart_write   : std_logic;
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   signal gpio0_reg           : std_logic_vector(31 downto 0);
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   signal uart_write_busy     : std_logic;
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   signal uart_data_avail     : std_logic;
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   signal irq_mask_reg        : std_logic_vector(7 downto 0);
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   signal irq_status          : std_logic_vector(7 downto 0);
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   signal irq                 : std_logic;
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   signal counter_reg         : std_logic_vector(31 downto 0);
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begin  --architecture
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   write_byte_enable <= write_byte_enable_reg;
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   data_write <= data_write_reg;
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   address  <= address_reg;
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   write_enable <= '1' when write_byte_enable_reg /= "0000" else '0';
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   mem_pause <= mem_pause_in or (uart_write_busy and enable_uart and write_enable);
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   irq_status <= gpioA_in(31 downto 30) & (gpioA_in(31 downto 30) xor "11") &
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                 counter_reg(18) & not counter_reg(18) &
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                 not uart_write_busy & uart_data_avail;
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   irq <= '1' when (irq_status and irq_mask_reg) /= ZERO(7 downto 0) else '0';
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   gpio0_out <= gpio0_reg;
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   enable_internal_ram <= '1' when mem_address(30 downto 28) = "000" else '0';
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   enable_misc <= '1' when address_reg(30 downto 28) = "010" else '0';
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   enable_uart <= '1' when enable_misc = '1' and address_reg(7 downto 4) = "0000" else '0';
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   enable_uart_read <= enable_uart and not write_enable;
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   enable_uart_write <= enable_uart and write_enable;
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   u1_cpu: mlite_cpu
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      generic map (memory_type => memory_type)
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      PORT MAP (
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         clk          => clk,
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         reset_in     => reset,
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         intr_in      => irq,
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         mem_address  => mem_address,
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         mem_data_w   => mem_data_write,
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         mem_data_r   => mem_data_read,
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         mem_byte_we  => mem_write_byte_enable,
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         mem_pause    => mem_pause);
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   misc_proc: process(clk, reset, mem_address, address_reg, enable_misc,
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      data_read_ram, data_read, data_read_uart, mem_pause,
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      irq_mask_reg, irq_status, gpio0_reg, write_enable,
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      gpioA_in, counter_reg, mem_data_write, data_write_reg)
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   begin
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      case address_reg(30 downto 28) is
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      when "000" =>      --internal RAM
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         mem_data_read <= data_read_ram;
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      when "001" =>      --external RAM
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         mem_data_read <= data_read;
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      when "010" =>      --misc
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         case address_reg(6 downto 4) is
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         when "000" =>      --uart
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            mem_data_read <= ZERO(31 downto 8) & data_read_uart;
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         when "001" =>      --irq_mask
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            mem_data_read <= ZERO(31 downto 8) & irq_mask_reg;
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         when "010" =>      --irq_status
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            mem_data_read <= ZERO(31 downto 8) & irq_status;
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         when "011" =>      --gpio0
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            mem_data_read <= gpio0_reg;
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         when "101" =>      --gpioA
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            mem_data_read <= gpioA_in;
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         when "110" =>      --counter
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            mem_data_read <= counter_reg;
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         when others =>
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            mem_data_read <= gpioA_in;
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         end case;
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      when others =>
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         mem_data_read <= ZERO;
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      end case;
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      if reset = '1' then
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         address_reg <= ZERO(31 downto 2);
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         data_write_reg <= ZERO;
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         write_byte_enable_reg <= ZERO(3 downto 0);
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         irq_mask_reg <= ZERO(7 downto 0);
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         gpio0_reg <= ZERO;
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         counter_reg <= ZERO;
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      elsif rising_edge(clk) then
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         if mem_pause = '0' then
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            address_reg <= mem_address(31 downto 2);
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            data_write_reg <= mem_data_write;
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            write_byte_enable_reg <= mem_write_byte_enable;
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            if enable_misc = '1' and write_enable = '1' then
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               if address_reg(6 downto 4) = "001" then
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                  irq_mask_reg <= data_write_reg(7 downto 0);
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               elsif address_reg(6 downto 4) = "011" then
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                  gpio0_reg <= data_write_reg;
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               end if;
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            end if;
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         end if;
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         counter_reg <= bv_inc(counter_reg);
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      end if;
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   end process;
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   u2_ram: ram
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      generic map (memory_type => memory_type)
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      port map (
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         clk               => clk,
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         enable            => enable_internal_ram,
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         write_byte_enable => mem_write_byte_enable,
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         address           => mem_address(31 downto 2),
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         data_write        => mem_data_write,
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         data_read         => data_read_ram);
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   u3_uart: uart
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      generic map (log_file => log_file)
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      port map(
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         clk          => clk,
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         reset        => reset,
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         enable_read  => enable_uart_read,
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         enable_write => enable_uart_write,
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         data_in      => data_write_reg(7 downto 0),
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         data_out     => data_read_uart,
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         uart_read    => uart_read,
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         uart_write   => uart_write,
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         busy_write   => uart_write_busy,
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         data_avail   => uart_data_avail);
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end; --architecture logic

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