URL https://opencores.org/ocsvn/mmcfpgaconfig/mmcfpgaconfig/trunk

Subversion Repositories mmcfpgaconfig

[/] [mmcfpgaconfig/] [trunk/] [rtl/] [verilog/] [mmc_boot_prescaler.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	2	openchip	`// Copyright 2004-2005 Openchip`
2			`// http://www.openchip.org`
3
4			`// ---------------------------------------------------------------------------`
5			`// Clock Prescaler`
6			`//`
7			`// For Xilinx Passive serial we use`
8			`// Divide by 16 or 1:1 clock deliver from FGPA (6MHz)`
9			`// ---------------------------------------------------------------------------`
10
11			`module mmc_boot_prescaler_16_1(`
12			`rst,`
13			`sys_clk,`
14			`mmc_clk,`
15			`mode_transfer`
16			`);`
17
18			`input rst;`
19			`input sys_clk;`
20			`output mmc_clk;`
21			`input mode_transfer;`
22
23			`reg [3:0] prescaler;`
24
25			`always @(posedge sys_clk)`
26			`if (rst)`
27			`prescaler <= 4'b0000;`
28			`else`
29			`prescaler <= prescaler + 4'b0001;`
30
31			`// ---------------------------------------------------------------------------`
32			`// Select divide by 16 or direct sys_clk (CCLK)`
33			`// ---------------------------------------------------------------------------`
34
35			`assign mmc_clk = mode_transfer ? sys_clk : prescaler[3];`
36
37
38			`endmodule`