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[/] [mmcfpgaconfig/] [trunk/] [rtl/] [verilog/] [mmc_cmd_select.v] - Blame information for rev 8

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//
// Hard-wired CMD bit module, includes hard-wired CRC
// optimized for PLD implementation
//
 
 
//
// MMC CMD Bit Select
// Start, Command, Arg, CRC, Stop
//
 
`include "mmc_boot_defines.v"
 
module mmc_cmd_select(
  cmd,
  bit,
  cmd_active,
  data);
 
input [3:0] cmd;
input [7:0] bit;
output cmd_active;
output data;
 
wire start_bit;
wire cmd_bits;
wire CMD1_dat;
wire arg16_bit;
wire crc_bit;
wire stop_bit;
 
 
//
// Command bits active 
// START, CMD, ARG, CRC7, STOP == 48Bits
//
assign cmd_bits  = (bit[7:6] == 2'b00) &
                   (bit[5:4] != 2'b11) &
                            (cmd[3:2] != 2'b11);
// Start bit
assign start_bit = bit[7:0] == 8'b00000001;
// RCA=0x01 (D16 in Argument)
assign arg16_bit = bit[7:0] == 8'b00010111;
// select Start Address for streaming
//assign arg_x_bit = counter_command_bits[7:0] == 8'b00010101; 
// Stop bit
assign stop_bit  = bit[7:0] == 8'b00101111;
 
// ---------------------------------------------------------------------------
// hard-wired CRC7 generator!
// this implementation requires less resources in PLD 
// than serial CRC calculator
// the values are calculated by an C program
// ---------------------------------------------------------------------------
 
// CMD0,0          xx
// CMD1,0x80FF8000 xx
// CMD2,0          4d   0100 1101
// CMD3,0x10000    7f   0111 1111
// CMD7,0x10000    dd   1101 1101
// CMD11,0         77   0111 0111
 
assign crc_bit =
    ( (bit[5:0] == 6'b101000) & (
      (cmd==`CMD0)
    | (cmd==`CMD1)
    | (cmd==`CMD7) ) ) // CRC6
 
  | ( (bit[5:0] == 6'b101001) & (
      (cmd==`CMD2)
    | (cmd==`CMD3)
    | (cmd==`CMD7)
    | (cmd==`CMD11) ) ) // CRC5
 
  | ( (bit[5:0] == 6'b101010) & (
      (cmd==`CMD1)
    | (cmd==`CMD3)
    | (cmd==`CMD11) ) ) // CRC4
 
  | ( (bit[5:0] == 6'b101011) & (
      (cmd==`CMD0)
    | (cmd==`CMD3)
    | (cmd==`CMD7)
    | (cmd==`CMD11) ) ) // CRC3
 
  | ( (bit[5:0] == 6'b101100) & (
      (cmd==`CMD1)
    | (cmd==`CMD2)
    | (cmd==`CMD3)
    | (cmd==`CMD7) ) ) // CRC2
 
  | ( (bit[5:0] == 6'b101101) & (
      (cmd==`CMD0)
    | (cmd==`CMD1)
    | (cmd==`CMD2)
    | (cmd==`CMD3)
    | (cmd==`CMD7)
    | (cmd==`CMD11) ) ) // CRC1
 
  | ( (bit[5:0] == 6'b101110) & (
      (cmd==`CMD1)
    | (cmd==`CMD3)
    | (cmd==`CMD11) ) ) // CRC0
  ;
 
// ---------------------------------------------------------------------------
// Hard wired ARG for CMD1 == 0x80FF8000
// ---------------------------------------------------------------------------
 
assign CMD1_dat = (cmd==`CMD1) &
  ( (bit[5:0] == 6'b001000) //
  | (bit[5:0] == 6'b010000) //
  | (bit[5:0] == 6'b010001) //
  | (bit[5:0] == 6'b010010) //
  | (bit[5:0] == 6'b010011) //
  | (bit[5:0] == 6'b010100) //
  | (bit[5:0] == 6'b010101) //
  | (bit[5:0] == 6'b010110) //
  | (bit[5:0] == 6'b010111) //
  | (bit[5:0] == 6'b011000) //
  );
 
 
// ---------------------------------------------------------------------------
// Select CMD Data output
// ---------------------------------------------------------------------------
 
assign data =
    start_bit                // START
  | ( cmd[0] & (bit[5:0] == 6'b000111)  )
  | ( cmd[1] & (bit[5:0] == 6'b000110)  )
  | ( cmd[2] & (bit[5:0] == 6'b000101)  )
  | ( cmd[3] & (bit[5:0] == 6'b000100)  )
  | CMD1_dat // CMD1 Argument
  | ( arg16_bit & ((cmd == `CMD3) | (cmd == `CMD7)) ) // RCA = 0x1 ARG16
//  | ( arg_x_bit & (cmd_state == CMD11) ) // Start Address = 0x0400 ARG10
  | crc_bit                  // Hard coded CRC7
  | stop_bit;                // STOP
 
assign cmd_active = cmd_bits;
 
endmodule

Line No.	Rev	Author	Line
1	4	openchip	`//`
2			`// Hard-wired CMD bit module, includes hard-wired CRC`
3			`// optimized for PLD implementation`
4			`//`
5
6
7			`//`
8			`// MMC CMD Bit Select`
9			`// Start, Command, Arg, CRC, Stop`
10			`//`
11
12			`include "mmc_boot_defines.v"
13
14			`module mmc_cmd_select(`
15			`cmd,`
16			`bit,`
17			`cmd_active,`
18			`data);`
19
20			`input [3:0] cmd;`
21			`input [7:0] bit;`
22			`output cmd_active;`
23			`output data;`
24
25			`wire start_bit;`
26			`wire cmd_bits;`
27			`wire CMD1_dat;`
28			`wire arg16_bit;`
29			`wire crc_bit;`
30			`wire stop_bit;`
31
32
33			`//`
34			`// Command bits active`
35			`// START, CMD, ARG, CRC7, STOP == 48Bits`
36			`//`
37			`assign cmd_bits = (bit[7:6] == 2'b00) &`
38			`(bit[5:4] != 2'b11) &`
39			`(cmd[3:2] != 2'b11);`
40			`// Start bit`
41			`assign start_bit = bit[7:0] == 8'b00000001;`
42			`// RCA=0x01 (D16 in Argument)`
43			`assign arg16_bit = bit[7:0] == 8'b00010111;`
44			`// select Start Address for streaming`
45			`//assign arg_x_bit = counter_command_bits[7:0] == 8'b00010101;`
46			`// Stop bit`
47			`assign stop_bit = bit[7:0] == 8'b00101111;`
48
49			`// ---------------------------------------------------------------------------`
50			`// hard-wired CRC7 generator!`
51			`// this implementation requires less resources in PLD`
52			`// than serial CRC calculator`
53			`// the values are calculated by an C program`
54			`// ---------------------------------------------------------------------------`
55
56			`// CMD0,0 xx`
57			`// CMD1,0x80FF8000 xx`
58			`// CMD2,0 4d 0100 1101`
59			`// CMD3,0x10000 7f 0111 1111`
60			`// CMD7,0x10000 dd 1101 1101`
61			`// CMD11,0 77 0111 0111`
62
63			`assign crc_bit =`
64			`( (bit[5:0] == 6'b101000) & (`
65			(cmd==`CMD0)
66			\| (cmd==`CMD1)
67			\| (cmd==`CMD7) ) ) // CRC6
68
69			`\| ( (bit[5:0] == 6'b101001) & (`
70			(cmd==`CMD2)
71			\| (cmd==`CMD3)
72			\| (cmd==`CMD7)
73			\| (cmd==`CMD11) ) ) // CRC5
74
75			`\| ( (bit[5:0] == 6'b101010) & (`
76			(cmd==`CMD1)
77			\| (cmd==`CMD3)
78			\| (cmd==`CMD11) ) ) // CRC4
79
80			`\| ( (bit[5:0] == 6'b101011) & (`
81			(cmd==`CMD0)
82			\| (cmd==`CMD3)
83			\| (cmd==`CMD7)
84			\| (cmd==`CMD11) ) ) // CRC3
85
86			`\| ( (bit[5:0] == 6'b101100) & (`
87			(cmd==`CMD1)
88			\| (cmd==`CMD2)
89			\| (cmd==`CMD3)
90			\| (cmd==`CMD7) ) ) // CRC2
91
92			`\| ( (bit[5:0] == 6'b101101) & (`
93			(cmd==`CMD0)
94			\| (cmd==`CMD1)
95			\| (cmd==`CMD2)
96			\| (cmd==`CMD3)
97			\| (cmd==`CMD7)
98			\| (cmd==`CMD11) ) ) // CRC1
99
100			`\| ( (bit[5:0] == 6'b101110) & (`
101			(cmd==`CMD1)
102			\| (cmd==`CMD3)
103			\| (cmd==`CMD11) ) ) // CRC0
104			`;`
105
106			`// ---------------------------------------------------------------------------`
107			`// Hard wired ARG for CMD1 == 0x80FF8000`
108			`// ---------------------------------------------------------------------------`
109
110			assign CMD1_dat = (cmd==`CMD1) &
111			`( (bit[5:0] == 6'b001000) //`
112			`\| (bit[5:0] == 6'b010000) //`
113			`\| (bit[5:0] == 6'b010001) //`
114			`\| (bit[5:0] == 6'b010010) //`
115			`\| (bit[5:0] == 6'b010011) //`
116			`\| (bit[5:0] == 6'b010100) //`
117			`\| (bit[5:0] == 6'b010101) //`
118			`\| (bit[5:0] == 6'b010110) //`
119			`\| (bit[5:0] == 6'b010111) //`
120			`\| (bit[5:0] == 6'b011000) //`
121			`);`
122
123
124			`// ---------------------------------------------------------------------------`
125			`// Select CMD Data output`
126			`// ---------------------------------------------------------------------------`
127
128			`assign data =`
129			`start_bit // START`
130			`\| ( cmd[0] & (bit[5:0] == 6'b000111) )`
131			`\| ( cmd[1] & (bit[5:0] == 6'b000110) )`
132			`\| ( cmd[2] & (bit[5:0] == 6'b000101) )`
133			`\| ( cmd[3] & (bit[5:0] == 6'b000100) )`
134			`\| CMD1_dat // CMD1 Argument`
135			\| ( arg16_bit & ((cmd == `CMD3) \| (cmd == `CMD7)) ) // RCA = 0x1 ARG16
136			`// \| ( arg_x_bit & (cmd_state == CMD11) ) // Start Address = 0x0400 ARG10`
137			`\| crc_bit // Hard coded CRC7`
138			`\| stop_bit; // STOP`
139
140			`assign cmd_active = cmd_bits;`
141
142			`endmodule`

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[/] [mmcfpgaconfig/] [trunk/] [rtl/] [verilog/] [mmc_cmd_select.v] - Blame information for rev 8