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[/] [mmcfpgaconfig/] [trunk/] [rtl/] [verilog/] [virtex_bitstream_const.v] - Blame information for rev 6

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// Copyright 2004-2005 Openchip
// http://www.openchip.org
 
 
// XAPP-151
`define VIRTEX_CFG_CMD_WCFG     4'b0001
`define VIRTEX_CFG_CMD_LFRM     4'b0011
`define VIRTEX_CFG_CMD_RCFG     4'b0100
`define VIRTEX_CFG_CMD_START    4'b0101
`define VIRTEX_CFG_CMD_RCAP     4'b0110
`define VIRTEX_CFG_CMD_RCRC     4'b0111
`define VIRTEX_CFG_CMD_AGHIGH   4'b1000
`define VIRTEX_CFG_CMD_SWITCH   4'b1001
// Virtex-II/Pro, S-3
`define VIRTEX_CFG_CMD_DESYNC   4'b1101
 
 
// XAPP 151
`define VIRTEX_CFG_REG_CRC      4'b0000
`define VIRTEX_CFG_REG_FAR      4'b0001
`define VIRTEX_CFG_REG_FDRI     4'b0010
`define VIRTEX_CFG_REG_FDRO     4'b0011
`define VIRTEX_CFG_REG_CMD      4'b0100
`define VIRTEX_CFG_REG_CTL      4'b0101
`define VIRTEX_CFG_REG_MASK     4'b0110
`define VIRTEX_CFG_REG_STAT     4'b0111
`define VIRTEX_CFG_REG_LOUT     4'b1000
`define VIRTEX_CFG_REG_COR      4'b1001
`define VIRTEX_CFG_REG_FLR      4'b1011
 
 
// Virtex-II
`define VIRTEX_CFG_REG_RES_E    4'b1110
 
 
// XAPP 151
`define VIRTEX_CFG_OP_READ      2'b01
`define VIRTEX_CFG_OP_WRITE     2'b10
 
 
 
 
 
 
 

Line No.	Rev	Author	Line
1	2	openchip	`// Copyright 2004-2005 Openchip`
2			`// http://www.openchip.org`
3
4
5			`// XAPP-151`
6			`define VIRTEX_CFG_CMD_WCFG 4'b0001
7			`define VIRTEX_CFG_CMD_LFRM 4'b0011
8			`define VIRTEX_CFG_CMD_RCFG 4'b0100
9			`define VIRTEX_CFG_CMD_START 4'b0101
10			`define VIRTEX_CFG_CMD_RCAP 4'b0110
11			`define VIRTEX_CFG_CMD_RCRC 4'b0111
12			`define VIRTEX_CFG_CMD_AGHIGH 4'b1000
13			`define VIRTEX_CFG_CMD_SWITCH 4'b1001
14			`// Virtex-II/Pro, S-3`
15			`define VIRTEX_CFG_CMD_DESYNC 4'b1101
16
17
18			`// XAPP 151`
19			`define VIRTEX_CFG_REG_CRC 4'b0000
20			`define VIRTEX_CFG_REG_FAR 4'b0001
21			`define VIRTEX_CFG_REG_FDRI 4'b0010
22			`define VIRTEX_CFG_REG_FDRO 4'b0011
23			`define VIRTEX_CFG_REG_CMD 4'b0100
24			`define VIRTEX_CFG_REG_CTL 4'b0101
25			`define VIRTEX_CFG_REG_MASK 4'b0110
26			`define VIRTEX_CFG_REG_STAT 4'b0111
27			`define VIRTEX_CFG_REG_LOUT 4'b1000
28			`define VIRTEX_CFG_REG_COR 4'b1001
29			`define VIRTEX_CFG_REG_FLR 4'b1011
30
31
32			`// Virtex-II`
33			`define VIRTEX_CFG_REG_RES_E 4'b1110
34
35
36			`// XAPP 151`
37			`define VIRTEX_CFG_OP_READ 2'b01
38			`define VIRTEX_CFG_OP_WRITE 2'b10
39
40
41
42
43
44
45

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[/] [mmcfpgaconfig/] [trunk/] [rtl/] [verilog/] [virtex_bitstream_const.v] - Blame information for rev 6