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[/] [mmcfpgaconfig/] [trunk/] [rtl/] [verilog/] [xilinx_fpga_config_int.v] - Blame information for rev 6

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// Copyright 2004-2005 Openchip
// http://www.openchip.org
 
`include "virtex_bitstream_const.v"
 
module xilinx_fpga_config_int(
  // Power on reset (simulat power on reset)
  por,
  sys_clk100,
  // Xilinx Config Interface
 
  cclk_I, cclk_T, cclk_O,
  init_I, init_T, init_O,
 
  din,
  prog_b,
  done,
  rdwr_b,
  cs_b,
 
  // internal registers
  CMD, COR, FAR,
 
  // config input
  M0, M1, M2,
  // JTAG port
  tclk, tdi, tdo, tms,
 
 
 
  //
  trace1,
  trace2
  );
 
 
input por;
input sys_clk100;
 
input  cclk_I;
output cclk_O;
output cclk_T;
 
input init_I;
output init_T;
output init_O;
 
input din;
input prog_b;
input rdwr_b;
input cs_b;
 
output done;
 
 
 
 
output [3:0] CMD;
output [31:0] COR;
output [31:0] FAR;
input  M0;
input  M1;
input  M2;
input  tclk;
input  tdi;
output tdo;
input  tms;
 
 
//
output trace1;
output trace2;
 
 
wire init;
assign init = init_I & init_O;
 
//
// internal reset is high when init and prog are both low
// or on Power On Reset
//
wire internal_reset;
assign internal_reset = !prog_b | !por;
 
 
 
//
// Clear Int memory, as long as prog_b is low, and some time after it (delay)
//
reg config_memory_cleared;
reg [7:0] config_clear_cnt;
 
always @(posedge sys_clk100)
  if (internal_reset)
    config_clear_cnt <= 8'b00000000;
  else
    config_clear_cnt <= config_clear_cnt + 8'b00000001;
 
always @(posedge sys_clk100)
  if (internal_reset)
    config_memory_cleared <= 1'b0;
  else
    if (config_clear_cnt[7])
      config_memory_cleared <= 1'b1;
 
//
// Latch M0, M1, M2
//
reg M_latched;
reg [2:0] M_r;
 
// have we latched M0, M1, M2 ?
always @(posedge sys_clk100)
  if (internal_reset)
    M_latched <= 1'b0;
  else
    if (config_memory_cleared)
       M_latched <= 1'b1;
 
// Latch M0, M1, M2
always @(posedge sys_clk100)
  if (internal_reset)
    M_r <= 3'b0;
  else
    if (!M_latched & config_memory_cleared)
      M_r <= {M2, M1, M0};
 
 
// 
assign init_0 = M_latched;
assign init_T = !M_latched;
 
 
//
// Start Master mode CCLK !
//
 
reg enable_internal_cclk;
 
always @(posedge sys_clk100)
  if (internal_reset)
    enable_internal_cclk <= 1'b0;
  else
    if (M_latched)
      enable_internal_cclk <= 1'b1;
//
//
//
wire mode_master_serial;
wire mode_slave_serial;
wire mode_master_parallel;
wire mode_slave_parallel;
wire mode_jtag;
 
assign mode_master_serial   = (M_r == 3'b000) & M_latched;
assign mode_slave_serial    = (M_r == 3'b000) & M_latched;
assign mode_master_parallel = (M_r == 3'b000) & M_latched;
assign mode_slave_parallel  = (M_r == 3'b000) & M_latched;
assign mode_jtag            = (M_r == 3'b000) & M_latched;
 
 
 
 
 
 
 
//
// Master CCLK prescaler
//
reg [7:0] prescaler;
wire cclk_master;
 
always @(posedge sys_clk100)
  prescaler <= prescaler + 8'b00000001;
 
assign cclk_master = prescaler[2];
 
 
//
// Master or Slave Clock select
//
wire master_clock;
assign master_clock = 1'b1;
 
assign cclk = master_clock ? cclk_master : cclk_I;
 
 
//
// only when running!! before memory clear no CCLK out !
//
assign cclk_O = enable_internal_cclk ? cclk_master : 1'b0;
assign cclk_T = enable_internal_cclk;
 
 
 
 
 
 
 
 
 
 
//
// 32 bit shift register to
// 
reg [31:0] sr;
 
always @(posedge cclk or posedge internal_reset)
  if (internal_reset)
    sr <= 32'h00000000;
  else
    begin
      sr[0] <= din;
         sr[1] <= sr[0];
         sr[2] <= sr[1];
         sr[3] <= sr[2];
         sr[4] <= sr[3];
         sr[5] <= sr[4];
         sr[6] <= sr[5];
         sr[7] <= sr[6];
         sr[8] <= sr[7];
         sr[9] <= sr[8];
         sr[10] <= sr[9];
         sr[11] <= sr[10];
         sr[12] <= sr[11];
         sr[13] <= sr[12];
         sr[14] <= sr[13];
         sr[15] <= sr[14];
         sr[16] <= sr[15];
         sr[17] <= sr[16];
         sr[18] <= sr[17];
         sr[19] <= sr[18];
         sr[20] <= sr[19];
         sr[21] <= sr[20];
         sr[22] <= sr[21];
         sr[23] <= sr[22];
         sr[24] <= sr[23];
         sr[25] <= sr[24];
         sr[26] <= sr[25];
         sr[27] <= sr[26];
         sr[28] <= sr[27];
         sr[29] <= sr[28];
         sr[30] <= sr[29];
      sr[31] <= sr[30];
    end
 
//
// Detect Align SYNC
//
wire sync_det;
 
assign syn_det = sr[31:0] == 32'hAA995566;
 
reg syn_det_ok;
 
always @(posedge cclk or posedge internal_reset)
  if (internal_reset)
    syn_det_ok <= 1'b0;
  else
    if (syn_det)
      syn_det_ok <= 1'b1;
 
 
//
// count 32 bits for each word
//
reg [4:0] shift_cnt32;
 
always @(posedge cclk)
  if (!syn_det_ok)
    shift_cnt32 <= 5'b00000;
  else
    shift_cnt32 <= shift_cnt32 + 5'b00001;
 
//
// strobe 32 bit words
//
wire word_stb;
 
assign word_stb = shift_cnt32 == 5'b11111;
 
//
//
//
reg [31:0] header;
//
// Statemachine to track latches to the header
//
always @(posedge cclk)
  if (!syn_det_ok)
    header <= 32'h00000000;
  else if (word_stb)
    header <= sr;
 
 
//
// Operation Read or Write
//
wire header_op_write;
wire header_op_read;
 
assign header_op_write = header[28:27] == `VIRTEX_CFG_OP_WRITE;
assign header_op_read =  header[28:27] == `VIRTEX_CFG_OP_READ;
 
 
// Command header field
wire header_type_command;
wire header_type_large_block;
 
assign header_type_command = header[31:29] == 3'b001;
assign header_type_large_block = header[31:29] == 3'b010;
 
wire command_header_stb;
assign command_header_stb = header_type_command & word_stb;
 
//
// Word Counter
//
reg [19:0] WC;
 
 
 
//
// write to config register
//
wire cfg_write_stb;
assign cfg_write_stb = header_type_command & header_op_write & word_stb;
 
 
//
// Write strobes to registers
//
 
 
// CMD Register is target
wire write_CMD;
assign write_CMD = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_CMD);
 
 
// COR Option Register is target
wire write_COR;
assign write_COR = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_COR);
 
// FAR Register is target
wire write_FAR;
assign write_FAR = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_FAR);
 
wire write_FLR;
assign write_FLR = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_FLR);
 
wire write_CRC;
assign write_CRC = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_CRC);
 
wire write_CTL;
assign write_CTL = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_CTL);
 
wire write_MASK;
assign write_MASK = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_MASK);
 
wire write_STAT;
assign write_STAT = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_STAT);
 
wire write_FDRI;
assign write_FDRI = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_FDRI);
 
 
wire write_RES_E;
assign write_RES_E = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_RES_E);
 
//
// 4 Bit CMD register
//
reg [3:0] CMD;
//
// Write to CMD latch value written
//
always @(posedge cclk or posedge internal_reset)
  if (internal_reset)
    CMD <= 4'b0000;
  else
    if (write_CMD)
      CMD <= sr[3:0];
//
// Config states (value in CMD)
//
wire cfg_state_START;
assign cfg_state_START = CMD == `VIRTEX_CFG_CMD_START;
 
wire cfg_state_RCRC;
assign cfg_state_RCRC = CMD == `VIRTEX_CFG_CMD_RCRC;
 
 
//
// 31 Bit COR register
//
reg [31:0] COR;
//
// Write to CMD latch value written
//
always @(posedge cclk or posedge internal_reset)
  if (internal_reset)
    COR <= 31'h00000000;
  else
    if (write_COR)
      COR <= sr[3:0];
 
//
// 31 Bit FAR register
//
reg [31:0] FAR;
//
// Write to CMD latch value written
//
always @(posedge cclk or posedge internal_reset)
  if (internal_reset)
    FAR <= 31'h00000000;
  else
    if (write_FAR)
      FAR <= sr[3:0];
 
 
 
 
 
//
// Large Block Count
//
 
 
wire write_LBC;
assign write_LBC = header_type_large_block & word_stb;
 
 
 
 
 
//
// CRC
//
 
//
//
// holds CRC as written with WCFG CRC 
reg [15:0] CRC_from_cfg;
 
 
always @(posedge cclk or posedge internal_reset)
  if (internal_reset)
    CRC_from_cfg <= 16'h0000;
  else if (write_CRC)
    CRC_from_cfg[15:0] <= sr[15:0];
 
 
//assign trace_sync_found = sr[15:0] == 16'h55AA;
 
// Virtex/Spartan SYNC word    
assign trace1 = cfg_state_START;
 
assign done = cfg_state_START;
 
assign trace2 =
  write_LBC |
  write_CMD |
  write_COR |
  write_CRC |
  write_FLR |
  write_FAR |
  write_CTL |
  write_STAT |
  write_FDRI |
 
  write_RES_E |
  write_MASK;
 
 
endmodule

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[/] [mmcfpgaconfig/] [trunk/] [rtl/] [verilog/] [xilinx_fpga_config_int.v] - Blame information for rev 6

Line No.	Rev	Author	Line
1	2	openchip
2			`// Copyright 2004-2005 Openchip`
3			`// http://www.openchip.org`
4
5			`include "virtex_bitstream_const.v"
6
7			`module xilinx_fpga_config_int(`
8			`// Power on reset (simulat power on reset)`
9			`por,`
10			`sys_clk100,`
11			`// Xilinx Config Interface`
12
13			`cclk_I, cclk_T, cclk_O,`
14			`init_I, init_T, init_O,`
15
16			`din,`
17			`prog_b,`
18			`done,`
19			`rdwr_b,`
20			`cs_b,`
21
22			`// internal registers`
23			`CMD, COR, FAR,`
24
25			`// config input`
26			`M0, M1, M2,`
27			`// JTAG port`
28			`tclk, tdi, tdo, tms,`
29
30
31
32			`//`
33			`trace1,`
34			`trace2`
35			`);`
36
37
38			`input por;`
39			`input sys_clk100;`
40
41			`input cclk_I;`
42			`output cclk_O;`
43			`output cclk_T;`
44
45			`input init_I;`
46			`output init_T;`
47			`output init_O;`
48
49			`input din;`
50			`input prog_b;`
51			`input rdwr_b;`
52			`input cs_b;`
53
54			`output done;`
55
56
57
58
59			`output [3:0] CMD;`
60			`output [31:0] COR;`
61			`output [31:0] FAR;`
62			`input M0;`
63			`input M1;`
64			`input M2;`
65			`input tclk;`
66			`input tdi;`
67			`output tdo;`
68			`input tms;`
69
70
71			`//`
72			`output trace1;`
73			`output trace2;`
74
75
76			`wire init;`
77			`assign init = init_I & init_O;`
78
79			`//`
80			`// internal reset is high when init and prog are both low`
81			`// or on Power On Reset`
82			`//`
83			`wire internal_reset;`
84			`assign internal_reset = !prog_b \| !por;`
85
86
87
88			`//`
89			`// Clear Int memory, as long as prog_b is low, and some time after it (delay)`
90			`//`
91			`reg config_memory_cleared;`
92			`reg [7:0] config_clear_cnt;`
93
94			`always @(posedge sys_clk100)`
95			`if (internal_reset)`
96			`config_clear_cnt <= 8'b00000000;`
97			`else`
98			`config_clear_cnt <= config_clear_cnt + 8'b00000001;`
99
100			`always @(posedge sys_clk100)`
101			`if (internal_reset)`
102			`config_memory_cleared <= 1'b0;`
103			`else`
104			`if (config_clear_cnt[7])`
105			`config_memory_cleared <= 1'b1;`
106
107			`//`
108			`// Latch M0, M1, M2`
109			`//`
110			`reg M_latched;`
111			`reg [2:0] M_r;`
112
113			`// have we latched M0, M1, M2 ?`
114			`always @(posedge sys_clk100)`
115			`if (internal_reset)`
116			`M_latched <= 1'b0;`
117			`else`
118			`if (config_memory_cleared)`
119			`M_latched <= 1'b1;`
120
121			`// Latch M0, M1, M2`
122			`always @(posedge sys_clk100)`
123			`if (internal_reset)`
124			`M_r <= 3'b0;`
125			`else`
126			`if (!M_latched & config_memory_cleared)`
127			`M_r <= {M2, M1, M0};`
128
129
130			`//`
131			`assign init_0 = M_latched;`
132			`assign init_T = !M_latched;`
133
134
135			`//`
136			`// Start Master mode CCLK !`
137			`//`
138
139			`reg enable_internal_cclk;`
140
141			`always @(posedge sys_clk100)`
142			`if (internal_reset)`
143			`enable_internal_cclk <= 1'b0;`
144			`else`
145			`if (M_latched)`
146			`enable_internal_cclk <= 1'b1;`
147			`//`
148			`//`
149			`//`
150			`wire mode_master_serial;`
151			`wire mode_slave_serial;`
152			`wire mode_master_parallel;`
153			`wire mode_slave_parallel;`
154			`wire mode_jtag;`
155
156			`assign mode_master_serial = (M_r == 3'b000) & M_latched;`
157			`assign mode_slave_serial = (M_r == 3'b000) & M_latched;`
158			`assign mode_master_parallel = (M_r == 3'b000) & M_latched;`
159			`assign mode_slave_parallel = (M_r == 3'b000) & M_latched;`
160			`assign mode_jtag = (M_r == 3'b000) & M_latched;`
161
162
163
164
165
166
167
168			`//`
169			`// Master CCLK prescaler`
170			`//`
171			`reg [7:0] prescaler;`
172			`wire cclk_master;`
173
174			`always @(posedge sys_clk100)`
175			`prescaler <= prescaler + 8'b00000001;`
176
177			`assign cclk_master = prescaler[2];`
178
179
180			`//`
181			`// Master or Slave Clock select`
182			`//`
183			`wire master_clock;`
184			`assign master_clock = 1'b1;`
185
186			`assign cclk = master_clock ? cclk_master : cclk_I;`
187
188
189			`//`
190			`// only when running!! before memory clear no CCLK out !`
191			`//`
192			`assign cclk_O = enable_internal_cclk ? cclk_master : 1'b0;`
193			`assign cclk_T = enable_internal_cclk;`
194
195
196
197
198
199
200
201
202
203
204			`//`
205			`// 32 bit shift register to`
206			`//`
207			`reg [31:0] sr;`
208
209			`always @(posedge cclk or posedge internal_reset)`
210			`if (internal_reset)`
211			`sr <= 32'h00000000;`
212			`else`
213			`begin`
214			`sr[0] <= din;`
215			`sr[1] <= sr[0];`
216			`sr[2] <= sr[1];`
217			`sr[3] <= sr[2];`
218			`sr[4] <= sr[3];`
219			`sr[5] <= sr[4];`
220			`sr[6] <= sr[5];`
221			`sr[7] <= sr[6];`
222			`sr[8] <= sr[7];`
223			`sr[9] <= sr[8];`
224			`sr[10] <= sr[9];`
225			`sr[11] <= sr[10];`
226			`sr[12] <= sr[11];`
227			`sr[13] <= sr[12];`
228			`sr[14] <= sr[13];`
229			`sr[15] <= sr[14];`
230			`sr[16] <= sr[15];`
231			`sr[17] <= sr[16];`
232			`sr[18] <= sr[17];`
233			`sr[19] <= sr[18];`
234			`sr[20] <= sr[19];`
235			`sr[21] <= sr[20];`
236			`sr[22] <= sr[21];`
237			`sr[23] <= sr[22];`
238			`sr[24] <= sr[23];`
239			`sr[25] <= sr[24];`
240			`sr[26] <= sr[25];`
241			`sr[27] <= sr[26];`
242			`sr[28] <= sr[27];`
243			`sr[29] <= sr[28];`
244			`sr[30] <= sr[29];`
245			`sr[31] <= sr[30];`
246			`end`
247
248			`//`
249			`// Detect Align SYNC`
250			`//`
251			`wire sync_det;`
252
253			`assign syn_det = sr[31:0] == 32'hAA995566;`
254
255			`reg syn_det_ok;`
256
257			`always @(posedge cclk or posedge internal_reset)`
258			`if (internal_reset)`
259			`syn_det_ok <= 1'b0;`
260			`else`
261			`if (syn_det)`
262			`syn_det_ok <= 1'b1;`
263
264
265			`//`
266			`// count 32 bits for each word`
267			`//`
268			`reg [4:0] shift_cnt32;`
269
270			`always @(posedge cclk)`
271			`if (!syn_det_ok)`
272			`shift_cnt32 <= 5'b00000;`
273			`else`
274			`shift_cnt32 <= shift_cnt32 + 5'b00001;`
275
276			`//`
277			`// strobe 32 bit words`
278			`//`
279			`wire word_stb;`
280
281			`assign word_stb = shift_cnt32 == 5'b11111;`
282
283			`//`
284			`//`
285			`//`
286			`reg [31:0] header;`
287			`//`
288			`// Statemachine to track latches to the header`
289			`//`
290			`always @(posedge cclk)`
291			`if (!syn_det_ok)`
292			`header <= 32'h00000000;`
293			`else if (word_stb)`
294			`header <= sr;`
295
296
297			`//`
298			`// Operation Read or Write`
299			`//`
300			`wire header_op_write;`
301			`wire header_op_read;`
302
303			assign header_op_write = header[28:27] == `VIRTEX_CFG_OP_WRITE;
304			assign header_op_read = header[28:27] == `VIRTEX_CFG_OP_READ;
305
306
307			`// Command header field`
308			`wire header_type_command;`
309			`wire header_type_large_block;`
310
311			`assign header_type_command = header[31:29] == 3'b001;`
312			`assign header_type_large_block = header[31:29] == 3'b010;`
313
314			`wire command_header_stb;`
315			`assign command_header_stb = header_type_command & word_stb;`
316
317			`//`
318			`// Word Counter`
319			`//`
320			`reg [19:0] WC;`
321
322
323
324			`//`
325			`// write to config register`
326			`//`
327			`wire cfg_write_stb;`
328			`assign cfg_write_stb = header_type_command & header_op_write & word_stb;`
329
330
331			`//`
332			`// Write strobes to registers`
333			`//`
334
335
336			`// CMD Register is target`
337			`wire write_CMD;`
338			assign write_CMD = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_CMD);
339
340
341			`// COR Option Register is target`
342			`wire write_COR;`
343			assign write_COR = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_COR);
344
345			`// FAR Register is target`
346			`wire write_FAR;`
347			assign write_FAR = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_FAR);
348
349			`wire write_FLR;`
350			assign write_FLR = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_FLR);
351
352			`wire write_CRC;`
353			assign write_CRC = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_CRC);
354
355			`wire write_CTL;`
356			assign write_CTL = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_CTL);
357
358			`wire write_MASK;`
359			assign write_MASK = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_MASK);
360
361			`wire write_STAT;`
362			assign write_STAT = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_STAT);
363
364			`wire write_FDRI;`
365			assign write_FDRI = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_FDRI);
366
367
368			`wire write_RES_E;`
369			assign write_RES_E = cfg_write_stb & (header[16:13]==`VIRTEX_CFG_REG_RES_E);
370
371			`//`
372			`// 4 Bit CMD register`
373			`//`
374			`reg [3:0] CMD;`
375			`//`
376			`// Write to CMD latch value written`
377			`//`
378			`always @(posedge cclk or posedge internal_reset)`
379			`if (internal_reset)`
380			`CMD <= 4'b0000;`
381			`else`
382			`if (write_CMD)`
383			`CMD <= sr[3:0];`
384			`//`
385			`// Config states (value in CMD)`
386			`//`
387			`wire cfg_state_START;`
388			assign cfg_state_START = CMD == `VIRTEX_CFG_CMD_START;
389
390			`wire cfg_state_RCRC;`
391			assign cfg_state_RCRC = CMD == `VIRTEX_CFG_CMD_RCRC;
392
393
394			`//`
395			`// 31 Bit COR register`
396			`//`
397			`reg [31:0] COR;`
398			`//`
399			`// Write to CMD latch value written`
400			`//`
401			`always @(posedge cclk or posedge internal_reset)`
402			`if (internal_reset)`
403			`COR <= 31'h00000000;`
404			`else`
405			`if (write_COR)`
406			`COR <= sr[3:0];`
407
408			`//`
409			`// 31 Bit FAR register`
410			`//`
411			`reg [31:0] FAR;`
412			`//`
413			`// Write to CMD latch value written`
414			`//`
415			`always @(posedge cclk or posedge internal_reset)`
416			`if (internal_reset)`
417			`FAR <= 31'h00000000;`
418			`else`
419			`if (write_FAR)`
420			`FAR <= sr[3:0];`
421
422
423
424
425
426			`//`
427			`// Large Block Count`
428			`//`
429
430
431			`wire write_LBC;`
432			`assign write_LBC = header_type_large_block & word_stb;`
433
434
435
436
437
438			`//`
439			`// CRC`
440			`//`
441
442			`//`
443			`//`
444			`// holds CRC as written with WCFG CRC`
445			`reg [15:0] CRC_from_cfg;`
446
447
448			`always @(posedge cclk or posedge internal_reset)`
449			`if (internal_reset)`
450			`CRC_from_cfg <= 16'h0000;`
451			`else if (write_CRC)`
452			`CRC_from_cfg[15:0] <= sr[15:0];`
453
454
455			`//assign trace_sync_found = sr[15:0] == 16'h55AA;`
456
457			`// Virtex/Spartan SYNC word`
458			`assign trace1 = cfg_state_START;`
459
460			`assign done = cfg_state_START;`
461
462			`assign trace2 =`
463			`write_LBC \|`
464			`write_CMD \|`
465			`write_COR \|`
466			`write_CRC \|`
467			`write_FLR \|`
468			`write_FAR \|`
469			`write_CTL \|`
470			`write_STAT \|`
471			`write_FDRI \|`
472
473			`write_RES_E \|`
474			`write_MASK;`
475
476
477			`endmodule`