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/** @package zGlue
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@file ioport.v
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@brief building blocks for I/O port and peripheral registers;
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for eZ80 Family host processor with 24-bit address bus.
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<BR>Simplified (2-clause) BSD License
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Copyright (c) 2012, Douglas Beattie Jr.
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All rights reserved.
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Redistribution and use in source and hardware/binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in hardware/binary form must reproduce the above
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copyright notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the distribution.
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THIS RTL SOURCE IS PROVIDED BY DOUGLAS BEATTIE JR. "AS IS" AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL DOUGLAS BEATTIE JR. BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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THIS RTL SOURCE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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Author: Douglas Beattie
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Created on: 4/12/2012 8:50:12 PM
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Last change: DBJR 4/28/2012 5:31:56 PM
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*/
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`timescale 1ns / 100ps
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module ioport_a16_d8_wo(reset_n, wr_n, data_in, ouplatched_bus);
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input reset_n, wr_n;
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input [7:0] data_in;
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output reg [7:0] ouplatched_bus;
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parameter INIT_VAL = 8'b0 ;
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always @ (posedge wr_n or negedge reset_n)
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if (! reset_n)
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ouplatched_bus <= #1 INIT_VAL;
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else if (wr_n)
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ouplatched_bus <= #1 data_in;
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endmodule
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module ioport_a16_dx_wo(reset_n, wr_n, data_in, ouplatched_bus);
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parameter NUM_BITS = 8;
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parameter INIT_VAL = 0 ;
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input reset_n, wr_n;
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input [NUM_BITS-1:0] data_in;
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output reg [NUM_BITS-1:0] ouplatched_bus;
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always @ (posedge wr_n or negedge reset_n)
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if (! reset_n)
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ouplatched_bus <= #1 INIT_VAL;
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else if (wr_n)
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ouplatched_bus <= #1 data_in;
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endmodule
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