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beattidp |
/** @package zGlue
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@file mmu180.v
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@brief Memory Management Unit, mimics classic Z180;
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for eZ80 Family host processor with 24-bit address bus.
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<BR>Simplified (2-clause) BSD License
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Copyright (c) 2012, Douglas Beattie Jr.
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All rights reserved.
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Redistribution and use in source and hardware/binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in hardware/binary form must reproduce the above
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copyright notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the distribution.
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THIS RTL SOURCE IS PROVIDED BY DOUGLAS BEATTIE JR. "AS IS" AND ANY
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EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL DOUGLAS BEATTIE JR. BE LIABLE FOR ANY
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DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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THIS RTL SOURCE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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Author: Douglas Beattie
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Created on: 4/12/2012 8:50:12 PM
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Last change: DBJR 4/27/2012 7:55:01 PM
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*/
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`timescale 1ns / 100ps
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// User-defined I/O addresses from eZ80 address bus;
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// these match the original Z180 MMU defaults at reset.
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// These must not be defined within eZ80 on-chip i/o space (7F..FF)
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`define CBR_IO_ADDR 16'h0038 // Common Bank Register
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`define BBR_IO_ADDR 16'h0039 // Bank Base Register
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`define CBAR_IO_ADDR 16'h003A // Common/Bank Address Register
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module mmu180(reset_n, en, iorq_n, mreq_n, rd_n, wr_n, phi, addr_in, dq, addr_out,
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cbar_hinyb, cbar_lonyb);
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input reset_n, en, iorq_n, mreq_n, rd_n, wr_n, phi;
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input [23:0] addr_in; //processor address bus
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inout [7:0] dq; // processor data bus
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output [19:12] addr_out; // memory address bus
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reg [7:0] cpu_data_buf;
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wire cbar_hinyb_gteq; // for CBR valid address match
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wire cbar_lonyb_gteq; // for BBR valid address match
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// These are for verification only
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output cbar_hinyb, cbar_lonyb;
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// These are for verification only
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assign cbar_hinyb = cbar_hinyb_gteq;
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assign cbar_lonyb = cbar_lonyb_gteq;
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/** *************************************************************** */
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/** define 3 I/O Ports, 1 each for CBR, BBR, and CBAR */
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wire [7:0] iolatched_oup_CBR;
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wire [7:0] iolatched_oup_BBR;
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wire [7:0] iolatched_oup_CBAR;
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/**************
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wire addr16_msb_zero;
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assign addr16_msb_zero = (addr_in[15:8] == 8'b0);
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wire iosel_CBR, iosel_BBR, iosel_CBAR;
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assign iosel_CBR = (addr16_msb_zero && (addr_in[7:0] == `CBR_IO_ADDR) && ! iorq_n && ! phi);
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assign iosel_BBR = (addr16_msb_zero && (addr_in[7:0] == `BBR_IO_ADDR) && ! iorq_n && ! phi);
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assign iosel_CBAR = (addr16_msb_zero && (addr_in[7:0] == `CBAR_IO_ADDR) && ! iorq_n && ! phi);
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********************/
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wire iosel_CBR, iosel_BBR, iosel_CBAR;
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assign iosel_CBR = ((addr_in[15:0] == `CBR_IO_ADDR) && ! iorq_n && ! phi);
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assign iosel_BBR = ((addr_in[15:0] == `BBR_IO_ADDR) && ! iorq_n && ! phi);
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assign iosel_CBAR = ((addr_in[15:0] == `CBAR_IO_ADDR) && ! iorq_n && ! phi);
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wire iosel_CBR_wr, iosel_BBR_wr, iosel_CBAR_wr;
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assign iosel_CBR_wr = ! (iosel_CBR & ! wr_n);
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assign iosel_BBR_wr = ! (iosel_BBR & ! wr_n);
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assign iosel_CBAR_wr = ! (iosel_CBAR & ! wr_n);
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assign dq = ( (iosel_CBR | iosel_BBR | iosel_CBAR) & (! rd_n)) ? cpu_data_buf : 8'bz;
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wire iosel;
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assign iosel = (! iorq_n && ! phi);
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always @ (posedge iosel)
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if (! rd_n) begin
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case (addr_in[15:0])
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`CBR_IO_ADDR: begin
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cpu_data_buf <= iolatched_oup_CBR;
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end
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`BBR_IO_ADDR: begin
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cpu_data_buf <= iolatched_oup_BBR;
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end
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`CBAR_IO_ADDR: begin
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cpu_data_buf <= iolatched_oup_CBAR;
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end
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endcase
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end
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/// define I/O port to read/write CBR
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ioport_a16_d8_wo ioport_CBR(
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.reset_n (reset_n),
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// .rd_n (iosel_CBR_rd),
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.wr_n (iosel_CBR_wr),
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.data_in (dq),
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.ouplatched_bus (iolatched_oup_CBR)
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);
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/// define I/O port to read/write BBR
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ioport_a16_d8_wo ioport_BBR(
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.reset_n (reset_n),
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// .rd_n (iosel_BBR_rd),
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.wr_n (iosel_BBR_wr),
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.data_in (dq),
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.ouplatched_bus (iolatched_oup_BBR)
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);
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/// define I/O port to read/write CBAR
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ioport_a16_d8_wo #(.INIT_VAL(8'hF0)) ioport_CBAR(
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.reset_n (reset_n),
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// .rd_n (iosel_CBAR_rd),
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.wr_n (iosel_CBAR_wr),
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.data_in (dq),
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.ouplatched_bus (iolatched_oup_CBAR)
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);
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/** **************************************************************** */
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/** define MMU compare and adder logic */
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// Compare CBAR high nybble for Common Area 1 address ("use CBR?")
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assign cbar_hinyb_gteq = (addr_in[15:12] >= iolatched_oup_CBAR[7:4]);
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// Compare CBAR low nybble for Bank Area address ("use BBR?")
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assign cbar_lonyb_gteq = (addr_in[15:12] >= iolatched_oup_CBAR[3:0]);
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wire cbar_is_valid;
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assign cbar_is_valid = (iolatched_oup_CBAR[7:4] >= iolatched_oup_CBAR[3:0]);
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wire [7:0] bbr_cbr_mux;
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assign bbr_cbr_mux =
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(cbar_is_valid & cbar_hinyb_gteq) ? iolatched_oup_CBR :
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(cbar_is_valid & cbar_lonyb_gteq) ? iolatched_oup_BBR : 8'b0;
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wire [7:0] hiaddr_1meg;
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assign hiaddr_1meg = bbr_cbr_mux + {4'b0,addr_in[15:12]};
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//define when hiaddr_1meg is to be used instead of normal a[19..12]
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assign addr_out = (/*en &&*/ (addr_in[23:16] != 0)) ?
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addr_in[19:12] : (en && (! mreq_n) && (cbar_hinyb_gteq | cbar_lonyb_gteq)) ?
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hiaddr_1meg : addr_in[19:12];// : 8'bz;
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/**
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addr_in[19:12] : (en_mmu && (! mreq_n) && (cbar_hinyb_gteq | cbar_lonyb_gteq)) ?
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hiaddr_1meg : (en_mod4 && (! mreq_n)) ? {addr_in[19:17], adj_a16, adj_a15, addr_in[14:12] }
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: addr_in[19:12];// : 8'bz;
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*/
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endmodule
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