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[/] [mod3_calc/] [trunk/] [rtl/] [mod3.v] - Blame information for rev 2

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1 2 yanzixuan 
module  mod3 (
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    input   [ 7: 0] dat_i,
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    output  [ 1: 0] reminder
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    );
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    wire    [ 1: 0] dat_1, dat_2, dat_3, dat_4;
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    wire    [ 1: 0] dat_5, dat_6;
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    type_conv TC0(
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        .plus_one(dat_i[0]),
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        .minus_one(dat_i[1]),
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        .dat_o(dat_1)
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    );
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    type_conv TC1(
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        .plus_one(dat_i[2]),
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        .minus_one(dat_i[3]),
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        .dat_o(dat_2)
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    );
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    type_conv TC2(
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        .plus_one(dat_i[4]),
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        .minus_one(dat_i[5]),
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        .dat_o(dat_3)
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    );
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    type_conv TC3(
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        .plus_one(dat_i[6]),
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        .minus_one(dat_i[7]),
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        .dat_o(dat_4)
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    );
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    mod3_adder MA0(
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        .din_a(dat_1), .din_b(dat_2),
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        .dat_o(dat_5)
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    );
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    mod3_adder MA1(
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        .din_a(dat_3), .din_b(dat_4),
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        .dat_o(dat_6)
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    );
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    mod3_adder MA3(
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        .din_a(dat_5), .din_b(dat_6),
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        .dat_o(reminder)
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    );
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endmodule
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//convert to signed data
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module  type_conv (
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    input   plus_one,
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            minus_one,
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    output  reg [ 1: 0] dat_o
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    );
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    always@(*)  begin
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        case ({plus_one, minus_one})
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            2'b00   :   dat_o   = 2'b00;
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            2'b01   :   dat_o   = 2'b10;
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            2'b10   :   dat_o   = 2'b01;
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            2'b11   :   dat_o   = 2'b00;
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            default :   dat_o   = 2'b00;
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        endcase
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    end
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endmodule
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//a qucik mod3 adder
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module  mod3_adder (
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    input   [ 1: 0] din_a, din_b,
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    output  reg [ 1: 0] dat_o
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    );
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    always@(*)  begin
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        case ({din_a, din_b})
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            4'b00_00    :   dat_o   = 2'b00;
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            4'b00_01    :   dat_o   = 2'b01;
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            4'b00_10    :   dat_o   = 2'b10;
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            4'b01_00    :   dat_o   = 2'b01;
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            4'b01_01    :   dat_o   = 2'b10;
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            4'b01_10    :   dat_o   = 2'b00;
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            4'b10_00    :   dat_o   = 2'b10;
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            4'b10_01    :   dat_o   = 2'b00;
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            4'b10_10    :   dat_o   = 2'b01;
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            default     :   dat_o   = 2'b00;
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        endcase
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    end
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endmodule
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