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[/] [mod_mult_exp/] [trunk/] [rtl/] [vhdl/] [commons/] [AsyncMux.vhd] - Blame information for rev 6

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1 6 gajos
-----------------------------------------------------------------------
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----                                                               ----
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---- Montgomery modular multiplier and exponentiator               ----
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----                                                               ----
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---- This file is part of the Montgomery modular multiplier        ----
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---- and exponentiator project                                     ----
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---- http://opencores.org/project,mod_mult_exp                     ----
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----                                                               ----
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---- Description:                                                  ----
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----     Asynchronous multiplexer - nothing special.               ----
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---- To Do:                                                        ----
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----                                                               ----
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---- Author(s):                                                    ----
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---- - Krzysztof Gajewski, gajos@opencores.org                     ----
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----                       k.gajewski@gmail.com                    ----
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----                                                               ----
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-----------------------------------------------------------------------
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----                                                               ----
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---- Copyright (C) 2014 Authors and OPENCORES.ORG                  ----
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----                                                               ----
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---- This source file may be used and distributed without          ----
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---- restriction provided that this copyright statement is not     ----
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---- removed from the file and that any derivative work contains   ----
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---- the original copyright notice and the associated disclaimer.  ----
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----                                                               ----
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---- This source file is free software; you can redistribute it    ----
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---- and-or modify it under the terms of the GNU Lesser General    ----
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---- Public License as published by the Free Software Foundation;  ----
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---- either version 2.1 of the License, or (at your option) any    ----
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---- later version.                                                ----
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----                                                               ----
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---- This source is distributed in the hope that it will be        ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied    ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR       ----
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---- PURPOSE. See the GNU Lesser General Public License for more   ----
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---- details.                                                      ----
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----                                                               ----
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---- You should have received a copy of the GNU Lesser General     ----
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---- Public License along with this source; if not, download it    ----
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---- from http://www.opencores.org/lgpl.shtml                      ----
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----                                                               ----
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use work.properties.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity AsyncMux is
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    generic (
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             word_size : integer := WORD_LENGTH
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         );
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    port (
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             input0 : in  STD_LOGIC_VECTOR(word_size downto 0);
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        input1 : in  STD_LOGIC_VECTOR(word_size downto 0);
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                  ctrl   : in  STD_LOGIC;
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                  output : out STD_LOGIC_VECTOR(word_size downto 0)
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          );
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end AsyncMux;
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architecture Behavioral of AsyncMux is
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begin
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    output <= input0 when (ctrl = '0') else
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                   input1;
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end Behavioral;
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