1 |
5 |
gajos |
|
2 |
|
|
--------------------------------------------------------------------------------
|
3 |
|
|
--
|
4 |
|
|
-- BLK MEM GEN v7_1 Core - Address Generator
|
5 |
|
|
--
|
6 |
|
|
--------------------------------------------------------------------------------
|
7 |
|
|
--
|
8 |
|
|
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
|
9 |
|
|
--
|
10 |
|
|
-- This file contains confidential and proprietary information
|
11 |
|
|
-- of Xilinx, Inc. and is protected under U.S. and
|
12 |
|
|
-- international copyright and other intellectual property
|
13 |
|
|
-- laws.
|
14 |
|
|
--
|
15 |
|
|
-- DISCLAIMER
|
16 |
|
|
-- This disclaimer is not a license and does not grant any
|
17 |
|
|
-- rights to the materials distributed herewith. Except as
|
18 |
|
|
-- otherwise provided in a valid license issued to you by
|
19 |
|
|
-- Xilinx, and to the maximum extent permitted by applicable
|
20 |
|
|
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
21 |
|
|
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
22 |
|
|
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
23 |
|
|
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
24 |
|
|
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
25 |
|
|
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
26 |
|
|
-- including negligence, or under any other theory of
|
27 |
|
|
-- liability) for any loss or damage of any kind or nature
|
28 |
|
|
-- related to, arising under or in connection with these
|
29 |
|
|
-- materials, including for any direct, or any indirect,
|
30 |
|
|
-- special, incidental, or consequential loss or damage
|
31 |
|
|
-- (including loss of data, profits, goodwill, or any type of
|
32 |
|
|
-- loss or damage suffered as a result of any action brought
|
33 |
|
|
-- by a third party) even if such damage or loss was
|
34 |
|
|
-- reasonably foreseeable or Xilinx had been advised of the
|
35 |
|
|
-- possibility of the same.
|
36 |
|
|
--
|
37 |
|
|
-- CRITICAL APPLICATIONS
|
38 |
|
|
-- Xilinx products are not designed or intended to be fail-
|
39 |
|
|
-- safe, or for use in any application requiring fail-safe
|
40 |
|
|
-- performance, such as life-support or safety devices or
|
41 |
|
|
-- systems, Class III medical devices, nuclear facilities,
|
42 |
|
|
-- applications related to the deployment of airbags, or any
|
43 |
|
|
-- other applications that could lead to death, personal
|
44 |
|
|
-- injury, or severe property or environmental damage
|
45 |
|
|
-- (individually and collectively, "Critical
|
46 |
|
|
-- Applications"). Customer assumes the sole risk and
|
47 |
|
|
-- liability of any use of Xilinx products in Critical
|
48 |
|
|
-- Applications, subject only to applicable laws and
|
49 |
|
|
-- regulations governing limitations on product liability.
|
50 |
|
|
--
|
51 |
|
|
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
52 |
|
|
-- PART OF THIS FILE AT ALL TIMES.
|
53 |
|
|
|
54 |
|
|
--------------------------------------------------------------------------------
|
55 |
|
|
--
|
56 |
|
|
-- Filename: addr_gen.vhd
|
57 |
|
|
--
|
58 |
|
|
-- Description:
|
59 |
|
|
-- Address Generator
|
60 |
|
|
--
|
61 |
|
|
--------------------------------------------------------------------------------
|
62 |
|
|
-- Author: IP Solutions Division
|
63 |
|
|
--
|
64 |
|
|
-- History: Sep 12, 2011 - First Release
|
65 |
|
|
--------------------------------------------------------------------------------
|
66 |
|
|
--
|
67 |
|
|
--------------------------------------------------------------------------------
|
68 |
|
|
-- Library Declarations
|
69 |
|
|
--------------------------------------------------------------------------------
|
70 |
|
|
|
71 |
|
|
LIBRARY IEEE;
|
72 |
|
|
USE IEEE.STD_LOGIC_1164.ALL;
|
73 |
|
|
USE IEEE.STD_LOGIC_ARITH.ALL;
|
74 |
|
|
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
|
75 |
|
|
|
76 |
|
|
LIBRARY work;
|
77 |
|
|
USE work.ALL;
|
78 |
|
|
|
79 |
|
|
ENTITY ADDR_GEN IS
|
80 |
|
|
GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ;
|
81 |
|
|
RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0');
|
82 |
|
|
RST_INC : INTEGER := 0);
|
83 |
|
|
PORT (
|
84 |
|
|
CLK : IN STD_LOGIC;
|
85 |
|
|
RST : IN STD_LOGIC;
|
86 |
|
|
EN : IN STD_LOGIC;
|
87 |
|
|
LOAD :IN STD_LOGIC;
|
88 |
|
|
LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
|
89 |
|
|
ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR
|
90 |
|
|
);
|
91 |
|
|
END ADDR_GEN;
|
92 |
|
|
|
93 |
|
|
ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS
|
94 |
|
|
SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0');
|
95 |
|
|
BEGIN
|
96 |
|
|
ADDR_OUT <= ADDR_TEMP;
|
97 |
|
|
PROCESS(CLK)
|
98 |
|
|
BEGIN
|
99 |
|
|
IF(RISING_EDGE(CLK)) THEN
|
100 |
|
|
IF(RST='1') THEN
|
101 |
|
|
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
|
102 |
|
|
ELSE
|
103 |
|
|
IF(EN='1') THEN
|
104 |
|
|
IF(LOAD='1') THEN
|
105 |
|
|
ADDR_TEMP <=LOAD_VALUE;
|
106 |
|
|
ELSE
|
107 |
|
|
IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN
|
108 |
|
|
ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 );
|
109 |
|
|
ELSE
|
110 |
|
|
ADDR_TEMP <= ADDR_TEMP + '1';
|
111 |
|
|
END IF;
|
112 |
|
|
END IF;
|
113 |
|
|
END IF;
|
114 |
|
|
END IF;
|
115 |
|
|
END IF;
|
116 |
|
|
END PROCESS;
|
117 |
|
|
END ARCHITECTURE;
|